* [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
@ 2023-11-21 19:43 Robin Dapp
2023-11-22 1:08 ` juzhe.zhong
0 siblings, 1 reply; 4+ messages in thread
From: Robin Dapp @ 2023-11-21 19:43 UTC (permalink / raw)
To: gcc-patches, palmer, Kito Cheng, jeffreyalaw, juzhe.zhong; +Cc: rdapp.gcc
Hi,
this removes the now-redundant vector_hw and zvfh_hw checks in the
testsuite.
Regards
Robin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c:
Remove zvfh_hw.
* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c:
Ditto.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c:
Ditto.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Allow
overriding N.
* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Remove
zvfh_hw.
* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Ditto.
* lib/target-supports.exp: Ditto.
---
.../rvv/autovec/binop/copysign-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vadd-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vdiv-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmax-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmin-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmul-zvfh-run.c | 2 +-
.../rvv/autovec/cond/cond_copysign-zvfh-run.c | 2 +-
.../rvv/autovec/struct/struct_vect_run-10.c | 5 +-
.../rvv/autovec/struct/struct_vect_run-6.c | 2 +
.../riscv/rvv/autovec/unop/abs-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/unop/vneg-zvfh-run.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-1.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-10.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-11.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-12.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-2.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-3.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-5.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-6.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-7.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-8.c | 2 +-
gcc/testsuite/lib/target-supports.exp | 51 +------------------
22 files changed, 26 insertions(+), 70 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
index 3bf64ab72ef..e71b6589fc3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
index 2a8618ad09b..6c2d096e103 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
index 1b8e69259ca..c9f9d83ccb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
index ea9455ae059..85e19c1ff43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vmax-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
index 7be92f5c82d..b24d4f3cb16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vmin-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
index 1082695c5de..63bcf707756 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
index bdf6eed1c78..79a51307034 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "cond_copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
index 79037048f55..17c734bb657 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
@@ -1,6 +1,9 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
#define TYPE _Float16
#define ITYPE int16_t
+
+/* Use a lower iteration count so we do not run into precision problems. */
+#define N 62
#include "struct_vect_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
index c096888398d..c836bcddb7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
@@ -3,7 +3,9 @@
#include "struct_vect-6.c"
+#ifndef N
#define N 93
+#endif
TYPE a[N], b[N], c[N], d[N], a2[N], b2[N], c2[N], d2[N], e[N * 8];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
index 65087d51665..f0c00de9f8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "abs-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
index 64c965fea1a..38c8c7ae83d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vneg-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
index 5661252a0ae..41c573460d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
index 1fcd8362ce8..99ceef0f0ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
index 8e73095bc12..cec71f91210 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
index 6f04595ae99..4afdcba522d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
index a3ddeb0b3ad..ffb8d7f6ec4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
index 47a1803a328..5c23112019e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
index a5eb47601fd..a91a51622a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
index 046d471ae30..5b7f000944e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
index d10017c6901..f01efa350d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
index 2b945f9ef53..ed79ac88717 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 87b2ae58720..06c8bf4c138 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1823,55 +1823,6 @@ proc check_linker_plugin_available { } {
} "-flto -fuse-linker-plugin"]
}
-# Return 1 if the we can build a vector example with proper -march flags
-# and the current target can execute it, 0 otherwise. Cache the result.
-
-proc check_effective_target_riscv_vector_hw { } {
-
- return [check_runtime riscv_vector_hw32 {
- int main (void)
- {
- asm ("vsetivli zero,8,e16,m1,ta,ma");
- asm ("vadd.vv v8,v8,v16" : : : "v8");
- return 0;
- }
- } ""] || [check_runtime riscv_vector_hw64 {
- int main (void)
- {
- asm ("vsetivli zero,8,e16,m1,ta,ma");
- asm ("vadd.vv v8,v8,v16" : : : "v8");
- return 0;
- }
- } ""]
-}
-
-# Return 1 if the we can build a Zvfh vector example with proper -march flags
-# and the current target can execute it, 0 otherwise. Cache the result.
-
-proc check_effective_target_riscv_zvfh_hw { } {
- if ![check_effective_target_riscv_vector_hw] then {
- return 0
- }
-
- return [check_runtime riscv_zvfh_hw32 {
- int main (void)
- {
- asm ("vsetivli zero,8,e16,m1,ta,ma");
- asm ("vfadd.vv v8,v8,v16" : : : "v8");
- return 0;
- }
- } "-march=rv32gcv_zvfh -mabi=ilp32d"]
- || [check_runtime riscv_zvfh_hw64 {
- int main (void)
- {
- asm ("vsetivli zero,8,e16,m1,ta,ma");
- asm ("vfadd.vv v8,v8,v16" : : : "v8");
- return 0;
- }
- } "-march=rv64gcv_zvfh -mabi=lp64d"]
-}
-
-
# Return 1 if the target is RV32, 0 otherwise. Cache the result.
proc check_effective_target_rv32 { } {
@@ -11574,7 +11525,7 @@ proc check_vect_support_and_set_flags { } {
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
} elseif [istarget riscv64-*-*] {
- if [check_effective_target_riscv_vector_hw] {
+ if [check_effective_target_riscv_v] {
lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
set dg-do-what-default run
} else {
--
2.42.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
2023-11-21 19:43 [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw Robin Dapp
@ 2023-11-22 1:08 ` juzhe.zhong
2023-11-22 6:03 ` Robin Dapp
0 siblings, 1 reply; 4+ messages in thread
From: juzhe.zhong @ 2023-11-22 1:08 UTC (permalink / raw)
To: Robin Dapp, gcc-patches, palmer, kito.cheng, jeffreyalaw; +Cc: Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 18204 bytes --]
I don't get it. Why do we need remove them ?
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2023-11-22 03:43
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zhong@rivai.ai
CC: rdapp.gcc
Subject: [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
Hi,
this removes the now-redundant vector_hw and zvfh_hw checks in the
testsuite.
Regards
Robin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c:
Remove zvfh_hw.
* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c:
Ditto.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c:
Ditto.
* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Allow
overriding N.
* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Remove
zvfh_hw.
* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Ditto.
* lib/target-supports.exp: Ditto.
---
.../rvv/autovec/binop/copysign-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vadd-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vdiv-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmax-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmin-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/binop/vmul-zvfh-run.c | 2 +-
.../rvv/autovec/cond/cond_copysign-zvfh-run.c | 2 +-
.../rvv/autovec/struct/struct_vect_run-10.c | 5 +-
.../rvv/autovec/struct/struct_vect_run-6.c | 2 +
.../riscv/rvv/autovec/unop/abs-zvfh-run.c | 2 +-
.../riscv/rvv/autovec/unop/vneg-zvfh-run.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-1.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-10.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-11.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-12.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-2.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-3.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-5.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-6.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-7.c | 2 +-
.../rvv/autovec/widen/widen_run_zvfh-8.c | 2 +-
gcc/testsuite/lib/target-supports.exp | 51 +------------------
22 files changed, 26 insertions(+), 70 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
index 3bf64ab72ef..e71b6589fc3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
index 2a8618ad09b..6c2d096e103 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
index 1b8e69259ca..c9f9d83ccb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
index ea9455ae059..85e19c1ff43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vmax-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
index 7be92f5c82d..b24d4f3cb16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vmin-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
index 1082695c5de..63bcf707756 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
index bdf6eed1c78..79a51307034 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "cond_copysign-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
index 79037048f55..17c734bb657 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
@@ -1,6 +1,9 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
#define TYPE _Float16
#define ITYPE int16_t
+
+/* Use a lower iteration count so we do not run into precision problems. */
+#define N 62
#include "struct_vect_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
index c096888398d..c836bcddb7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
@@ -3,7 +3,9 @@
#include "struct_vect-6.c"
+#ifndef N
#define N 93
+#endif
TYPE a[N], b[N], c[N], d[N], a2[N], b2[N], c2[N], d2[N], e[N * 8];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
index 65087d51665..f0c00de9f8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "abs-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
index 64c965fea1a..38c8c7ae83d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
#include "vneg-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
index 5661252a0ae..41c573460d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
index 1fcd8362ce8..99ceef0f0ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
index 8e73095bc12..cec71f91210 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
index 6f04595ae99..4afdcba522d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
index a3ddeb0b3ad..ffb8d7f6ec4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
index 47a1803a328..5c23112019e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
index a5eb47601fd..a91a51622a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
index 046d471ae30..5b7f000944e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
index d10017c6901..f01efa350d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
index 2b945f9ef53..ed79ac88717 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v && riscv_zvfh_hw } } } */
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
#include <assert.h>
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 87b2ae58720..06c8bf4c138 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1823,55 +1823,6 @@ proc check_linker_plugin_available { } {
} "-flto -fuse-linker-plugin"]
}
-# Return 1 if the we can build a vector example with proper -march flags
-# and the current target can execute it, 0 otherwise. Cache the result.
-
-proc check_effective_target_riscv_vector_hw { } {
-
- return [check_runtime riscv_vector_hw32 {
- int main (void)
- {
- asm ("vsetivli zero,8,e16,m1,ta,ma");
- asm ("vadd.vv v8,v8,v16" : : : "v8");
- return 0;
- }
- } ""] || [check_runtime riscv_vector_hw64 {
- int main (void)
- {
- asm ("vsetivli zero,8,e16,m1,ta,ma");
- asm ("vadd.vv v8,v8,v16" : : : "v8");
- return 0;
- }
- } ""]
-}
-
-# Return 1 if the we can build a Zvfh vector example with proper -march flags
-# and the current target can execute it, 0 otherwise. Cache the result.
-
-proc check_effective_target_riscv_zvfh_hw { } {
- if ![check_effective_target_riscv_vector_hw] then {
- return 0
- }
-
- return [check_runtime riscv_zvfh_hw32 {
- int main (void)
- {
- asm ("vsetivli zero,8,e16,m1,ta,ma");
- asm ("vfadd.vv v8,v8,v16" : : : "v8");
- return 0;
- }
- } "-march=rv32gcv_zvfh -mabi=ilp32d"]
- || [check_runtime riscv_zvfh_hw64 {
- int main (void)
- {
- asm ("vsetivli zero,8,e16,m1,ta,ma");
- asm ("vfadd.vv v8,v8,v16" : : : "v8");
- return 0;
- }
- } "-march=rv64gcv_zvfh -mabi=lp64d"]
-}
-
-
# Return 1 if the target is RV32, 0 otherwise. Cache the result.
proc check_effective_target_rv32 { } {
@@ -11574,7 +11525,7 @@ proc check_vect_support_and_set_flags { } {
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
} elseif [istarget riscv64-*-*] {
- if [check_effective_target_riscv_vector_hw] {
+ if [check_effective_target_riscv_v] {
lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
set dg-do-what-default run
} else {
--
2.42.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
2023-11-22 1:08 ` juzhe.zhong
@ 2023-11-22 6:03 ` Robin Dapp
2023-11-22 6:09 ` juzhe.zhong
0 siblings, 1 reply; 4+ messages in thread
From: Robin Dapp @ 2023-11-22 6:03 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches, palmer, kito.cheng, jeffreyalaw; +Cc: rdapp.gcc
> I don't get it. Why do we need remove them ?
It's just replaced by riscv_zvfh. I should probably edit the
patch description and changelog entries to make it clearer.
Regards
Robin
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Re: [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
2023-11-22 6:03 ` Robin Dapp
@ 2023-11-22 6:09 ` juzhe.zhong
0 siblings, 0 replies; 4+ messages in thread
From: juzhe.zhong @ 2023-11-22 6:09 UTC (permalink / raw)
To: Robin Dapp, gcc-patches, palmer, kito.cheng, jeffreyalaw; +Cc: Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 451 bytes --]
LGTM。
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2023-11-22 14:03
To: juzhe.zhong@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
> I don't get it. Why do we need remove them ?
It's just replaced by riscv_zvfh. I should probably edit the
patch description and changelog entries to make it clearer.
Regards
Robin
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-11-22 6:09 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-21 19:43 [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw Robin Dapp
2023-11-22 1:08 ` juzhe.zhong
2023-11-22 6:03 ` Robin Dapp
2023-11-22 6:09 ` juzhe.zhong
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