[PATCH 3/4] RISC-V: Add not broken RW prefetch RTL instructions without offsets

[Tsukasa OI <research_trasio@irq.a4lg.com>]

From: Tsukasa OI <research_trasio@irq.a4lg.com>

To prepare adding new not broken prefetch built-in functions and fixing
an ICE in __builtin_prefetch, this commit adds two new instructions,
each corresponding a 'Zicbop' prefetch hint instruction, but with no
specifiable offset field for simplicity.

This commit also excludes new instruction corresponding "prefetch.i"
because it is not needed to fix an ICE (so new instruction corresponding
"prefetch.i" is going to be a separate commit).

gcc/ChangeLog:

	* config/riscv/riscv.md (unspecv) Add UNSPECV_PREFETCH_[RW].
	(riscv_prefetch_w_<mode>, riscv_prefetch_w_<mode>): New.
---
 gcc/config/riscv/riscv.md | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4b445cb8be9c..e67a6d1f1b81 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -118,6 +118,8 @@
   UNSPECV_FLUSH
   UNSPECV_INVAL
   UNSPECV_ZERO
+  UNSPECV_PREFETCH_R
+  UNSPECV_PREFETCH_W
 
   ;; Zihintpause unspec
   UNSPECV_PAUSE
@@ -3492,6 +3494,20 @@
 }
   [(set_attr "type" "cbo")])
 
+(define_insn "riscv_prefetch_r_<mode>"
+  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+		       UNSPECV_PREFETCH_R)]
+  "TARGET_ZICBOP"
+  "prefetch.r\t0(%0)"
+  [(set_attr "type" "cbo")])
+
+(define_insn "riscv_prefetch_w_<mode>"
+  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+		       UNSPECV_PREFETCH_W)]
+  "TARGET_ZICBOP"
+  "prefetch.w\t0(%0)"
+  [(set_attr "type" "cbo")])
+
 (define_expand "extv<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=r")
 	(sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
-- 
2.42.0