* [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities
2023-10-23 7:22 [PATCH 0/4] RISC-V: Fix 'Zicbop'-related bugs (fix ICE and remove broken built-in) Tsukasa OI
@ 2023-10-23 7:22 ` Tsukasa OI
2023-10-30 21:57 ` Jeff Law
2023-10-23 7:22 ` [PATCH 2/4] RISC-V: Remove broken __builtin_riscv_zicbop_cbo_prefetchi Tsukasa OI
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Tsukasa OI @ 2023-10-23 7:22 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Because they are for all prefetch instructions, "prefetch" fits better
than "prefetchi".
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc: Rename availabilities
"prefetchi{32,64}" to "prefetch{32,64}".
* config/riscv/riscv-cmo.def
(__builtin_riscv_zicbop_cbo_prefetchi):
Reflect availability name changes.
---
gcc/config/riscv/riscv-builtins.cc | 4 ++--
gcc/config/riscv/riscv-cmo.def | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba12..ce549eb3782d 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -103,8 +103,8 @@ AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT)
AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT)
AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT)
AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT)
-AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
-AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (prefetch32, TARGET_ZICBOP && !TARGET_64BIT)
+AVAIL (prefetch64, TARGET_ZICBOP && TARGET_64BIT)
AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index ff713b78e19e..017370d1d0e3 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -13,8 +13,8 @@ RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV
RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, zero64),
// zicbop
-RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, prefetchi32),
-RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetchi64),
+RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, prefetch32),
+RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetch64),
// zbkc or zbc
RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
--
2.42.0
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities
2023-10-23 7:22 ` [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities Tsukasa OI
@ 2023-10-30 21:57 ` Jeff Law
2023-10-31 1:17 ` Kito Cheng
0 siblings, 1 reply; 7+ messages in thread
From: Jeff Law @ 2023-10-30 21:57 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman, Jim Wilson
Cc: gcc-patches
On 10/23/23 01:22, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> Because they are for all prefetch instructions, "prefetch" fits better
> than "prefetchi".
But there's a significant difference between the cases. prefetch.i in
particular fetches into the icache. While prefetch.r and prefetch.w
would fetch into the data cache.
And I strongly suspect from an API standpoint we'll want to distinguish
each case from the others.
Unless Kito feels otherwise I would suggest keeping a distinct API
interface for each case.
Jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/4] RISC-V: Remove broken __builtin_riscv_zicbop_cbo_prefetchi
2023-10-23 7:22 [PATCH 0/4] RISC-V: Fix 'Zicbop'-related bugs (fix ICE and remove broken built-in) Tsukasa OI
2023-10-23 7:22 ` [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities Tsukasa OI
@ 2023-10-23 7:22 ` Tsukasa OI
2023-10-23 7:22 ` [PATCH 3/4] RISC-V: Add not broken RW prefetch RTL instructions without offsets Tsukasa OI
2023-10-23 7:22 ` [PATCH 4/4] RISC-V: Fix ICE by expansion and register coercion Tsukasa OI
3 siblings, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2023-10-23 7:22 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
From: Tsukasa OI <research_trasio@irq.a4lg.com>
__builtin_riscv_zicbop_cbo_prefetchi (corresponding "prefetch.i"
instruction from the 'Zicbop' extension) is completely broken (not even
functional) and should be removed rather than fixing it because it has
no good way to "fix" this built-in function.
gcc/ChangeLog:
* config/riscv/riscv-cmo.def
(__builtin_riscv_zicbop_cbo_prefetchi): Remove since it's broken.
* config/riscv/riscv.md
(unspecv) Remove UNSPECV_PREI.
(riscv_prefetchi_<mode>): Remove.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbop-1.c: Remove references to
__builtin_riscv_zicbop_cbo_prefetchi.
* gcc.target/riscv/cmo-zicbop-2.c: Ditto with minor tidying.
---
gcc/config/riscv/riscv-cmo.def | 4 ----
gcc/config/riscv/riscv.md | 9 ---------
gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 6 ------
gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 8 +-------
4 files changed, 1 insertion(+), 26 deletions(-)
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index 017370d1d0e3..dbd5d2f0d9eb 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -12,10 +12,6 @@ RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT_NO_TARGET, RIS
RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, zero32),
RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, zero64),
-// zicbop
-RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, prefetch32),
-RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetch64),
-
// zbkc or zbc
RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 23d91331290b..4b445cb8be9c 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -118,7 +118,6 @@
UNSPECV_FLUSH
UNSPECV_INVAL
UNSPECV_ZERO
- UNSPECV_PREI
;; Zihintpause unspec
UNSPECV_PAUSE
@@ -3493,14 +3492,6 @@
}
[(set_attr "type" "cbo")])
-(define_insn "riscv_prefetchi_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
- (match_operand:X 1 "imm5_operand" "i")]
- UNSPECV_PREI)]
- "TARGET_ZICBOP"
- "prefetch.i\t%a0"
- [(set_attr "type" "cbo")])
-
(define_expand "extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
index c5d78c1763d3..54b764fb7452 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
@@ -13,11 +13,5 @@ void foo (char *p)
__builtin_prefetch (p, 1, 3);
}
-int foo1()
-{
- return __builtin_riscv_zicbop_cbo_prefetchi(1);
-}
-
-/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
index 6576365b39ca..917adc8f2008 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
@@ -13,11 +13,5 @@ void foo (char *p)
__builtin_prefetch (p, 1, 3);
}
-int foo1()
-{
- return __builtin_riscv_zicbop_cbo_prefetchi(1);
-}
-
-/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
-/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
--
2.42.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 3/4] RISC-V: Add not broken RW prefetch RTL instructions without offsets
2023-10-23 7:22 [PATCH 0/4] RISC-V: Fix 'Zicbop'-related bugs (fix ICE and remove broken built-in) Tsukasa OI
2023-10-23 7:22 ` [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities Tsukasa OI
2023-10-23 7:22 ` [PATCH 2/4] RISC-V: Remove broken __builtin_riscv_zicbop_cbo_prefetchi Tsukasa OI
@ 2023-10-23 7:22 ` Tsukasa OI
2023-10-23 7:22 ` [PATCH 4/4] RISC-V: Fix ICE by expansion and register coercion Tsukasa OI
3 siblings, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2023-10-23 7:22 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
From: Tsukasa OI <research_trasio@irq.a4lg.com>
To prepare adding new not broken prefetch built-in functions and fixing
an ICE in __builtin_prefetch, this commit adds two new instructions,
each corresponding a 'Zicbop' prefetch hint instruction, but with no
specifiable offset field for simplicity.
This commit also excludes new instruction corresponding "prefetch.i"
because it is not needed to fix an ICE (so new instruction corresponding
"prefetch.i" is going to be a separate commit).
gcc/ChangeLog:
* config/riscv/riscv.md (unspecv) Add UNSPECV_PREFETCH_[RW].
(riscv_prefetch_w_<mode>, riscv_prefetch_w_<mode>): New.
---
gcc/config/riscv/riscv.md | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4b445cb8be9c..e67a6d1f1b81 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -118,6 +118,8 @@
UNSPECV_FLUSH
UNSPECV_INVAL
UNSPECV_ZERO
+ UNSPECV_PREFETCH_R
+ UNSPECV_PREFETCH_W
;; Zihintpause unspec
UNSPECV_PAUSE
@@ -3492,6 +3494,20 @@
}
[(set_attr "type" "cbo")])
+(define_insn "riscv_prefetch_r_<mode>"
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ UNSPECV_PREFETCH_R)]
+ "TARGET_ZICBOP"
+ "prefetch.r\t0(%0)"
+ [(set_attr "type" "cbo")])
+
+(define_insn "riscv_prefetch_w_<mode>"
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ UNSPECV_PREFETCH_W)]
+ "TARGET_ZICBOP"
+ "prefetch.w\t0(%0)"
+ [(set_attr "type" "cbo")])
+
(define_expand "extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
--
2.42.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 4/4] RISC-V: Fix ICE by expansion and register coercion
2023-10-23 7:22 [PATCH 0/4] RISC-V: Fix 'Zicbop'-related bugs (fix ICE and remove broken built-in) Tsukasa OI
` (2 preceding siblings ...)
2023-10-23 7:22 ` [PATCH 3/4] RISC-V: Add not broken RW prefetch RTL instructions without offsets Tsukasa OI
@ 2023-10-23 7:22 ` Tsukasa OI
3 siblings, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2023-10-23 7:22 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
From: Tsukasa OI <research_trasio@irq.a4lg.com>
A "prefetch" instruction on RISC-V GCC emits a machine hint instruction
directly when the 'Zicbop' extension is enabled but it could cause an ICE
when the address argument of __builtin_prefetch is an integral constant
(such like 0 [NULL] or some other [but possibly not all] fixed addresses).
This is caused by the fact that the "r" constraint is not actually checked
and something other than a register can be the first argument of the
"prefetch" RTL instruction.
It fixes the problem by changing "prefetch" from a native instruction to
an expansion and coercing the address to a register there.
gcc/ChangeLog:
* config/riscv/riscv.md (prefetch): Expand to a native prefetch
instruction instead of emitting a machine instruction directly.
Coerce the address argument into a register.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbop-by-common-ice-1.c: New ICE test.
* gcc.target/riscv/cmo-zicbop-by-common-ice-2.c: Ditto.
---
gcc/config/riscv/riscv.md | 43 ++++++++++++-------
.../riscv/cmo-zicbop-by-common-ice-1.c | 13 ++++++
.../riscv/cmo-zicbop-by-common-ice-2.c | 7 +++
3 files changed, 48 insertions(+), 15 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index e67a6d1f1b81..bf232345b1ab 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3479,21 +3479,6 @@
[(set_attr "type" "cbo")]
)
-(define_insn "prefetch"
- [(prefetch (match_operand 0 "address_operand" "r")
- (match_operand 1 "imm5_operand" "i")
- (match_operand 2 "const_int_operand" "n"))]
- "TARGET_ZICBOP"
-{
- switch (INTVAL (operands[1]))
- {
- case 0: return "prefetch.r\t%a0";
- case 1: return "prefetch.w\t%a0";
- default: gcc_unreachable ();
- }
-}
- [(set_attr "type" "cbo")])
-
(define_insn "riscv_prefetch_r_<mode>"
[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
UNSPECV_PREFETCH_R)]
@@ -3508,6 +3493,34 @@
"prefetch.w\t0(%0)"
[(set_attr "type" "cbo")])
+(define_expand "prefetch"
+ [(prefetch (match_operand 0 "address_operand" "")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))]
+ "TARGET_ZICBOP"
+{
+ operands[0] = force_reg (Pmode, operands[0]);
+ switch (INTVAL (operands[1]))
+ {
+ case 0:
+ if (TARGET_64BIT)
+ emit_insn (gen_riscv_prefetch_r_di (operands[0]));
+ else
+ emit_insn (gen_riscv_prefetch_r_si (operands[0]));
+ break;
+ case 1:
+ if (TARGET_64BIT)
+ emit_insn (gen_riscv_prefetch_w_di (operands[0]));
+ else
+ emit_insn (gen_riscv_prefetch_w_si (operands[0]));
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ DONE;
+}
+ [(set_attr "type" "cbo")])
+
(define_expand "extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c
new file mode 100644
index 000000000000..47e83f29cc5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zicbop -mabi=ilp32" } */
+
+void foo (void)
+{
+ /* Second argument defaults to zero (read). */
+ __builtin_prefetch (0);
+ __builtin_prefetch (0, 0);
+ __builtin_prefetch (0, 1);
+}
+
+/* { dg-final { scan-assembler-times "prefetch\\.r" 2 } } */
+/* { dg-final { scan-assembler-times "prefetch\\.w" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c
new file mode 100644
index 000000000000..a245b8163c1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zicbop -mabi=lp64" } */
+
+#include "cmo-zicbop-by-common-ice-1.c"
+
+/* { dg-final { scan-assembler-times "prefetch\\.r" 2 } } */
+/* { dg-final { scan-assembler-times "prefetch\\.w" 1 } } */
--
2.42.0
^ permalink raw reply [flat|nested] 7+ messages in thread