* [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction
@ 2023-05-31 10:47 juzhe.zhong
2023-05-31 13:02 ` Jeff Law
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-05-31 10:47 UTC (permalink / raw)
To: gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc,
Juzhe-Zhong
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
gcc/ChangeLog:
* config/riscv/vector.md: Remove FRM.
---
gcc/config/riscv/vector.md | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3c4565dc775..cd41ebbb24f 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7286,10 +7286,8 @@
(match_operand 5 "const_int_operand" " i, i, i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)
- (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:<V_DOUBLE_TRUNC>
[(float_truncate:<V_DOUBLE_TRUNC>
(match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
--
2.36.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction
2023-05-31 10:47 [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction juzhe.zhong
@ 2023-05-31 13:02 ` Jeff Law
2023-05-31 13:51 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Jeff Law @ 2023-05-31 13:02 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, rdapp.gcc
On 5/31/23 04:47, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Remove FRM.
OK
jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction
2023-05-31 13:02 ` Jeff Law
@ 2023-05-31 13:51 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-05-31 13:51 UTC (permalink / raw)
To: Jeff Law, juzhe.zhong, gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, rdapp.gcc
Committed, thanks Jeff.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches
Sent: Wednesday, May 31, 2023 9:02 PM
To: juzhe.zhong@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com; kito.cheng@sifive.com; palmer@dabbelt.com; palmer@rivosinc.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction
On 5/31/23 04:47, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Remove FRM.
OK
jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-05-31 10:47 [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction juzhe.zhong
2023-05-31 13:02 ` Jeff Law
2023-05-31 13:51 ` Li, Pan2
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