* [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores
@ 2023-10-31 0:49 Patrick O'Neill
2023-10-31 0:49 ` [PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns Patrick O'Neill
2023-10-31 13:05 ` [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores Jeff Law
0 siblings, 2 replies; 6+ messages in thread
From: Patrick O'Neill @ 2023-10-31 0:49 UTC (permalink / raw)
To: gcc-patches; +Cc: Patrick O'Neill
Non-atomic targets are currently prevented from using the optimized fencing for
seq_cst load/seq_cst store. This patch removes that constraint.
gcc/ChangeLog:
* config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Remove
TARGET_ATOMIC constraint
(atomic_store_rvwmo<mode>): Ditto.
* config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Ditto.
(atomic_store_ztso<mode>): Ditto.
* config/riscv/sync.md (atomic_load<mode>): Ditto.
(atomic_store<mode>): Ditto.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
gcc/config/riscv/sync-rvwmo.md | 4 ++--
gcc/config/riscv/sync-ztso.md | 4 ++--
gcc/config/riscv/sync.md | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index cb641ea9ec3..c35eae15334 100644
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -52,7 +52,7 @@
[(match_operand:GPR 1 "memory_operand" "A")
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_ATOMIC_LOAD))]
- "TARGET_ATOMIC && !TARGET_ZTSO"
+ "!TARGET_ZTSO"
{
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
model = memmodel_base (model);
@@ -78,7 +78,7 @@
[(match_operand:GPR 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_ATOMIC_STORE))]
- "TARGET_ATOMIC && !TARGET_ZTSO"
+ "!TARGET_ZTSO"
{
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
model = memmodel_base (model);
diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index 7bb15b7ab8c..6fdfa912a2c 100644
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -46,7 +46,7 @@
[(match_operand:GPR 1 "memory_operand" "A")
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_ATOMIC_LOAD))]
- "TARGET_ATOMIC && TARGET_ZTSO"
+ "TARGET_ZTSO"
{
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
model = memmodel_base (model);
@@ -66,7 +66,7 @@
[(match_operand:GPR 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_ATOMIC_STORE))]
- "TARGET_ATOMIC && TARGET_ZTSO"
+ "TARGET_ZTSO"
{
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
model = memmodel_base (model);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 6ff3493b5ce..ec9d4b4f59e 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -60,7 +60,7 @@
[(match_operand:GPR 0 "register_operand")
(match_operand:GPR 1 "memory_operand")
(match_operand:SI 2 "const_int_operand")] ;; model
- "TARGET_ATOMIC"
+ ""
{
if (TARGET_ZTSO)
emit_insn (gen_atomic_load_ztso<mode> (operands[0], operands[1],
@@ -75,7 +75,7 @@
[(match_operand:GPR 0 "memory_operand")
(match_operand:GPR 1 "reg_or_0_operand")
(match_operand:SI 2 "const_int_operand")] ;; model
- "TARGET_ATOMIC"
+ ""
{
if (TARGET_ZTSO)
emit_insn (gen_atomic_store_ztso<mode> (operands[0], operands[1],
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns
2023-10-31 0:49 [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores Patrick O'Neill
@ 2023-10-31 0:49 ` Patrick O'Neill
2023-10-31 13:07 ` Jeff Law
2023-10-31 13:05 ` [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores Jeff Law
1 sibling, 1 reply; 6+ messages in thread
From: Patrick O'Neill @ 2023-10-31 0:49 UTC (permalink / raw)
To: gcc-patches; +Cc: Patrick O'Neill
Add testsuite infrastructure for the A extension and use it to require the A
extension for dg-do run and add the add extension for non-A dg-do compile.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A extension to
dg-options for dg-do compile.
* gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/inline-atomics-2.c: Ditto.
* gcc.target/riscv/inline-atomics-3.c: Require A extension for dg-do
run.
* gcc.target/riscv/inline-atomics-4.c: Ditto.
* gcc.target/riscv/inline-atomics-5.c: Ditto.
* gcc.target/riscv/inline-atomics-6.c: Ditto.
* gcc.target/riscv/inline-atomics-7.c: Ditto.
* gcc.target/riscv/inline-atomics-8.c: Ditto.
* lib/target-supports.exp: Add testing infrastructure to require the A
extension or add it to an existing -march.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
This patch relies on the previous one in the series. If applied seperately,
amo-table-a-6-store-compat-3.c and amo-table-a-6-load-3.c must be updated to
require the A extension as those testcases check for the optimized fences.
---
.../riscv/amo-table-a-6-amo-add-1.c | 1 +
.../riscv/amo-table-a-6-amo-add-2.c | 1 +
.../riscv/amo-table-a-6-amo-add-3.c | 1 +
.../riscv/amo-table-a-6-amo-add-4.c | 1 +
.../riscv/amo-table-a-6-amo-add-5.c | 1 +
.../riscv/amo-table-a-6-compare-exchange-1.c | 1 +
.../riscv/amo-table-a-6-compare-exchange-2.c | 1 +
.../riscv/amo-table-a-6-compare-exchange-3.c | 1 +
.../riscv/amo-table-a-6-compare-exchange-4.c | 1 +
.../riscv/amo-table-a-6-compare-exchange-5.c | 1 +
.../riscv/amo-table-a-6-compare-exchange-6.c | 1 +
.../riscv/amo-table-a-6-compare-exchange-7.c | 1 +
.../riscv/amo-table-a-6-subword-amo-add-1.c | 1 +
.../riscv/amo-table-a-6-subword-amo-add-2.c | 1 +
.../riscv/amo-table-a-6-subword-amo-add-3.c | 1 +
.../riscv/amo-table-a-6-subword-amo-add-4.c | 1 +
.../riscv/amo-table-a-6-subword-amo-add-5.c | 1 +
.../gcc.target/riscv/inline-atomics-2.c | 3 ++-
.../gcc.target/riscv/inline-atomics-3.c | 2 +-
.../gcc.target/riscv/inline-atomics-4.c | 2 +-
.../gcc.target/riscv/inline-atomics-5.c | 2 +-
.../gcc.target/riscv/inline-atomics-6.c | 2 +-
.../gcc.target/riscv/inline-atomics-7.c | 2 +-
.../gcc.target/riscv/inline-atomics-8.c | 2 +-
gcc/testsuite/lib/target-supports.exp | 23 +++++++++++++++++++
25 files changed, 48 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
index 071a33928fe..8ab1a02b40c 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* Verify that atomic op mappings match Table A.6's recommended mapping. */
/* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
index d6b2d91db2a..a5a841abdcd 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* Verify that atomic op mappings match Table A.6's recommended mapping. */
/* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
index 68a69ed8b78..f523821b658 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* Verify that atomic op mappings match Table A.6's recommended mapping. */
/* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
index b5cac4c4797..f1561b52c89 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* Verify that atomic op mappings match Table A.6's recommended mapping. */
/* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
index 268e58cb95f..81f876ee625 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* Verify that atomic op mappings match Table A.6's recommended mapping. */
/* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
index 8349e7a69ac..dc445f0316a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that compare exchange mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
index bf30b298b4b..7e8ab7bb5ef 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that compare exchange mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
index 41444ec95e9..4cb6c422213 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that compare exchange mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
index dc2d7bd300d..da81c34b92c 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that compare exchange mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
index 53246210900..bb16ccc754c 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that compare exchange mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
index 1376ac2a95b..0f3f0b49d95 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that compare exchange mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* Mixed mappings need to be unioned. */
/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
index 98083cbae08..d51de56cc78 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that compare exchange mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
index d7d887dd181..ca8aa715bed 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
index 897bad26ebd..e64759a54ae 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
index 79efca2839a..9d3f69264fa 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
index 772ac1be6eb..ba32ed59c2f 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
index b0bec66990e..f9be8c5e628 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */
+/* { dg-add-options riscv_a } */
/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c
index 01b43908692..76c99829f33 100644
--- a/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
/* Verify that subword atomics do not generate calls. */
/* { dg-options "-minline-atomics" } */
+/* { dg-add-options riscv_a } */
/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */
/* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_add_1" } } */
/* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_nand_1" } } */
/* { dg-final { scan-assembler-not "\tcall\t__sync_bool_compare_and_swap_1" } } */
-#include "inline-atomics-1.c"
\ No newline at end of file
+#include "inline-atomics-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c
index 709f3734377..7bab0dda03f 100644
--- a/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c
@@ -2,7 +2,7 @@
/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-op-1.c */
/* Test __atomic routines for existence and proper execution on 1 byte
values with each valid memory model. */
-/* { dg-do run } */
+/* { dg-do run { target { riscv_a } } } */
/* { dg-options "-minline-atomics -Wno-address-of-packed-member" } */
/* Test the execution of the __atomic_*OP builtin routines for a char. */
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-4.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-4.c
index eecfaae5cc6..480661353b8 100644
--- a/gcc/testsuite/gcc.target/riscv/inline-atomics-4.c
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-4.c
@@ -2,7 +2,7 @@
/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-op-2.c */
/* Test __atomic routines for existence and proper execution on 2 byte
values with each valid memory model. */
-/* { dg-do run } */
+/* { dg-do run { target { riscv_a } } } */
/* { dg-options "-minline-atomics -Wno-address-of-packed-member" } */
/* Test the execution of the __atomic_*OP builtin routines for a short. */
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-5.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-5.c
index 52093894a79..b677418e480 100644
--- a/gcc/testsuite/gcc.target/riscv/inline-atomics-5.c
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-5.c
@@ -1,7 +1,7 @@
/* Test __atomic routines for existence and proper execution on 1 byte
values with each valid memory model. */
/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-compare-exchange-1.c */
-/* { dg-do run } */
+/* { dg-do run { target { riscv_a } } } */
/* { dg-options "-minline-atomics" } */
/* Test the execution of the __atomic_compare_exchange_n builtin for a char. */
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-6.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-6.c
index 8fee8c44811..fcf2a13fd26 100644
--- a/gcc/testsuite/gcc.target/riscv/inline-atomics-6.c
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-6.c
@@ -1,7 +1,7 @@
/* Test __atomic routines for existence and proper execution on 2 byte
values with each valid memory model. */
/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-compare-exchange-2.c */
-/* { dg-do run } */
+/* { dg-do run { target { riscv_a } } } */
/* { dg-options "-minline-atomics" } */
/* Test the execution of the __atomic_compare_exchange_n builtin for a short. */
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-7.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-7.c
index 24c344c0ce3..72dc42272f1 100644
--- a/gcc/testsuite/gcc.target/riscv/inline-atomics-7.c
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-7.c
@@ -1,7 +1,7 @@
/* Test __atomic routines for existence and proper execution on 1 byte
values with each valid memory model. */
/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-exchange-1.c */
-/* { dg-do run } */
+/* { dg-do run { target { riscv_a } } } */
/* { dg-options "-minline-atomics" } */
/* Test the execution of the __atomic_exchange_n builtin for a char. */
diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-8.c b/gcc/testsuite/gcc.target/riscv/inline-atomics-8.c
index edc212df04e..f583e7187ea 100644
--- a/gcc/testsuite/gcc.target/riscv/inline-atomics-8.c
+++ b/gcc/testsuite/gcc.target/riscv/inline-atomics-8.c
@@ -1,7 +1,7 @@
/* Test __atomic routines for existence and proper execution on 2 byte
values with each valid memory model. */
/* Duplicate logic as libatomic/testsuite/libatomic.c/atomic-exchange-2.c */
-/* { dg-do run } */
+/* { dg-do run { target { riscv_a } } } */
/* { dg-options "-minline-atomics" } */
/* Test the execution of the __atomic_X builtin for a short. */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index f0b692a2e19..8cc170242eb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1903,6 +1903,17 @@ proc check_effective_target_rv_float_abi_soft { } {
}]
}
+# Return 1 if the target arch supports the atomic extension, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_riscv_a { } {
+ return [check_no_compiler_messages riscv_ext_a assembly {
+ #ifndef __riscv_a
+ #error "Not __riscv_a"
+ #endif
+ }]
+}
+
# Return 1 if the target arch supports the double precision floating point
# extension, 0 otherwise. Cache the result.
@@ -2018,6 +2029,18 @@ proc riscv_get_arch { } {
return "$gcc_march"
}
+proc add_options_for_riscv_a { flags } {
+ if { [lsearch $flags -march=*] >= 0 } {
+ # If there are multiple -march flags, we have to adjust all of them.
+ set expanded_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*)g+} $flags \\1imafd ]
+ return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[b-eg-rt-wy]*)a*} $expanded_flags \\1a ]
+ }
+ if { [check_effective_target_riscv_a] } {
+ return "$flags"
+ }
+ return "$flags -march=[regsub {(rv[[:digit:]]*[b-eg-rt-wy]*)a*} [riscv_get_arch] &a]"
+}
+
proc add_options_for_riscv_d { flags } {
if { [lsearch $flags -march=*] >= 0 } {
# If there are multiple -march flags, we have to adjust all of them.
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores
2023-10-31 0:49 [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores Patrick O'Neill
2023-10-31 0:49 ` [PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns Patrick O'Neill
@ 2023-10-31 13:05 ` Jeff Law
2023-10-31 17:16 ` [Committed " Patrick O'Neill
1 sibling, 1 reply; 6+ messages in thread
From: Jeff Law @ 2023-10-31 13:05 UTC (permalink / raw)
To: Patrick O'Neill, gcc-patches
On 10/30/23 18:49, Patrick O'Neill wrote:
> Non-atomic targets are currently prevented from using the optimized fencing for
> seq_cst load/seq_cst store. This patch removes that constraint.
>
> gcc/ChangeLog:
>
> * config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Remove
> TARGET_ATOMIC constraint
> (atomic_store_rvwmo<mode>): Ditto.
> * config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Ditto.
> (atomic_store_ztso<mode>): Ditto.
> * config/riscv/sync.md (atomic_load<mode>): Ditto.
> (atomic_store<mode>): Ditto.
OK
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns
2023-10-31 0:49 ` [PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns Patrick O'Neill
@ 2023-10-31 13:07 ` Jeff Law
2023-10-31 17:16 ` [Committed " Patrick O'Neill
0 siblings, 1 reply; 6+ messages in thread
From: Jeff Law @ 2023-10-31 13:07 UTC (permalink / raw)
To: Patrick O'Neill, gcc-patches
On 10/30/23 18:49, Patrick O'Neill wrote:
> Add testsuite infrastructure for the A extension and use it to require the A
> extension for dg-do run and add the add extension for non-A dg-do compile.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A extension to
> dg-options for dg-do compile.
> * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
> * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
> * gcc.target/riscv/inline-atomics-2.c: Ditto.
> * gcc.target/riscv/inline-atomics-3.c: Require A extension for dg-do
> run.
> * gcc.target/riscv/inline-atomics-4.c: Ditto.
> * gcc.target/riscv/inline-atomics-5.c: Ditto.
> * gcc.target/riscv/inline-atomics-6.c: Ditto.
> * gcc.target/riscv/inline-atomics-7.c: Ditto.
> * gcc.target/riscv/inline-atomics-8.c: Ditto.
> * lib/target-supports.exp: Add testing infrastructure to require the A
> extension or add it to an existing -march.
OK
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Committed 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores
2023-10-31 13:05 ` [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores Jeff Law
@ 2023-10-31 17:16 ` Patrick O'Neill
0 siblings, 0 replies; 6+ messages in thread
From: Patrick O'Neill @ 2023-10-31 17:16 UTC (permalink / raw)
To: Jeff Law, gcc-patches
On 10/31/23 06:05, Jeff Law wrote:
>
>
> On 10/30/23 18:49, Patrick O'Neill wrote:
>> Non-atomic targets are currently prevented from using the optimized
>> fencing for
>> seq_cst load/seq_cst store. This patch removes that constraint.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Remove
>> TARGET_ATOMIC constraint
>> (atomic_store_rvwmo<mode>): Ditto.
>> * config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Ditto.
>> (atomic_store_ztso<mode>): Ditto.
>> * config/riscv/sync.md (atomic_load<mode>): Ditto.
>> (atomic_store<mode>): Ditto.
> OK
> jeff
Committed
Patrick
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Committed 2/2] RISC-V: Require a extension for testcases with atomic insns
2023-10-31 13:07 ` Jeff Law
@ 2023-10-31 17:16 ` Patrick O'Neill
0 siblings, 0 replies; 6+ messages in thread
From: Patrick O'Neill @ 2023-10-31 17:16 UTC (permalink / raw)
To: Jeff Law, gcc-patches
On 10/31/23 06:07, Jeff Law wrote:
>
>
> On 10/30/23 18:49, Patrick O'Neill wrote:
>> Add testsuite infrastructure for the A extension and use it to
>> require the A
>> extension for dg-do run and add the add extension for non-A dg-do
>> compile.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A
>> extension to
>> dg-options for dg-do compile.
>> * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
>> * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
>> * gcc.target/riscv/inline-atomics-2.c: Ditto.
>> * gcc.target/riscv/inline-atomics-3.c: Require A extension
>> for dg-do
>> run.
>> * gcc.target/riscv/inline-atomics-4.c: Ditto.
>> * gcc.target/riscv/inline-atomics-5.c: Ditto.
>> * gcc.target/riscv/inline-atomics-6.c: Ditto.
>> * gcc.target/riscv/inline-atomics-7.c: Ditto.
>> * gcc.target/riscv/inline-atomics-8.c: Ditto.
>> * lib/target-supports.exp: Add testing infrastructure to
>> require the A
>> extension or add it to an existing -march.
> OK
> jeff
Committed
Patrick
^ permalink raw reply [flat|nested] 6+ messages in thread
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2023-10-31 0:49 [PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores Patrick O'Neill
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2023-10-31 13:07 ` Jeff Law
2023-10-31 17:16 ` [Committed " Patrick O'Neill
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