From: Jeff Law <jeffreyalaw@gmail.com>
To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH] RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
Date: Sun, 22 Jan 2023 12:28:28 -0700 [thread overview]
Message-ID: <7023629d-291b-93ed-c79d-9fd01d84de3a@gmail.com> (raw)
In-Reply-To: <20230120093309.104394-1-juzhe.zhong@rivai.ai>
On 1/20/23 02:33, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
> and zve32f. So it makes sense add predicate in the iterators of EEW = 64
> vector modes.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
OK.
Jeff
next prev parent reply other threads:[~2023-01-22 19:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 9:33 juzhe.zhong
2023-01-22 19:28 ` Jeff Law [this message]
2023-01-27 9:59 ` Kito Cheng
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