* [PATCH] RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
@ 2023-01-20 9:33 juzhe.zhong
2023-01-22 19:28 ` Jeff Law
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-01-20 9:33 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
and zve32f. So it makes sense add predicate in the iterators of EEW = 64
vector modes.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
---
gcc/config/riscv/vector-iterators.md | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 92c4bd0a6a3..1f29050622b 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -22,7 +22,8 @@
VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32")
VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32")
VNx1SI VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32")
- VNx1DI VNx2DI VNx4DI (VNx8DI "TARGET_MIN_VLEN > 32")
+ (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32")
+ (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
(VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -38,7 +39,8 @@
(VNx4QI "TARGET_MIN_VLEN == 32") VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32")
(VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32")
(VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32")
- VNx1DI VNx2DI VNx4DI (VNx8DI "TARGET_MIN_VLEN > 32")
+ (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32")
+ (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
(VNx4SF "TARGET_VECTOR_ELEN_FP_32")
--
2.36.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
2023-01-20 9:33 [PATCH] RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes juzhe.zhong
@ 2023-01-22 19:28 ` Jeff Law
2023-01-27 9:59 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: Jeff Law @ 2023-01-22 19:28 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng, palmer
On 1/20/23 02:33, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
> and zve32f. So it makes sense add predicate in the iterators of EEW = 64
> vector modes.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
OK.
Jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
2023-01-22 19:28 ` Jeff Law
@ 2023-01-27 9:59 ` Kito Cheng
0 siblings, 0 replies; 3+ messages in thread
From: Kito Cheng @ 2023-01-27 9:59 UTC (permalink / raw)
To: Jeff Law; +Cc: juzhe.zhong, gcc-patches, palmer
[-- Attachment #1: Type: text/plain, Size: 524 bytes --]
committed, thanks :)
On Mon, Jan 23, 2023 at 3:29 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 1/20/23 02:33, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > According to RVV ISA, RVV doesn't support EEW == 64 vector type for
> zve32x
> > and zve32f. So it makes sense add predicate in the iterators of EEW = 64
> > vector modes.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32
> predicates.
> OK.
>
> Jeff
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-01-20 9:33 [PATCH] RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes juzhe.zhong
2023-01-22 19:28 ` Jeff Law
2023-01-27 9:59 ` Kito Cheng
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