* [PATCH v2 0/5] RISC-V: Add Types to Untyped Instructions
@ 2023-09-08 18:16 Edwin Lu
2023-09-08 18:16 ` [PATCH v2 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
2023-09-08 18:16 ` [PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
0 siblings, 2 replies; 7+ messages in thread
From: Edwin Lu @ 2023-09-08 18:16 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This series adds types to the remaining untyped instructions.
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/
Also enables assert which checks to make sure every instruction has a type
All patches were tested with rv32/rv64 linux/newlib multilib
Additional extensions tested:
gcv
gc_zba_zbb_zbc_zbs
Edwin Lu (5):
RISC-V: Update Types for Vector Instructions
RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Remove Assert Protecting Types
gcc/config/riscv/autovec-opt.md | 72 ++++++++++++++--------
gcc/config/riscv/autovec.md | 52 ++++++++++------
gcc/config/riscv/riscv.cc | 2 -
gcc/config/riscv/riscv.md | 10 +++-
gcc/config/riscv/zc.md | 102 ++++++++++++++++----------------
gcc/config/riscv/zicond.md | 8 +--
6 files changed, 147 insertions(+), 99 deletions(-)
--
2.42.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/5] RISC-V: Update Types for Vector Instructions
2023-09-08 18:16 [PATCH v2 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
@ 2023-09-08 18:16 ` Edwin Lu
2023-09-08 23:56 ` Jeff Law
2023-09-08 18:16 ` [PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
1 sibling, 1 reply; 7+ messages in thread
From: Edwin Lu @ 2023-09-08 18:16 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This patch adds types to vector instructions that were added after or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Update types
* config/riscv/autovec.md: likewise
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
Changes in V2:
- Add types to insns missed by prev version
---
gcc/config/riscv/autovec-opt.md | 72 ++++++++++++++++++++++-----------
gcc/config/riscv/autovec.md | 52 ++++++++++++++++--------
2 files changed, 83 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 3aaee54f02a..58e80044f1e 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -628,7 +628,8 @@ (define_insn_and_split "*cond_abs<mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
const0_rtx));
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine vfsqrt.v and cond_mask
(define_insn_and_split "*cond_<optab><mode>"
@@ -666,7 +667,8 @@ (define_insn_and_split "*copysign<mode>_neg"
riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (<MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf2) and vcond_mask
(define_insn_and_split "*cond_<optab><v_double_trunc><mode>"
@@ -685,7 +687,8 @@ (define_insn_and_split "*cond_<optab><v_double_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf4) and vcond_mask
(define_insn_and_split "*cond_<optab><v_quad_trunc><mode>"
@@ -704,7 +707,8 @@ (define_insn_and_split "*cond_<optab><v_quad_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf8) and vcond_mask
(define_insn_and_split "*cond_<optab><v_oct_trunc><mode>"
@@ -723,7 +727,8 @@ (define_insn_and_split "*cond_<optab><v_oct_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine trunc(vf2) + vcond_mask
(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
@@ -743,7 +748,8 @@ (define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine FP extend(vf2) and vcond_mask
(define_insn_and_split "*cond_extend<v_double_trunc><mode>"
@@ -762,7 +768,8 @@ (define_insn_and_split "*cond_extend<v_double_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine FP trunc(vf2) + vcond_mask
(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
@@ -782,7 +789,8 @@ (define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(FP->INT) + vcond_mask
(define_insn_and_split "*cond_<optab><mode><vconvert>"
@@ -802,7 +810,8 @@ (define_insn_and_split "*cond_<optab><mode><vconvert>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(INT->FP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
@@ -822,7 +831,8 @@ (define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(FP->2xINT) + vcond_mask
(define_insn_and_split "*cond_<optab><vnconvert><mode>"
@@ -842,7 +852,8 @@ (define_insn_and_split "*cond_<optab><vnconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(INT->2xFP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
@@ -862,7 +873,8 @@ (define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(2xFP->INT) + vcond_mask
(define_insn_and_split "*cond_<optab><mode><vnconvert>"
@@ -882,7 +894,8 @@ (define_insn_and_split "*cond_<optab><mode><vnconvert>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(2xINT->FP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2"
@@ -902,7 +915,8 @@ (define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; =============================================================================
;; Combine extend + binop to widen_binop
@@ -925,7 +939,8 @@ (define_insn_and_split "*dual_widen_<any_widen_binop:optab><any_extend:su><mode>
<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
(define_insn_and_split "*single_widen_sub<any_extend:su><mode>"
[(set (match_operand:VWEXTI 0 "register_operand")
@@ -942,7 +957,8 @@ (define_insn_and_split "*single_widen_sub<any_extend:su><mode>"
<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "viwalu")])
(define_insn_and_split "*single_widen_add<any_extend:su><mode>"
[(set (match_operand:VWEXTI 0 "register_operand")
@@ -959,7 +975,8 @@ (define_insn_and_split "*single_widen_add<any_extend:su><mode>"
<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "viwalu")])
;; This combine pattern does not correspond to an single instruction,
;; i.e. there is no vwmul.wv instruction. This is a temporary pattern
@@ -985,7 +1002,8 @@ (define_insn_and_split "*single_widen_mult<any_extend:su><mode>"
insn_code icode = code_for_pred (MULT, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, ops);
DONE;
-})
+}
+[(set_attr "type" "viwmul")])
(define_insn_and_split "*dual_widen_mulsu<mode>"
[(set (match_operand:VWEXTI 0 "register_operand")
@@ -1002,7 +1020,8 @@ (define_insn_and_split "*dual_widen_mulsu<mode>"
insn_code icode = code_for_pred_widen_mulsu (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
(define_insn_and_split "*dual_widen_mulus<mode>"
[(set (match_operand:VWEXTI 0 "register_operand")
@@ -1019,7 +1038,8 @@ (define_insn_and_split "*dual_widen_mulus<mode>"
insn_code icode = code_for_pred_widen_mulsu (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
(define_insn_and_split "*dual_widen_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand")
@@ -1036,7 +1056,8 @@ (define_insn_and_split "*dual_widen_<optab><mode>"
insn_code icode = code_for_pred_dual_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
(define_insn_and_split "*single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand")
@@ -1052,7 +1073,8 @@ (define_insn_and_split "*single_widen_add<mode>"
insn_code icode = code_for_pred_single_widen_add (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwalu")])
(define_insn_and_split "*single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand")
@@ -1068,7 +1090,8 @@ (define_insn_and_split "*single_widen_sub<mode>"
insn_code icode = code_for_pred_single_widen_sub (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwalu")])
;; This combine pattern does not correspond to an single instruction,
;; i.e. there is no vfwmul.wv instruction. This is a temporary pattern
@@ -1094,4 +1117,5 @@ (define_insn_and_split "*single_widen_mult<mode>"
riscv_vector::emit_vlmax_insn (code_for_pred (MULT, <MODE>mode),
riscv_vector::BINARY_OP_FRM_DYN, ops);
DONE;
-})
+}
+[(set_attr "type" "vfwmul")])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 98cd0c07625..ed4f0f8607a 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -432,7 +432,8 @@ (define_insn_and_split "<optab><mode>3"
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vialu")])
;; -------------------------------------------------------------------------
;; ---- [INT] Binary shifts by scalar.
@@ -561,6 +562,7 @@ (define_insn_and_split "@vcond_mask_<mode><vm>"
riscv_vector::MERGE_OP, operands);
DONE;
}
+ [(set_attr "type" "vector")]
)
;; -------------------------------------------------------------------------
@@ -648,7 +650,8 @@ (define_insn_and_split "<optab><v_quad_trunc><mode>2"
insn_code icode = code_for_pred_vf4 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vext")])
(define_insn_and_split "<optab><v_oct_trunc><mode>2"
[(set (match_operand:VOEXTI 0 "register_operand")
@@ -662,7 +665,8 @@ (define_insn_and_split "<optab><v_oct_trunc><mode>2"
insn_code icode = code_for_pred_vf8 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vext")])
;; -------------------------------------------------------------------------
;; ---- [INT] Truncation
@@ -818,7 +822,8 @@ (define_insn_and_split "<optab><mode><vconvert>2"
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfcvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Conversions
@@ -840,7 +845,8 @@ (define_insn_and_split "<float_cvt><vconvert><mode>2"
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfcvtitof")])
;; =========================================================================
;; == Widening/narrowing Conversions
@@ -865,7 +871,8 @@ (define_insn_and_split "<optab><vnconvert><mode>2"
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwcvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Widening Conversions
@@ -886,7 +893,8 @@ (define_insn_and_split "<float_cvt><vnconvert><mode>2"
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwcvtitof")])
;; -------------------------------------------------------------------------
;; ---- [INT<-FP] Narrowing Conversions
@@ -907,7 +915,8 @@ (define_insn_and_split "<optab><mode><vnconvert>2"
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfncvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Narrowing Conversions
@@ -928,7 +937,8 @@ (define_insn_and_split "<float_cvt><mode><vnconvert>2"
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfncvtitof")])
;; =========================================================================
;; == Unary arithmetic
@@ -952,7 +962,8 @@ (define_insn_and_split "<optab><mode>2"
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vialu")])
;; -------------------------------------------------------------------------------
;; - [INT] ABS expansion to vmslt and vneg.
@@ -976,7 +987,8 @@ (define_insn_and_split "abs<mode>2"
riscv_vector::emit_vlmax_insn (code_for_pred (NEG, <MODE>mode),
riscv_vector::UNARY_OP_TAMU, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; -------------------------------------------------------------------------------
;; ---- [FP] Unary operations
@@ -996,7 +1008,8 @@ (define_insn_and_split "<optab><mode>2"
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; -------------------------------------------------------------------------------
;; - [FP] Square root
@@ -1016,7 +1029,8 @@ (define_insn_and_split "<optab><mode>2"
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfsqrt")])
;; =========================================================================
;; == Ternary arithmetic
@@ -1480,7 +1494,8 @@ (define_insn_and_split "<optab><mode>3"
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
riscv_vector::BINARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfalu")])
;; -------------------------------------------------------------------------
;; Includes:
@@ -1500,7 +1515,8 @@ (define_insn_and_split "<optab><mode>3"
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfminmax")])
;; -------------------------------------------------------------------------------
;; ---- [FP] Sign copying
@@ -1566,7 +1582,8 @@ (define_insn_and_split "smul<mode>3_highpart"
insn_code icode = code_for_pred_mulh (UNSPEC_VMULHS, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vimul")])
(define_insn_and_split "umul<mode>3_highpart"
[(set (match_operand:VFULLI 0 "register_operand")
@@ -1581,7 +1598,8 @@ (define_insn_and_split "umul<mode>3_highpart"
insn_code icode = code_for_pred_mulh (UNSPEC_VMULHU, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vimul")])
;; -------------------------------------------------------------------------
;; ---- [INT] Conditional unary operations
--
2.42.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions
2023-09-08 18:16 [PATCH v2 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
2023-09-08 18:16 ` [PATCH v2 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
@ 2023-09-08 18:16 ` Edwin Lu
2023-09-08 23:57 ` Jeff Law
1 sibling, 1 reply; 7+ messages in thread
From: Edwin Lu @ 2023-09-08 18:16 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This patch adds types to the untyped zc instructions. Creates a new
types "pushpop" and "mvpair" for now
gcc/ChangeLog:
* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
Changes in V2:
- Change "csr" type to "pushpop" and "mvpair"
---
gcc/config/riscv/riscv.md | 6 ++-
gcc/config/riscv/zc.md | 102 +++++++++++++++++++-------------------
2 files changed, 56 insertions(+), 52 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b630b51ee50..a6046c17fc3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -316,6 +316,8 @@ (define_attr "ext_enabled" "no,yes"
;; condmove conditional moves
;; cbo cache block instructions
;; crypto cryptography instructions
+;; pushpop zc push and pop instructions
+;; mvpair zc move pair instructions
;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
;; rdvlenb vector byte length vlenb csrr read
;; rdvl vector length vl csrr read
@@ -425,8 +427,8 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
- atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
- vlde,vste,vldm,vstm,vlds,vsts,
+ atomic,condmove,cbo,crypto,pushpop,mvpair,rdvlenb,rdvl,wrvxrm,wrfrm,
+ rdfrm,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 77b28adde95..18b3c30c342 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_<mode>"
(const_int <slot0_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_<mode>"
(const_int <slot1_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_<mode>"
(const_int <slot2_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s1}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_<mode>"
(const_int <slot3_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s2}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_<mode>"
(const_int <slot4_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s3}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_<mode>"
(const_int <slot5_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s4}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_<mode>"
(const_int <slot6_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s5}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_<mode>"
(const_int <slot7_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s6}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_<mode>"
(const_int <slot8_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s7}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_<mode>"
(const_int <slot9_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s8}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_<mode>"
(const_int <slot10_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s9}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_pop_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_<mode>"
(const_int <slot12_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s11}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_ra_<mode>"
[(set (reg:X SP_REGNUM)
@@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -378,7 +378,7 @@ (define_insn "@gpr_multi_popret_up_to_s0_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -397,7 +397,7 @@ (define_insn "@gpr_multi_popret_up_to_s1_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s1}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -419,7 +419,7 @@ (define_insn "@gpr_multi_popret_up_to_s2_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s2}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -444,7 +444,7 @@ (define_insn "@gpr_multi_popret_up_to_s3_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s3}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -472,7 +472,7 @@ (define_insn "@gpr_multi_popret_up_to_s4_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s4}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -503,7 +503,7 @@ (define_insn "@gpr_multi_popret_up_to_s5_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s5}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -537,7 +537,7 @@ (define_insn "@gpr_multi_popret_up_to_s6_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s6}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -574,7 +574,7 @@ (define_insn "@gpr_multi_popret_up_to_s7_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s7}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -614,7 +614,7 @@ (define_insn "@gpr_multi_popret_up_to_s8_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s8}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -657,7 +657,7 @@ (define_insn "@gpr_multi_popret_up_to_s9_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s9}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popret_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -706,7 +706,7 @@ (define_insn "@gpr_multi_popret_up_to_s11_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s11}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
[(set (reg:X SP_REGNUM)
@@ -722,7 +722,7 @@ (define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -741,7 +741,7 @@ (define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -763,7 +763,7 @@ (define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s1}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -788,7 +788,7 @@ (define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s2}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -816,7 +816,7 @@ (define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s3}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -847,7 +847,7 @@ (define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s4}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -881,7 +881,7 @@ (define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s5}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -918,7 +918,7 @@ (define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s6}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -958,7 +958,7 @@ (define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s7}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1001,7 +1001,7 @@ (define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s8}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1047,7 +1047,7 @@ (define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s9}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1099,7 +1099,7 @@ (define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s11}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_ra_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1110,7 +1110,7 @@ (define_insn "@gpr_multi_push_up_to_ra_<mode>"
(match_operand 0 "stack_push_up_to_ra_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s0_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1124,7 +1124,7 @@ (define_insn "@gpr_multi_push_up_to_s0_<mode>"
(match_operand 0 "stack_push_up_to_s0_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s1_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1141,7 +1141,7 @@ (define_insn "@gpr_multi_push_up_to_s1_<mode>"
(match_operand 0 "stack_push_up_to_s1_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s1}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s2_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1161,7 +1161,7 @@ (define_insn "@gpr_multi_push_up_to_s2_<mode>"
(match_operand 0 "stack_push_up_to_s2_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s2}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s3_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1184,7 +1184,7 @@ (define_insn "@gpr_multi_push_up_to_s3_<mode>"
(match_operand 0 "stack_push_up_to_s3_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s3}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s4_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1210,7 +1210,7 @@ (define_insn "@gpr_multi_push_up_to_s4_<mode>"
(match_operand 0 "stack_push_up_to_s4_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s4}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s5_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1239,7 +1239,7 @@ (define_insn "@gpr_multi_push_up_to_s5_<mode>"
(match_operand 0 "stack_push_up_to_s5_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s5}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s6_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1271,7 +1271,7 @@ (define_insn "@gpr_multi_push_up_to_s6_<mode>"
(match_operand 0 "stack_push_up_to_s6_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s6}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s7_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1306,7 +1306,7 @@ (define_insn "@gpr_multi_push_up_to_s7_<mode>"
(match_operand 0 "stack_push_up_to_s7_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s7}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s8_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1344,7 +1344,7 @@ (define_insn "@gpr_multi_push_up_to_s8_<mode>"
(match_operand 0 "stack_push_up_to_s8_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s8}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s9_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1385,7 +1385,7 @@ (define_insn "@gpr_multi_push_up_to_s9_<mode>"
(match_operand 0 "stack_push_up_to_s9_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s9}, %0"
-)
+[(set_attr "type" "pushpop")])
(define_insn "@gpr_multi_push_up_to_s11_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1432,7 +1432,7 @@ (define_insn "@gpr_multi_push_up_to_s11_<mode>"
(match_operand 0 "stack_push_up_to_s11_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s11}, %0"
-)
+[(set_attr "type" "pushpop")])
;; ZCMP mv
(define_insn "*mva01s<X:mode>"
@@ -1443,7 +1443,8 @@ (define_insn "*mva01s<X:mode>"
"TARGET_ZCMP
&& (REGNO (operands[2]) != REGNO (operands[0]))"
{ return (REGNO (operands[0]) == A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; }
- [(set_attr "mode" "<X:MODE>")])
+ [(set_attr "mode" "<X:MODE>")
+ (set_attr "type" "mvpair")])
(define_insn "*mvsa01<X:mode>"
[(set (match_operand:X 0 "zcmp_mv_sreg_operand" "=r")
@@ -1454,4 +1455,5 @@ (define_insn "*mvsa01<X:mode>"
&& (REGNO (operands[0]) != REGNO (operands[2]))
&& (REGNO (operands[1]) != REGNO (operands[3]))"
{ return (REGNO (operands[1]) == A0_REGNUM)?"cm.mvsa01\t%0,%2":"cm.mvsa01\t%2,%0"; }
- [(set_attr "mode" "<X:MODE>")])
+ [(set_attr "mode" "<X:MODE>")
+ (set_attr "type" "mvpair")])
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/5] RISC-V: Update Types for Vector Instructions
2023-09-08 18:16 ` [PATCH v2 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
@ 2023-09-08 23:56 ` Jeff Law
2023-09-11 17:36 ` [PATCH v2 1/5][Committed] " Edwin Lu
0 siblings, 1 reply; 7+ messages in thread
From: Jeff Law @ 2023-09-08 23:56 UTC (permalink / raw)
To: Edwin Lu, gcc-patches; +Cc: gnu-toolchain
On 9/8/23 12:16, Edwin Lu wrote:
> This patch adds types to vector instructions that were added after or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Update types
> * config/riscv/autovec.md: likewise
I think these were all define_insn_and_splits, so just about anything
will do. OK.
jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions
2023-09-08 18:16 ` [PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
@ 2023-09-08 23:57 ` Jeff Law
0 siblings, 0 replies; 7+ messages in thread
From: Jeff Law @ 2023-09-08 23:57 UTC (permalink / raw)
To: Edwin Lu, gcc-patches; +Cc: gnu-toolchain
On 9/8/23 12:16, Edwin Lu wrote:
> This patch adds types to the untyped zc instructions. Creates a new
> types "pushpop" and "mvpair" for now
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "csr" type
> * config/riscv/zc.md: Update types
OK.
Note that once we finish this exercise, making sure any new types that
have been created are handled by the existing scheduling descriptions
would be good follow-up.
jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/5][Committed] RISC-V: Update Types for Vector Instructions
2023-09-08 23:56 ` Jeff Law
@ 2023-09-11 17:36 ` Edwin Lu
2023-09-11 17:36 ` Edwin Lu
0 siblings, 1 reply; 7+ messages in thread
From: Edwin Lu @ 2023-09-11 17:36 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: gnu-toolchain
On 9/8/2023 4:56 PM, Jeff Law via Gcc-patches wrote:
>
>
> On 9/8/23 12:16, Edwin Lu wrote:
>> This patch adds types to vector instructions that were added after or
>> were
>> missed by the original patch
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/autovec-opt.md: Update types
>> * config/riscv/autovec.md: likewise
> I think these were all define_insn_and_splits, so just about anything
> will do. OK.
>
> jeff
>
Committed!
Edwin
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/5][Committed] RISC-V: Update Types for Vector Instructions
2023-09-11 17:36 ` [PATCH v2 1/5][Committed] " Edwin Lu
@ 2023-09-11 17:36 ` Edwin Lu
0 siblings, 0 replies; 7+ messages in thread
From: Edwin Lu @ 2023-09-11 17:36 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain
On 9/8/2023 4:56 PM, Jeff Law via Gcc-patches wrote:
>
>
> On 9/8/23 12:16, Edwin Lu wrote:
>> This patch adds types to vector instructions that were added after or
>> were
>> missed by the original patch
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/autovec-opt.md: Update types
>> * config/riscv/autovec.md: likewise
> I think these were all define_insn_and_splits, so just about anything
> will do. OK.
>
> jeff
>
Committed!
Edwin
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-09-11 17:37 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-08 18:16 [PATCH v2 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
2023-09-08 18:16 ` [PATCH v2 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
2023-09-08 23:56 ` Jeff Law
2023-09-11 17:36 ` [PATCH v2 1/5][Committed] " Edwin Lu
2023-09-11 17:36 ` Edwin Lu
2023-09-08 18:16 ` [PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
2023-09-08 23:57 ` Jeff Law
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