* [PATCH,rs6000] Add insn types for fusion pairs
@ 2021-04-26 18:04 acsawdey
2021-04-26 20:33 ` will schmidt
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: acsawdey @ 2021-04-26 18:04 UTC (permalink / raw)
To: gcc-patches; +Cc: segher, wschmidt, will_schmidt, Aaron Sawdey
From: Aaron Sawdey <acsawdey@linux.ibm.com>
This adds new values for insn attr type for p10 fusion. The genfusion.pl
script is modified to use them, and fusion.md regenerated to capture
the new patterns. There are also some formatting only changes to
fusion.md that apparently weren't captured after a previous commit
of genfusion.pl.
If bootstrap/regtest passes, OK for trunk and backport to 11.2?
Thanks,
Aaron
gcc/
* rs6000.md (define_attr "type"): Add types for fusion.
* genfusion.md (gen_ld_cmpi_p10): Use new fusion types.
(gen_2logical): Use new fusion types.
* fusion.md: Regenerate.
---
gcc/config/rs6000/fusion.md | 288 ++++++++++++++++-----------------
gcc/config/rs6000/genfusion.pl | 8 +-
gcc/config/rs6000/rs6000.md | 4 +-
3 files changed, 152 insertions(+), 148 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 56478fcae1d..6d71bc2df73 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -35,7 +35,7 @@ (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
(set (match_dup 2)
(compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -56,7 +56,7 @@ (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -77,7 +77,7 @@ (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
(set (match_dup 2)
(compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -98,7 +98,7 @@ (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -119,7 +119,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
(set (match_dup 2)
(compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -140,7 +140,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_clobber_CCUNS_none"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -161,7 +161,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
(set (match_dup 2)
(compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -182,7 +182,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_SI_CCUNS_none"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -203,7 +203,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
(set (match_dup 2)
(compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -224,7 +224,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -245,7 +245,7 @@ (define_insn_and_split "*lha_cmpdi_cr0_HI_clobber_CC_sign"
(set (match_dup 2)
(compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -266,7 +266,7 @@ (define_insn_and_split "*lhz_cmpldi_cr0_HI_clobber_CCUNS_zero"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -287,7 +287,7 @@ (define_insn_and_split "*lha_cmpdi_cr0_HI_EXTHI_CC_sign"
(set (match_dup 2)
(compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -308,7 +308,7 @@ (define_insn_and_split "*lhz_cmpldi_cr0_HI_EXTHI_CCUNS_zero"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -329,7 +329,7 @@ (define_insn_and_split "*lbz_cmpldi_cr0_QI_clobber_CCUNS_zero"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -350,7 +350,7 @@ (define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero"
(set (match_dup 2)
(compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -369,7 +369,7 @@ (define_insn "*fuse_and_and"
and %3,%1,%0\;and %3,%3,%2
and %3,%1,%0\;and %3,%3,%2
and %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -387,7 +387,7 @@ (define_insn "*fuse_andc_and"
andc %3,%1,%0\;and %3,%3,%2
andc %3,%1,%0\;and %3,%3,%2
andc %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -405,7 +405,7 @@ (define_insn "*fuse_eqv_and"
eqv %3,%1,%0\;and %3,%3,%2
eqv %3,%1,%0\;and %3,%3,%2
eqv %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -423,7 +423,7 @@ (define_insn "*fuse_nand_and"
nand %3,%1,%0\;and %3,%3,%2
nand %3,%1,%0\;and %3,%3,%2
nand %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -441,7 +441,7 @@ (define_insn "*fuse_nor_and"
nor %3,%1,%0\;and %3,%3,%2
nor %3,%1,%0\;and %3,%3,%2
nor %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -459,7 +459,7 @@ (define_insn "*fuse_or_and"
or %3,%1,%0\;and %3,%3,%2
or %3,%1,%0\;and %3,%3,%2
or %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -477,7 +477,7 @@ (define_insn "*fuse_orc_and"
orc %3,%1,%0\;and %3,%3,%2
orc %3,%1,%0\;and %3,%3,%2
orc %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -495,7 +495,7 @@ (define_insn "*fuse_xor_and"
xor %3,%1,%0\;and %3,%3,%2
xor %3,%1,%0\;and %3,%3,%2
xor %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -513,7 +513,7 @@ (define_insn "*fuse_and_andc"
and %3,%1,%0\;andc %3,%3,%2
and %3,%1,%0\;andc %3,%3,%2
and %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -531,7 +531,7 @@ (define_insn "*fuse_andc_andc"
andc %3,%1,%0\;andc %3,%3,%2
andc %3,%1,%0\;andc %3,%3,%2
andc %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -549,7 +549,7 @@ (define_insn "*fuse_eqv_andc"
eqv %3,%1,%0\;andc %3,%3,%2
eqv %3,%1,%0\;andc %3,%3,%2
eqv %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -567,7 +567,7 @@ (define_insn "*fuse_nand_andc"
nand %3,%1,%0\;andc %3,%3,%2
nand %3,%1,%0\;andc %3,%3,%2
nand %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -585,7 +585,7 @@ (define_insn "*fuse_nor_andc"
nor %3,%1,%0\;andc %3,%3,%2
nor %3,%1,%0\;andc %3,%3,%2
nor %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -603,7 +603,7 @@ (define_insn "*fuse_or_andc"
or %3,%1,%0\;andc %3,%3,%2
or %3,%1,%0\;andc %3,%3,%2
or %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -621,7 +621,7 @@ (define_insn "*fuse_orc_andc"
orc %3,%1,%0\;andc %3,%3,%2
orc %3,%1,%0\;andc %3,%3,%2
orc %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -639,7 +639,7 @@ (define_insn "*fuse_xor_andc"
xor %3,%1,%0\;andc %3,%3,%2
xor %3,%1,%0\;andc %3,%3,%2
xor %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -657,7 +657,7 @@ (define_insn "*fuse_and_eqv"
and %3,%1,%0\;eqv %3,%3,%2
and %3,%1,%0\;eqv %3,%3,%2
and %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -675,7 +675,7 @@ (define_insn "*fuse_andc_eqv"
andc %3,%1,%0\;eqv %3,%3,%2
andc %3,%1,%0\;eqv %3,%3,%2
andc %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -693,7 +693,7 @@ (define_insn "*fuse_eqv_eqv"
eqv %3,%1,%0\;eqv %3,%3,%2
eqv %3,%1,%0\;eqv %3,%3,%2
eqv %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -711,7 +711,7 @@ (define_insn "*fuse_nand_eqv"
nand %3,%1,%0\;eqv %3,%3,%2
nand %3,%1,%0\;eqv %3,%3,%2
nand %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -729,7 +729,7 @@ (define_insn "*fuse_nor_eqv"
nor %3,%1,%0\;eqv %3,%3,%2
nor %3,%1,%0\;eqv %3,%3,%2
nor %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -747,7 +747,7 @@ (define_insn "*fuse_or_eqv"
or %3,%1,%0\;eqv %3,%3,%2
or %3,%1,%0\;eqv %3,%3,%2
or %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -765,7 +765,7 @@ (define_insn "*fuse_orc_eqv"
orc %3,%1,%0\;eqv %3,%3,%2
orc %3,%1,%0\;eqv %3,%3,%2
orc %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -783,7 +783,7 @@ (define_insn "*fuse_xor_eqv"
xor %3,%1,%0\;eqv %3,%3,%2
xor %3,%1,%0\;eqv %3,%3,%2
xor %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -801,7 +801,7 @@ (define_insn "*fuse_and_nand"
and %3,%1,%0\;nand %3,%3,%2
and %3,%1,%0\;nand %3,%3,%2
and %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -819,7 +819,7 @@ (define_insn "*fuse_andc_nand"
andc %3,%1,%0\;nand %3,%3,%2
andc %3,%1,%0\;nand %3,%3,%2
andc %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -837,7 +837,7 @@ (define_insn "*fuse_eqv_nand"
eqv %3,%1,%0\;nand %3,%3,%2
eqv %3,%1,%0\;nand %3,%3,%2
eqv %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -855,7 +855,7 @@ (define_insn "*fuse_nand_nand"
nand %3,%1,%0\;nand %3,%3,%2
nand %3,%1,%0\;nand %3,%3,%2
nand %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -873,7 +873,7 @@ (define_insn "*fuse_nor_nand"
nor %3,%1,%0\;nand %3,%3,%2
nor %3,%1,%0\;nand %3,%3,%2
nor %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -891,7 +891,7 @@ (define_insn "*fuse_or_nand"
or %3,%1,%0\;nand %3,%3,%2
or %3,%1,%0\;nand %3,%3,%2
or %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -909,7 +909,7 @@ (define_insn "*fuse_orc_nand"
orc %3,%1,%0\;nand %3,%3,%2
orc %3,%1,%0\;nand %3,%3,%2
orc %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -927,7 +927,7 @@ (define_insn "*fuse_xor_nand"
xor %3,%1,%0\;nand %3,%3,%2
xor %3,%1,%0\;nand %3,%3,%2
xor %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -945,7 +945,7 @@ (define_insn "*fuse_and_nor"
and %3,%1,%0\;nor %3,%3,%2
and %3,%1,%0\;nor %3,%3,%2
and %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -963,7 +963,7 @@ (define_insn "*fuse_andc_nor"
andc %3,%1,%0\;nor %3,%3,%2
andc %3,%1,%0\;nor %3,%3,%2
andc %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -981,7 +981,7 @@ (define_insn "*fuse_eqv_nor"
eqv %3,%1,%0\;nor %3,%3,%2
eqv %3,%1,%0\;nor %3,%3,%2
eqv %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -999,7 +999,7 @@ (define_insn "*fuse_nand_nor"
nand %3,%1,%0\;nor %3,%3,%2
nand %3,%1,%0\;nor %3,%3,%2
nand %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1017,7 +1017,7 @@ (define_insn "*fuse_nor_nor"
nor %3,%1,%0\;nor %3,%3,%2
nor %3,%1,%0\;nor %3,%3,%2
nor %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1035,7 +1035,7 @@ (define_insn "*fuse_or_nor"
or %3,%1,%0\;nor %3,%3,%2
or %3,%1,%0\;nor %3,%3,%2
or %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1053,7 +1053,7 @@ (define_insn "*fuse_orc_nor"
orc %3,%1,%0\;nor %3,%3,%2
orc %3,%1,%0\;nor %3,%3,%2
orc %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1071,7 +1071,7 @@ (define_insn "*fuse_xor_nor"
xor %3,%1,%0\;nor %3,%3,%2
xor %3,%1,%0\;nor %3,%3,%2
xor %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1089,7 +1089,7 @@ (define_insn "*fuse_and_or"
and %3,%1,%0\;or %3,%3,%2
and %3,%1,%0\;or %3,%3,%2
and %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1107,7 +1107,7 @@ (define_insn "*fuse_andc_or"
andc %3,%1,%0\;or %3,%3,%2
andc %3,%1,%0\;or %3,%3,%2
andc %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1125,7 +1125,7 @@ (define_insn "*fuse_eqv_or"
eqv %3,%1,%0\;or %3,%3,%2
eqv %3,%1,%0\;or %3,%3,%2
eqv %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1143,7 +1143,7 @@ (define_insn "*fuse_nand_or"
nand %3,%1,%0\;or %3,%3,%2
nand %3,%1,%0\;or %3,%3,%2
nand %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1161,7 +1161,7 @@ (define_insn "*fuse_nor_or"
nor %3,%1,%0\;or %3,%3,%2
nor %3,%1,%0\;or %3,%3,%2
nor %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1179,7 +1179,7 @@ (define_insn "*fuse_or_or"
or %3,%1,%0\;or %3,%3,%2
or %3,%1,%0\;or %3,%3,%2
or %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1197,7 +1197,7 @@ (define_insn "*fuse_orc_or"
orc %3,%1,%0\;or %3,%3,%2
orc %3,%1,%0\;or %3,%3,%2
orc %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1215,7 +1215,7 @@ (define_insn "*fuse_xor_or"
xor %3,%1,%0\;or %3,%3,%2
xor %3,%1,%0\;or %3,%3,%2
xor %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1233,7 +1233,7 @@ (define_insn "*fuse_and_orc"
and %3,%1,%0\;orc %3,%3,%2
and %3,%1,%0\;orc %3,%3,%2
and %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1251,7 +1251,7 @@ (define_insn "*fuse_andc_orc"
andc %3,%1,%0\;orc %3,%3,%2
andc %3,%1,%0\;orc %3,%3,%2
andc %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1269,7 +1269,7 @@ (define_insn "*fuse_eqv_orc"
eqv %3,%1,%0\;orc %3,%3,%2
eqv %3,%1,%0\;orc %3,%3,%2
eqv %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1287,7 +1287,7 @@ (define_insn "*fuse_nand_orc"
nand %3,%1,%0\;orc %3,%3,%2
nand %3,%1,%0\;orc %3,%3,%2
nand %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1305,7 +1305,7 @@ (define_insn "*fuse_nor_orc"
nor %3,%1,%0\;orc %3,%3,%2
nor %3,%1,%0\;orc %3,%3,%2
nor %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1323,7 +1323,7 @@ (define_insn "*fuse_or_orc"
or %3,%1,%0\;orc %3,%3,%2
or %3,%1,%0\;orc %3,%3,%2
or %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1341,7 +1341,7 @@ (define_insn "*fuse_orc_orc"
orc %3,%1,%0\;orc %3,%3,%2
orc %3,%1,%0\;orc %3,%3,%2
orc %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1359,7 +1359,7 @@ (define_insn "*fuse_xor_orc"
xor %3,%1,%0\;orc %3,%3,%2
xor %3,%1,%0\;orc %3,%3,%2
xor %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1377,7 +1377,7 @@ (define_insn "*fuse_and_xor"
and %3,%1,%0\;xor %3,%3,%2
and %3,%1,%0\;xor %3,%3,%2
and %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1395,7 +1395,7 @@ (define_insn "*fuse_andc_xor"
andc %3,%1,%0\;xor %3,%3,%2
andc %3,%1,%0\;xor %3,%3,%2
andc %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1413,7 +1413,7 @@ (define_insn "*fuse_eqv_xor"
eqv %3,%1,%0\;xor %3,%3,%2
eqv %3,%1,%0\;xor %3,%3,%2
eqv %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1431,7 +1431,7 @@ (define_insn "*fuse_nand_xor"
nand %3,%1,%0\;xor %3,%3,%2
nand %3,%1,%0\;xor %3,%3,%2
nand %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1449,7 +1449,7 @@ (define_insn "*fuse_nor_xor"
nor %3,%1,%0\;xor %3,%3,%2
nor %3,%1,%0\;xor %3,%3,%2
nor %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1467,7 +1467,7 @@ (define_insn "*fuse_or_xor"
or %3,%1,%0\;xor %3,%3,%2
or %3,%1,%0\;xor %3,%3,%2
or %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1485,7 +1485,7 @@ (define_insn "*fuse_orc_xor"
orc %3,%1,%0\;xor %3,%3,%2
orc %3,%1,%0\;xor %3,%3,%2
orc %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1503,7 +1503,7 @@ (define_insn "*fuse_xor_xor"
xor %3,%1,%0\;xor %3,%3,%2
xor %3,%1,%0\;xor %3,%3,%2
xor %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_arith_logical")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1521,7 +1521,7 @@ (define_insn "*fuse_vand_vand"
vand %3,%1,%0\;vand %3,%3,%2
vand %3,%1,%0\;vand %3,%3,%2
vand %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1539,7 +1539,7 @@ (define_insn "*fuse_vandc_vand"
vandc %3,%1,%0\;vand %3,%3,%2
vandc %3,%1,%0\;vand %3,%3,%2
vandc %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1557,7 +1557,7 @@ (define_insn "*fuse_veqv_vand"
veqv %3,%1,%0\;vand %3,%3,%2
veqv %3,%1,%0\;vand %3,%3,%2
veqv %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1575,7 +1575,7 @@ (define_insn "*fuse_vnand_vand"
vnand %3,%1,%0\;vand %3,%3,%2
vnand %3,%1,%0\;vand %3,%3,%2
vnand %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1593,7 +1593,7 @@ (define_insn "*fuse_vnor_vand"
vnor %3,%1,%0\;vand %3,%3,%2
vnor %3,%1,%0\;vand %3,%3,%2
vnor %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1611,7 +1611,7 @@ (define_insn "*fuse_vor_vand"
vor %3,%1,%0\;vand %3,%3,%2
vor %3,%1,%0\;vand %3,%3,%2
vor %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1629,7 +1629,7 @@ (define_insn "*fuse_vorc_vand"
vorc %3,%1,%0\;vand %3,%3,%2
vorc %3,%1,%0\;vand %3,%3,%2
vorc %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1647,7 +1647,7 @@ (define_insn "*fuse_vxor_vand"
vxor %3,%1,%0\;vand %3,%3,%2
vxor %3,%1,%0\;vand %3,%3,%2
vxor %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1665,7 +1665,7 @@ (define_insn "*fuse_vand_vandc"
vand %3,%1,%0\;vandc %3,%3,%2
vand %3,%1,%0\;vandc %3,%3,%2
vand %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1683,7 +1683,7 @@ (define_insn "*fuse_vandc_vandc"
vandc %3,%1,%0\;vandc %3,%3,%2
vandc %3,%1,%0\;vandc %3,%3,%2
vandc %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1701,7 +1701,7 @@ (define_insn "*fuse_veqv_vandc"
veqv %3,%1,%0\;vandc %3,%3,%2
veqv %3,%1,%0\;vandc %3,%3,%2
veqv %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1719,7 +1719,7 @@ (define_insn "*fuse_vnand_vandc"
vnand %3,%1,%0\;vandc %3,%3,%2
vnand %3,%1,%0\;vandc %3,%3,%2
vnand %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1737,7 +1737,7 @@ (define_insn "*fuse_vnor_vandc"
vnor %3,%1,%0\;vandc %3,%3,%2
vnor %3,%1,%0\;vandc %3,%3,%2
vnor %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1755,7 +1755,7 @@ (define_insn "*fuse_vor_vandc"
vor %3,%1,%0\;vandc %3,%3,%2
vor %3,%1,%0\;vandc %3,%3,%2
vor %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1773,7 +1773,7 @@ (define_insn "*fuse_vorc_vandc"
vorc %3,%1,%0\;vandc %3,%3,%2
vorc %3,%1,%0\;vandc %3,%3,%2
vorc %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1791,7 +1791,7 @@ (define_insn "*fuse_vxor_vandc"
vxor %3,%1,%0\;vandc %3,%3,%2
vxor %3,%1,%0\;vandc %3,%3,%2
vxor %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1809,7 +1809,7 @@ (define_insn "*fuse_vand_veqv"
vand %3,%1,%0\;veqv %3,%3,%2
vand %3,%1,%0\;veqv %3,%3,%2
vand %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1827,7 +1827,7 @@ (define_insn "*fuse_vandc_veqv"
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1845,7 +1845,7 @@ (define_insn "*fuse_veqv_veqv"
veqv %3,%1,%0\;veqv %3,%3,%2
veqv %3,%1,%0\;veqv %3,%3,%2
veqv %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1863,7 +1863,7 @@ (define_insn "*fuse_vnand_veqv"
vnand %3,%1,%0\;veqv %3,%3,%2
vnand %3,%1,%0\;veqv %3,%3,%2
vnand %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1881,7 +1881,7 @@ (define_insn "*fuse_vnor_veqv"
vnor %3,%1,%0\;veqv %3,%3,%2
vnor %3,%1,%0\;veqv %3,%3,%2
vnor %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1899,7 +1899,7 @@ (define_insn "*fuse_vor_veqv"
vor %3,%1,%0\;veqv %3,%3,%2
vor %3,%1,%0\;veqv %3,%3,%2
vor %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1917,7 +1917,7 @@ (define_insn "*fuse_vorc_veqv"
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1935,7 +1935,7 @@ (define_insn "*fuse_vxor_veqv"
vxor %3,%1,%0\;veqv %3,%3,%2
vxor %3,%1,%0\;veqv %3,%3,%2
vxor %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1953,7 +1953,7 @@ (define_insn "*fuse_vand_vnand"
vand %3,%1,%0\;vnand %3,%3,%2
vand %3,%1,%0\;vnand %3,%3,%2
vand %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1971,7 +1971,7 @@ (define_insn "*fuse_vandc_vnand"
vandc %3,%1,%0\;vnand %3,%3,%2
vandc %3,%1,%0\;vnand %3,%3,%2
vandc %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1989,7 +1989,7 @@ (define_insn "*fuse_veqv_vnand"
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2007,7 +2007,7 @@ (define_insn "*fuse_vnand_vnand"
vnand %3,%1,%0\;vnand %3,%3,%2
vnand %3,%1,%0\;vnand %3,%3,%2
vnand %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2025,7 +2025,7 @@ (define_insn "*fuse_vnor_vnand"
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2043,7 +2043,7 @@ (define_insn "*fuse_vor_vnand"
vor %3,%1,%0\;vnand %3,%3,%2
vor %3,%1,%0\;vnand %3,%3,%2
vor %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2061,7 +2061,7 @@ (define_insn "*fuse_vorc_vnand"
vorc %3,%1,%0\;vnand %3,%3,%2
vorc %3,%1,%0\;vnand %3,%3,%2
vorc %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2079,7 +2079,7 @@ (define_insn "*fuse_vxor_vnand"
vxor %3,%1,%0\;vnand %3,%3,%2
vxor %3,%1,%0\;vnand %3,%3,%2
vxor %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2097,7 +2097,7 @@ (define_insn "*fuse_vand_vnor"
vand %3,%1,%0\;vnor %3,%3,%2
vand %3,%1,%0\;vnor %3,%3,%2
vand %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2115,7 +2115,7 @@ (define_insn "*fuse_vandc_vnor"
vandc %3,%1,%0\;vnor %3,%3,%2
vandc %3,%1,%0\;vnor %3,%3,%2
vandc %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2133,7 +2133,7 @@ (define_insn "*fuse_veqv_vnor"
veqv %3,%1,%0\;vnor %3,%3,%2
veqv %3,%1,%0\;vnor %3,%3,%2
veqv %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2151,7 +2151,7 @@ (define_insn "*fuse_vnand_vnor"
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2169,7 +2169,7 @@ (define_insn "*fuse_vnor_vnor"
vnor %3,%1,%0\;vnor %3,%3,%2
vnor %3,%1,%0\;vnor %3,%3,%2
vnor %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2187,7 +2187,7 @@ (define_insn "*fuse_vor_vnor"
vor %3,%1,%0\;vnor %3,%3,%2
vor %3,%1,%0\;vnor %3,%3,%2
vor %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2205,7 +2205,7 @@ (define_insn "*fuse_vorc_vnor"
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2223,7 +2223,7 @@ (define_insn "*fuse_vxor_vnor"
vxor %3,%1,%0\;vnor %3,%3,%2
vxor %3,%1,%0\;vnor %3,%3,%2
vxor %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2241,7 +2241,7 @@ (define_insn "*fuse_vand_vor"
vand %3,%1,%0\;vor %3,%3,%2
vand %3,%1,%0\;vor %3,%3,%2
vand %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2259,7 +2259,7 @@ (define_insn "*fuse_vandc_vor"
vandc %3,%1,%0\;vor %3,%3,%2
vandc %3,%1,%0\;vor %3,%3,%2
vandc %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2277,7 +2277,7 @@ (define_insn "*fuse_veqv_vor"
veqv %3,%1,%0\;vor %3,%3,%2
veqv %3,%1,%0\;vor %3,%3,%2
veqv %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2295,7 +2295,7 @@ (define_insn "*fuse_vnand_vor"
vnand %3,%1,%0\;vor %3,%3,%2
vnand %3,%1,%0\;vor %3,%3,%2
vnand %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2313,7 +2313,7 @@ (define_insn "*fuse_vnor_vor"
vnor %3,%1,%0\;vor %3,%3,%2
vnor %3,%1,%0\;vor %3,%3,%2
vnor %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2331,7 +2331,7 @@ (define_insn "*fuse_vor_vor"
vor %3,%1,%0\;vor %3,%3,%2
vor %3,%1,%0\;vor %3,%3,%2
vor %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2349,7 +2349,7 @@ (define_insn "*fuse_vorc_vor"
vorc %3,%1,%0\;vor %3,%3,%2
vorc %3,%1,%0\;vor %3,%3,%2
vorc %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2367,7 +2367,7 @@ (define_insn "*fuse_vxor_vor"
vxor %3,%1,%0\;vor %3,%3,%2
vxor %3,%1,%0\;vor %3,%3,%2
vxor %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2385,7 +2385,7 @@ (define_insn "*fuse_vand_vorc"
vand %3,%1,%0\;vorc %3,%3,%2
vand %3,%1,%0\;vorc %3,%3,%2
vand %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2403,7 +2403,7 @@ (define_insn "*fuse_vandc_vorc"
vandc %3,%1,%0\;vorc %3,%3,%2
vandc %3,%1,%0\;vorc %3,%3,%2
vandc %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2421,7 +2421,7 @@ (define_insn "*fuse_veqv_vorc"
veqv %3,%1,%0\;vorc %3,%3,%2
veqv %3,%1,%0\;vorc %3,%3,%2
veqv %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2439,7 +2439,7 @@ (define_insn "*fuse_vnand_vorc"
vnand %3,%1,%0\;vorc %3,%3,%2
vnand %3,%1,%0\;vorc %3,%3,%2
vnand %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2457,7 +2457,7 @@ (define_insn "*fuse_vnor_vorc"
vnor %3,%1,%0\;vorc %3,%3,%2
vnor %3,%1,%0\;vorc %3,%3,%2
vnor %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2475,7 +2475,7 @@ (define_insn "*fuse_vor_vorc"
vor %3,%1,%0\;vorc %3,%3,%2
vor %3,%1,%0\;vorc %3,%3,%2
vor %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2493,7 +2493,7 @@ (define_insn "*fuse_vorc_vorc"
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2511,7 +2511,7 @@ (define_insn "*fuse_vxor_vorc"
vxor %3,%1,%0\;vorc %3,%3,%2
vxor %3,%1,%0\;vorc %3,%3,%2
vxor %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2529,7 +2529,7 @@ (define_insn "*fuse_vand_vxor"
vand %3,%1,%0\;vxor %3,%3,%2
vand %3,%1,%0\;vxor %3,%3,%2
vand %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2547,7 +2547,7 @@ (define_insn "*fuse_vandc_vxor"
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2565,7 +2565,7 @@ (define_insn "*fuse_veqv_vxor"
veqv %3,%1,%0\;vxor %3,%3,%2
veqv %3,%1,%0\;vxor %3,%3,%2
veqv %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2583,7 +2583,7 @@ (define_insn "*fuse_vnand_vxor"
vnand %3,%1,%0\;vxor %3,%3,%2
vnand %3,%1,%0\;vxor %3,%3,%2
vnand %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2601,7 +2601,7 @@ (define_insn "*fuse_vnor_vxor"
vnor %3,%1,%0\;vxor %3,%3,%2
vnor %3,%1,%0\;vxor %3,%3,%2
vnor %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2619,7 +2619,7 @@ (define_insn "*fuse_vor_vxor"
vor %3,%1,%0\;vxor %3,%3,%2
vor %3,%1,%0\;vxor %3,%3,%2
vor %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2637,7 +2637,7 @@ (define_insn "*fuse_vorc_vxor"
vorc %3,%1,%0\;vxor %3,%3,%2
vorc %3,%1,%0\;vxor %3,%3,%2
vorc %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2655,6 +2655,6 @@ (define_insn "*fuse_vxor_vxor"
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fused_vector")
(set_attr "cost" "6")
(set_attr "length" "8")])
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index c86c7436a62..ce48fd94f95 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -135,7 +135,7 @@ sub gen_ld_cmpi_p10
print " (set (match_dup 2)\n";
print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
print " \"\"\n";
- print " [(set_attr \"type\" \"load\")\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
print " (set_attr \"cost\" \"8\")\n";
print " (set_attr \"length\" \"8\")])\n";
print "\n";
@@ -159,18 +159,20 @@ sub gen_2logical
my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, $outer_op,
$outer_comp, $outer_inv, $outer_rtl, $inner, $inner_comp, $inner_inv,
$inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0,
- $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn);
+ $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn, $fuse_type);
KIND: foreach $kind ('scalar','vector') {
if ( $kind eq 'vector' ) {
$vchr = "v";
$mode = "VM";
$pred = "altivec_register_operand";
$constraint = "v";
+ $fuse_type = "fused_vector";
} else {
$vchr = "";
$mode = "GPR";
$pred = "gpc_reg_operand";
$constraint = "r";
+ $fuse_type = "fused_arith_logical";
}
$c4 = "${constraint},${constraint},${constraint},${constraint}";
OUTER: foreach $outer ( @logicals ) {
@@ -227,7 +229,7 @@ sub gen_2logical
${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "$fuse_type")
(set_attr "cost" "6")
(set_attr "length" "8")])
EOF
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c8cdc42533c..801e1014267 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -204,7 +204,9 @@ (define_attr "type"
vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
vecfloat,vecfdiv,vecdouble,mtvsr,mfvsr,crypto,
veclogical,veccmpfx,vecexts,vecmove,
- htm,htmsimple,dfp,mma"
+ htm,htmsimple,dfp,mma,
+ fused_arith_logical,fused_cmp_isel,fused_carry,fused_load_cmpi,
+ fused_load_load,fused_store_store,fused_addis_load,fused_mtbc,fused_vector"
(const_string "integer"))
;; What data size does this instruction work on?
--
2.27.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH,rs6000] Add insn types for fusion pairs
2021-04-26 18:04 [PATCH,rs6000] Add insn types for fusion pairs acsawdey
@ 2021-04-26 20:33 ` will schmidt
2021-05-11 13:51 ` Aaron Sawdey
2021-05-19 20:10 ` Segher Boessenkool
2 siblings, 0 replies; 4+ messages in thread
From: will schmidt @ 2021-04-26 20:33 UTC (permalink / raw)
To: acsawdey, gcc-patches; +Cc: segher, wschmidt
On Mon, 2021-04-26 at 13:04 -0500, acsawdey@linux.ibm.com wrote:
> From: Aaron Sawdey <acsawdey@linux.ibm.com>
>
> This adds new values for insn attr type for p10 fusion. The
> genfusion.pl
> script is modified to use them, and fusion.md regenerated to capture
> the new patterns. There are also some formatting only changes to
> fusion.md that apparently weren't captured after a previous commit
> of genfusion.pl.
>
> If bootstrap/regtest passes, OK for trunk and backport to 11.2?
>
> Thanks,
> Aaron
>
Hi,
> gcc/
> * rs6000.md (define_attr "type"): Add types for fusion.
> * genfusion.md (gen_ld_cmpi_p10): Use new fusion types.
> (gen_2logical): Use new fusion types.
> * fusion.md: Regenerate.
Should the new types be listed here?
> ---
> gcc/config/rs6000/fusion.md | 288 ++++++++++++++++---------------
> --
> gcc/config/rs6000/genfusion.pl | 8 +-
> gcc/config/rs6000/rs6000.md | 4 +-
> 3 files changed, 152 insertions(+), 148 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000.md
> b/gcc/config/rs6000/rs6000.md
> index c8cdc42533c..801e1014267 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -204,7 +204,9 @@ (define_attr "type"
> vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
> vecfloat,vecfdiv,vecdouble,mtvsr,mfvsr,crypto,
> veclogical,veccmpfx,vecexts,vecmove,
> - htm,htmsimple,dfp,mma"
> + htm,htmsimple,dfp,mma,
> + fused_arith_logical,fused_cmp_isel,fused_carry,fused_load_cmpi,
> + fused_load_load,fused_store_store,fused_addis_load,fused_mtbc,fus
> ed_vector"
A few of these new attributes appear unused in this patch.
Should those be dropped, or will they be used later?
> diff --git a/gcc/config/rs6000/fusion.md
> b/gcc/config/rs6000/fusion.md
> index 56478fcae1d..6d71bc2df73 100644
> --- a/gcc/config/rs6000/fusion.md
> +++ b/gcc/config/rs6000/fusion.md
<snip>
> @@ -1503,7 +1503,7 @@ (define_insn "*fuse_xor_xor"
> xor %3,%1,%0\;xor %3,%3,%2
> xor %3,%1,%0\;xor %3,%3,%2
> xor %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1521,7 +1521,7 @@ (define_insn "*fuse_vand_vand"
> vand %3,%1,%0\;vand %3,%3,%2
> vand %3,%1,%0\;vand %3,%3,%2
> vand %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
Noting that the vector-logicals are lumped into the fused_vector versus
logical.. I assume this is correct. :-)
<snip>
diff --git a/gcc/config/rs6000/genfusion.pl
> b/gcc/config/rs6000/genfusion.pl
> index c86c7436a62..ce48fd94f95 100755
> --- a/gcc/config/rs6000/genfusion.pl
> +++ b/gcc/config/rs6000/genfusion.pl
> @@ -135,7 +135,7 @@ sub gen_ld_cmpi_p10
> print " (set (match_dup 2)\n";
> print " (compare:${ccmode} (match_dup 0) (match_dup
> 3)))]\n";
> print " \"\"\n";
> - print " [(set_attr \"type\" \"load\")\n";
> + print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
> print " (set_attr \"cost\" \"8\")\n";
> print " (set_attr \"length\" \"8\")])\n";
> print "\n";
> @@ -159,18 +159,20 @@ sub gen_2logical
> my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer,
> $outer_op,
> $outer_comp, $outer_inv, $outer_rtl, $inner, $inner_comp,
> $inner_inv,
> $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0,
> - $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn);
> + $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn,
> $fuse_type);
> KIND: foreach $kind ('scalar','vector') {
> if ( $kind eq 'vector' ) {
> $vchr = "v";
> $mode = "VM";
> $pred = "altivec_register_operand";
> $constraint = "v";
> + $fuse_type = "fused_vector";
> } else {
> $vchr = "";
> $mode = "GPR";
> $pred = "gpc_reg_operand";
> $constraint = "r";
> + $fuse_type = "fused_arith_logical";
> }
> $c4 =
> "${constraint},${constraint},${constraint},${constraint}";
> OUTER: foreach $outer ( @logicals ) {
> @@ -227,7 +229,7 @@ sub gen_2logical
> ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
> ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
> ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "$fuse_type")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
ok
thanks
-Will
> EOF
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH,rs6000] Add insn types for fusion pairs
2021-04-26 18:04 [PATCH,rs6000] Add insn types for fusion pairs acsawdey
2021-04-26 20:33 ` will schmidt
@ 2021-05-11 13:51 ` Aaron Sawdey
2021-05-19 20:10 ` Segher Boessenkool
2 siblings, 0 replies; 4+ messages in thread
From: Aaron Sawdey @ 2021-05-11 13:51 UTC (permalink / raw)
To: gcc-patches; +Cc: segher, wschmidt, will_schmidt
Ping.
In answer to Will’s question — some of these are not immediately used but will be in other pending patches.
Aaron Sawdey, Ph.D. sawdey@linux.ibm.com
IBM Linux on POWER Toolchain
> On Apr 26, 2021, at 1:04 PM, acsawdey@linux.ibm.com wrote:
>
> From: Aaron Sawdey <acsawdey@linux.ibm.com>
>
> This adds new values for insn attr type for p10 fusion. The genfusion.pl
> script is modified to use them, and fusion.md regenerated to capture
> the new patterns. There are also some formatting only changes to
> fusion.md that apparently weren't captured after a previous commit
> of genfusion.pl.
>
> If bootstrap/regtest passes, OK for trunk and backport to 11.2?
>
> Thanks,
> Aaron
>
> gcc/
> * rs6000.md (define_attr "type"): Add types for fusion.
> * genfusion.md (gen_ld_cmpi_p10): Use new fusion types.
> (gen_2logical): Use new fusion types.
> * fusion.md: Regenerate.
> ---
> gcc/config/rs6000/fusion.md | 288 ++++++++++++++++-----------------
> gcc/config/rs6000/genfusion.pl | 8 +-
> gcc/config/rs6000/rs6000.md | 4 +-
> 3 files changed, 152 insertions(+), 148 deletions(-)
>
> diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
> index 56478fcae1d..6d71bc2df73 100644
> --- a/gcc/config/rs6000/fusion.md
> +++ b/gcc/config/rs6000/fusion.md
> @@ -35,7 +35,7 @@ (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
> (set (match_dup 2)
> (compare:CC (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -56,7 +56,7 @@ (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -77,7 +77,7 @@ (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
> (set (match_dup 2)
> (compare:CC (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -98,7 +98,7 @@ (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -119,7 +119,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
> (set (match_dup 2)
> (compare:CC (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -140,7 +140,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_clobber_CCUNS_none"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -161,7 +161,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
> (set (match_dup 2)
> (compare:CC (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -182,7 +182,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_SI_CCUNS_none"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -203,7 +203,7 @@ (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
> (set (match_dup 2)
> (compare:CC (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -224,7 +224,7 @@ (define_insn_and_split "*lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -245,7 +245,7 @@ (define_insn_and_split "*lha_cmpdi_cr0_HI_clobber_CC_sign"
> (set (match_dup 2)
> (compare:CC (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -266,7 +266,7 @@ (define_insn_and_split "*lhz_cmpldi_cr0_HI_clobber_CCUNS_zero"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -287,7 +287,7 @@ (define_insn_and_split "*lha_cmpdi_cr0_HI_EXTHI_CC_sign"
> (set (match_dup 2)
> (compare:CC (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -308,7 +308,7 @@ (define_insn_and_split "*lhz_cmpldi_cr0_HI_EXTHI_CCUNS_zero"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -329,7 +329,7 @@ (define_insn_and_split "*lbz_cmpldi_cr0_QI_clobber_CCUNS_zero"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -350,7 +350,7 @@ (define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero"
> (set (match_dup 2)
> (compare:CCUNS (match_dup 0) (match_dup 3)))]
> ""
> - [(set_attr "type" "load")
> + [(set_attr "type" "fused_load_cmpi")
> (set_attr "cost" "8")
> (set_attr "length" "8")])
>
> @@ -369,7 +369,7 @@ (define_insn "*fuse_and_and"
> and %3,%1,%0\;and %3,%3,%2
> and %3,%1,%0\;and %3,%3,%2
> and %4,%1,%0\;and %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -387,7 +387,7 @@ (define_insn "*fuse_andc_and"
> andc %3,%1,%0\;and %3,%3,%2
> andc %3,%1,%0\;and %3,%3,%2
> andc %4,%1,%0\;and %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -405,7 +405,7 @@ (define_insn "*fuse_eqv_and"
> eqv %3,%1,%0\;and %3,%3,%2
> eqv %3,%1,%0\;and %3,%3,%2
> eqv %4,%1,%0\;and %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -423,7 +423,7 @@ (define_insn "*fuse_nand_and"
> nand %3,%1,%0\;and %3,%3,%2
> nand %3,%1,%0\;and %3,%3,%2
> nand %4,%1,%0\;and %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -441,7 +441,7 @@ (define_insn "*fuse_nor_and"
> nor %3,%1,%0\;and %3,%3,%2
> nor %3,%1,%0\;and %3,%3,%2
> nor %4,%1,%0\;and %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -459,7 +459,7 @@ (define_insn "*fuse_or_and"
> or %3,%1,%0\;and %3,%3,%2
> or %3,%1,%0\;and %3,%3,%2
> or %4,%1,%0\;and %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -477,7 +477,7 @@ (define_insn "*fuse_orc_and"
> orc %3,%1,%0\;and %3,%3,%2
> orc %3,%1,%0\;and %3,%3,%2
> orc %4,%1,%0\;and %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -495,7 +495,7 @@ (define_insn "*fuse_xor_and"
> xor %3,%1,%0\;and %3,%3,%2
> xor %3,%1,%0\;and %3,%3,%2
> xor %4,%1,%0\;and %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -513,7 +513,7 @@ (define_insn "*fuse_and_andc"
> and %3,%1,%0\;andc %3,%3,%2
> and %3,%1,%0\;andc %3,%3,%2
> and %4,%1,%0\;andc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -531,7 +531,7 @@ (define_insn "*fuse_andc_andc"
> andc %3,%1,%0\;andc %3,%3,%2
> andc %3,%1,%0\;andc %3,%3,%2
> andc %4,%1,%0\;andc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -549,7 +549,7 @@ (define_insn "*fuse_eqv_andc"
> eqv %3,%1,%0\;andc %3,%3,%2
> eqv %3,%1,%0\;andc %3,%3,%2
> eqv %4,%1,%0\;andc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -567,7 +567,7 @@ (define_insn "*fuse_nand_andc"
> nand %3,%1,%0\;andc %3,%3,%2
> nand %3,%1,%0\;andc %3,%3,%2
> nand %4,%1,%0\;andc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -585,7 +585,7 @@ (define_insn "*fuse_nor_andc"
> nor %3,%1,%0\;andc %3,%3,%2
> nor %3,%1,%0\;andc %3,%3,%2
> nor %4,%1,%0\;andc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -603,7 +603,7 @@ (define_insn "*fuse_or_andc"
> or %3,%1,%0\;andc %3,%3,%2
> or %3,%1,%0\;andc %3,%3,%2
> or %4,%1,%0\;andc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -621,7 +621,7 @@ (define_insn "*fuse_orc_andc"
> orc %3,%1,%0\;andc %3,%3,%2
> orc %3,%1,%0\;andc %3,%3,%2
> orc %4,%1,%0\;andc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -639,7 +639,7 @@ (define_insn "*fuse_xor_andc"
> xor %3,%1,%0\;andc %3,%3,%2
> xor %3,%1,%0\;andc %3,%3,%2
> xor %4,%1,%0\;andc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -657,7 +657,7 @@ (define_insn "*fuse_and_eqv"
> and %3,%1,%0\;eqv %3,%3,%2
> and %3,%1,%0\;eqv %3,%3,%2
> and %4,%1,%0\;eqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -675,7 +675,7 @@ (define_insn "*fuse_andc_eqv"
> andc %3,%1,%0\;eqv %3,%3,%2
> andc %3,%1,%0\;eqv %3,%3,%2
> andc %4,%1,%0\;eqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -693,7 +693,7 @@ (define_insn "*fuse_eqv_eqv"
> eqv %3,%1,%0\;eqv %3,%3,%2
> eqv %3,%1,%0\;eqv %3,%3,%2
> eqv %4,%1,%0\;eqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -711,7 +711,7 @@ (define_insn "*fuse_nand_eqv"
> nand %3,%1,%0\;eqv %3,%3,%2
> nand %3,%1,%0\;eqv %3,%3,%2
> nand %4,%1,%0\;eqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -729,7 +729,7 @@ (define_insn "*fuse_nor_eqv"
> nor %3,%1,%0\;eqv %3,%3,%2
> nor %3,%1,%0\;eqv %3,%3,%2
> nor %4,%1,%0\;eqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -747,7 +747,7 @@ (define_insn "*fuse_or_eqv"
> or %3,%1,%0\;eqv %3,%3,%2
> or %3,%1,%0\;eqv %3,%3,%2
> or %4,%1,%0\;eqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -765,7 +765,7 @@ (define_insn "*fuse_orc_eqv"
> orc %3,%1,%0\;eqv %3,%3,%2
> orc %3,%1,%0\;eqv %3,%3,%2
> orc %4,%1,%0\;eqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -783,7 +783,7 @@ (define_insn "*fuse_xor_eqv"
> xor %3,%1,%0\;eqv %3,%3,%2
> xor %3,%1,%0\;eqv %3,%3,%2
> xor %4,%1,%0\;eqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -801,7 +801,7 @@ (define_insn "*fuse_and_nand"
> and %3,%1,%0\;nand %3,%3,%2
> and %3,%1,%0\;nand %3,%3,%2
> and %4,%1,%0\;nand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -819,7 +819,7 @@ (define_insn "*fuse_andc_nand"
> andc %3,%1,%0\;nand %3,%3,%2
> andc %3,%1,%0\;nand %3,%3,%2
> andc %4,%1,%0\;nand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -837,7 +837,7 @@ (define_insn "*fuse_eqv_nand"
> eqv %3,%1,%0\;nand %3,%3,%2
> eqv %3,%1,%0\;nand %3,%3,%2
> eqv %4,%1,%0\;nand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -855,7 +855,7 @@ (define_insn "*fuse_nand_nand"
> nand %3,%1,%0\;nand %3,%3,%2
> nand %3,%1,%0\;nand %3,%3,%2
> nand %4,%1,%0\;nand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -873,7 +873,7 @@ (define_insn "*fuse_nor_nand"
> nor %3,%1,%0\;nand %3,%3,%2
> nor %3,%1,%0\;nand %3,%3,%2
> nor %4,%1,%0\;nand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -891,7 +891,7 @@ (define_insn "*fuse_or_nand"
> or %3,%1,%0\;nand %3,%3,%2
> or %3,%1,%0\;nand %3,%3,%2
> or %4,%1,%0\;nand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -909,7 +909,7 @@ (define_insn "*fuse_orc_nand"
> orc %3,%1,%0\;nand %3,%3,%2
> orc %3,%1,%0\;nand %3,%3,%2
> orc %4,%1,%0\;nand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -927,7 +927,7 @@ (define_insn "*fuse_xor_nand"
> xor %3,%1,%0\;nand %3,%3,%2
> xor %3,%1,%0\;nand %3,%3,%2
> xor %4,%1,%0\;nand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -945,7 +945,7 @@ (define_insn "*fuse_and_nor"
> and %3,%1,%0\;nor %3,%3,%2
> and %3,%1,%0\;nor %3,%3,%2
> and %4,%1,%0\;nor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -963,7 +963,7 @@ (define_insn "*fuse_andc_nor"
> andc %3,%1,%0\;nor %3,%3,%2
> andc %3,%1,%0\;nor %3,%3,%2
> andc %4,%1,%0\;nor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -981,7 +981,7 @@ (define_insn "*fuse_eqv_nor"
> eqv %3,%1,%0\;nor %3,%3,%2
> eqv %3,%1,%0\;nor %3,%3,%2
> eqv %4,%1,%0\;nor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -999,7 +999,7 @@ (define_insn "*fuse_nand_nor"
> nand %3,%1,%0\;nor %3,%3,%2
> nand %3,%1,%0\;nor %3,%3,%2
> nand %4,%1,%0\;nor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1017,7 +1017,7 @@ (define_insn "*fuse_nor_nor"
> nor %3,%1,%0\;nor %3,%3,%2
> nor %3,%1,%0\;nor %3,%3,%2
> nor %4,%1,%0\;nor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1035,7 +1035,7 @@ (define_insn "*fuse_or_nor"
> or %3,%1,%0\;nor %3,%3,%2
> or %3,%1,%0\;nor %3,%3,%2
> or %4,%1,%0\;nor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1053,7 +1053,7 @@ (define_insn "*fuse_orc_nor"
> orc %3,%1,%0\;nor %3,%3,%2
> orc %3,%1,%0\;nor %3,%3,%2
> orc %4,%1,%0\;nor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1071,7 +1071,7 @@ (define_insn "*fuse_xor_nor"
> xor %3,%1,%0\;nor %3,%3,%2
> xor %3,%1,%0\;nor %3,%3,%2
> xor %4,%1,%0\;nor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1089,7 +1089,7 @@ (define_insn "*fuse_and_or"
> and %3,%1,%0\;or %3,%3,%2
> and %3,%1,%0\;or %3,%3,%2
> and %4,%1,%0\;or %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1107,7 +1107,7 @@ (define_insn "*fuse_andc_or"
> andc %3,%1,%0\;or %3,%3,%2
> andc %3,%1,%0\;or %3,%3,%2
> andc %4,%1,%0\;or %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1125,7 +1125,7 @@ (define_insn "*fuse_eqv_or"
> eqv %3,%1,%0\;or %3,%3,%2
> eqv %3,%1,%0\;or %3,%3,%2
> eqv %4,%1,%0\;or %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1143,7 +1143,7 @@ (define_insn "*fuse_nand_or"
> nand %3,%1,%0\;or %3,%3,%2
> nand %3,%1,%0\;or %3,%3,%2
> nand %4,%1,%0\;or %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1161,7 +1161,7 @@ (define_insn "*fuse_nor_or"
> nor %3,%1,%0\;or %3,%3,%2
> nor %3,%1,%0\;or %3,%3,%2
> nor %4,%1,%0\;or %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1179,7 +1179,7 @@ (define_insn "*fuse_or_or"
> or %3,%1,%0\;or %3,%3,%2
> or %3,%1,%0\;or %3,%3,%2
> or %4,%1,%0\;or %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1197,7 +1197,7 @@ (define_insn "*fuse_orc_or"
> orc %3,%1,%0\;or %3,%3,%2
> orc %3,%1,%0\;or %3,%3,%2
> orc %4,%1,%0\;or %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1215,7 +1215,7 @@ (define_insn "*fuse_xor_or"
> xor %3,%1,%0\;or %3,%3,%2
> xor %3,%1,%0\;or %3,%3,%2
> xor %4,%1,%0\;or %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1233,7 +1233,7 @@ (define_insn "*fuse_and_orc"
> and %3,%1,%0\;orc %3,%3,%2
> and %3,%1,%0\;orc %3,%3,%2
> and %4,%1,%0\;orc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1251,7 +1251,7 @@ (define_insn "*fuse_andc_orc"
> andc %3,%1,%0\;orc %3,%3,%2
> andc %3,%1,%0\;orc %3,%3,%2
> andc %4,%1,%0\;orc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1269,7 +1269,7 @@ (define_insn "*fuse_eqv_orc"
> eqv %3,%1,%0\;orc %3,%3,%2
> eqv %3,%1,%0\;orc %3,%3,%2
> eqv %4,%1,%0\;orc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1287,7 +1287,7 @@ (define_insn "*fuse_nand_orc"
> nand %3,%1,%0\;orc %3,%3,%2
> nand %3,%1,%0\;orc %3,%3,%2
> nand %4,%1,%0\;orc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1305,7 +1305,7 @@ (define_insn "*fuse_nor_orc"
> nor %3,%1,%0\;orc %3,%3,%2
> nor %3,%1,%0\;orc %3,%3,%2
> nor %4,%1,%0\;orc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1323,7 +1323,7 @@ (define_insn "*fuse_or_orc"
> or %3,%1,%0\;orc %3,%3,%2
> or %3,%1,%0\;orc %3,%3,%2
> or %4,%1,%0\;orc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1341,7 +1341,7 @@ (define_insn "*fuse_orc_orc"
> orc %3,%1,%0\;orc %3,%3,%2
> orc %3,%1,%0\;orc %3,%3,%2
> orc %4,%1,%0\;orc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1359,7 +1359,7 @@ (define_insn "*fuse_xor_orc"
> xor %3,%1,%0\;orc %3,%3,%2
> xor %3,%1,%0\;orc %3,%3,%2
> xor %4,%1,%0\;orc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1377,7 +1377,7 @@ (define_insn "*fuse_and_xor"
> and %3,%1,%0\;xor %3,%3,%2
> and %3,%1,%0\;xor %3,%3,%2
> and %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1395,7 +1395,7 @@ (define_insn "*fuse_andc_xor"
> andc %3,%1,%0\;xor %3,%3,%2
> andc %3,%1,%0\;xor %3,%3,%2
> andc %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1413,7 +1413,7 @@ (define_insn "*fuse_eqv_xor"
> eqv %3,%1,%0\;xor %3,%3,%2
> eqv %3,%1,%0\;xor %3,%3,%2
> eqv %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1431,7 +1431,7 @@ (define_insn "*fuse_nand_xor"
> nand %3,%1,%0\;xor %3,%3,%2
> nand %3,%1,%0\;xor %3,%3,%2
> nand %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1449,7 +1449,7 @@ (define_insn "*fuse_nor_xor"
> nor %3,%1,%0\;xor %3,%3,%2
> nor %3,%1,%0\;xor %3,%3,%2
> nor %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1467,7 +1467,7 @@ (define_insn "*fuse_or_xor"
> or %3,%1,%0\;xor %3,%3,%2
> or %3,%1,%0\;xor %3,%3,%2
> or %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1485,7 +1485,7 @@ (define_insn "*fuse_orc_xor"
> orc %3,%1,%0\;xor %3,%3,%2
> orc %3,%1,%0\;xor %3,%3,%2
> orc %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1503,7 +1503,7 @@ (define_insn "*fuse_xor_xor"
> xor %3,%1,%0\;xor %3,%3,%2
> xor %3,%1,%0\;xor %3,%3,%2
> xor %4,%1,%0\;xor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_arith_logical")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1521,7 +1521,7 @@ (define_insn "*fuse_vand_vand"
> vand %3,%1,%0\;vand %3,%3,%2
> vand %3,%1,%0\;vand %3,%3,%2
> vand %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1539,7 +1539,7 @@ (define_insn "*fuse_vandc_vand"
> vandc %3,%1,%0\;vand %3,%3,%2
> vandc %3,%1,%0\;vand %3,%3,%2
> vandc %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1557,7 +1557,7 @@ (define_insn "*fuse_veqv_vand"
> veqv %3,%1,%0\;vand %3,%3,%2
> veqv %3,%1,%0\;vand %3,%3,%2
> veqv %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1575,7 +1575,7 @@ (define_insn "*fuse_vnand_vand"
> vnand %3,%1,%0\;vand %3,%3,%2
> vnand %3,%1,%0\;vand %3,%3,%2
> vnand %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1593,7 +1593,7 @@ (define_insn "*fuse_vnor_vand"
> vnor %3,%1,%0\;vand %3,%3,%2
> vnor %3,%1,%0\;vand %3,%3,%2
> vnor %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1611,7 +1611,7 @@ (define_insn "*fuse_vor_vand"
> vor %3,%1,%0\;vand %3,%3,%2
> vor %3,%1,%0\;vand %3,%3,%2
> vor %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1629,7 +1629,7 @@ (define_insn "*fuse_vorc_vand"
> vorc %3,%1,%0\;vand %3,%3,%2
> vorc %3,%1,%0\;vand %3,%3,%2
> vorc %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1647,7 +1647,7 @@ (define_insn "*fuse_vxor_vand"
> vxor %3,%1,%0\;vand %3,%3,%2
> vxor %3,%1,%0\;vand %3,%3,%2
> vxor %4,%1,%0\;vand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1665,7 +1665,7 @@ (define_insn "*fuse_vand_vandc"
> vand %3,%1,%0\;vandc %3,%3,%2
> vand %3,%1,%0\;vandc %3,%3,%2
> vand %4,%1,%0\;vandc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1683,7 +1683,7 @@ (define_insn "*fuse_vandc_vandc"
> vandc %3,%1,%0\;vandc %3,%3,%2
> vandc %3,%1,%0\;vandc %3,%3,%2
> vandc %4,%1,%0\;vandc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1701,7 +1701,7 @@ (define_insn "*fuse_veqv_vandc"
> veqv %3,%1,%0\;vandc %3,%3,%2
> veqv %3,%1,%0\;vandc %3,%3,%2
> veqv %4,%1,%0\;vandc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1719,7 +1719,7 @@ (define_insn "*fuse_vnand_vandc"
> vnand %3,%1,%0\;vandc %3,%3,%2
> vnand %3,%1,%0\;vandc %3,%3,%2
> vnand %4,%1,%0\;vandc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1737,7 +1737,7 @@ (define_insn "*fuse_vnor_vandc"
> vnor %3,%1,%0\;vandc %3,%3,%2
> vnor %3,%1,%0\;vandc %3,%3,%2
> vnor %4,%1,%0\;vandc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1755,7 +1755,7 @@ (define_insn "*fuse_vor_vandc"
> vor %3,%1,%0\;vandc %3,%3,%2
> vor %3,%1,%0\;vandc %3,%3,%2
> vor %4,%1,%0\;vandc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1773,7 +1773,7 @@ (define_insn "*fuse_vorc_vandc"
> vorc %3,%1,%0\;vandc %3,%3,%2
> vorc %3,%1,%0\;vandc %3,%3,%2
> vorc %4,%1,%0\;vandc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1791,7 +1791,7 @@ (define_insn "*fuse_vxor_vandc"
> vxor %3,%1,%0\;vandc %3,%3,%2
> vxor %3,%1,%0\;vandc %3,%3,%2
> vxor %4,%1,%0\;vandc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1809,7 +1809,7 @@ (define_insn "*fuse_vand_veqv"
> vand %3,%1,%0\;veqv %3,%3,%2
> vand %3,%1,%0\;veqv %3,%3,%2
> vand %4,%1,%0\;veqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1827,7 +1827,7 @@ (define_insn "*fuse_vandc_veqv"
> vandc %3,%1,%0\;veqv %3,%3,%2
> vandc %3,%1,%0\;veqv %3,%3,%2
> vandc %4,%1,%0\;veqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1845,7 +1845,7 @@ (define_insn "*fuse_veqv_veqv"
> veqv %3,%1,%0\;veqv %3,%3,%2
> veqv %3,%1,%0\;veqv %3,%3,%2
> veqv %4,%1,%0\;veqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1863,7 +1863,7 @@ (define_insn "*fuse_vnand_veqv"
> vnand %3,%1,%0\;veqv %3,%3,%2
> vnand %3,%1,%0\;veqv %3,%3,%2
> vnand %4,%1,%0\;veqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1881,7 +1881,7 @@ (define_insn "*fuse_vnor_veqv"
> vnor %3,%1,%0\;veqv %3,%3,%2
> vnor %3,%1,%0\;veqv %3,%3,%2
> vnor %4,%1,%0\;veqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1899,7 +1899,7 @@ (define_insn "*fuse_vor_veqv"
> vor %3,%1,%0\;veqv %3,%3,%2
> vor %3,%1,%0\;veqv %3,%3,%2
> vor %4,%1,%0\;veqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1917,7 +1917,7 @@ (define_insn "*fuse_vorc_veqv"
> vorc %3,%1,%0\;veqv %3,%3,%2
> vorc %3,%1,%0\;veqv %3,%3,%2
> vorc %4,%1,%0\;veqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1935,7 +1935,7 @@ (define_insn "*fuse_vxor_veqv"
> vxor %3,%1,%0\;veqv %3,%3,%2
> vxor %3,%1,%0\;veqv %3,%3,%2
> vxor %4,%1,%0\;veqv %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1953,7 +1953,7 @@ (define_insn "*fuse_vand_vnand"
> vand %3,%1,%0\;vnand %3,%3,%2
> vand %3,%1,%0\;vnand %3,%3,%2
> vand %4,%1,%0\;vnand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1971,7 +1971,7 @@ (define_insn "*fuse_vandc_vnand"
> vandc %3,%1,%0\;vnand %3,%3,%2
> vandc %3,%1,%0\;vnand %3,%3,%2
> vandc %4,%1,%0\;vnand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -1989,7 +1989,7 @@ (define_insn "*fuse_veqv_vnand"
> veqv %3,%1,%0\;vnand %3,%3,%2
> veqv %3,%1,%0\;vnand %3,%3,%2
> veqv %4,%1,%0\;vnand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2007,7 +2007,7 @@ (define_insn "*fuse_vnand_vnand"
> vnand %3,%1,%0\;vnand %3,%3,%2
> vnand %3,%1,%0\;vnand %3,%3,%2
> vnand %4,%1,%0\;vnand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2025,7 +2025,7 @@ (define_insn "*fuse_vnor_vnand"
> vnor %3,%1,%0\;vnand %3,%3,%2
> vnor %3,%1,%0\;vnand %3,%3,%2
> vnor %4,%1,%0\;vnand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2043,7 +2043,7 @@ (define_insn "*fuse_vor_vnand"
> vor %3,%1,%0\;vnand %3,%3,%2
> vor %3,%1,%0\;vnand %3,%3,%2
> vor %4,%1,%0\;vnand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2061,7 +2061,7 @@ (define_insn "*fuse_vorc_vnand"
> vorc %3,%1,%0\;vnand %3,%3,%2
> vorc %3,%1,%0\;vnand %3,%3,%2
> vorc %4,%1,%0\;vnand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2079,7 +2079,7 @@ (define_insn "*fuse_vxor_vnand"
> vxor %3,%1,%0\;vnand %3,%3,%2
> vxor %3,%1,%0\;vnand %3,%3,%2
> vxor %4,%1,%0\;vnand %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2097,7 +2097,7 @@ (define_insn "*fuse_vand_vnor"
> vand %3,%1,%0\;vnor %3,%3,%2
> vand %3,%1,%0\;vnor %3,%3,%2
> vand %4,%1,%0\;vnor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2115,7 +2115,7 @@ (define_insn "*fuse_vandc_vnor"
> vandc %3,%1,%0\;vnor %3,%3,%2
> vandc %3,%1,%0\;vnor %3,%3,%2
> vandc %4,%1,%0\;vnor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2133,7 +2133,7 @@ (define_insn "*fuse_veqv_vnor"
> veqv %3,%1,%0\;vnor %3,%3,%2
> veqv %3,%1,%0\;vnor %3,%3,%2
> veqv %4,%1,%0\;vnor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2151,7 +2151,7 @@ (define_insn "*fuse_vnand_vnor"
> vnand %3,%1,%0\;vnor %3,%3,%2
> vnand %3,%1,%0\;vnor %3,%3,%2
> vnand %4,%1,%0\;vnor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2169,7 +2169,7 @@ (define_insn "*fuse_vnor_vnor"
> vnor %3,%1,%0\;vnor %3,%3,%2
> vnor %3,%1,%0\;vnor %3,%3,%2
> vnor %4,%1,%0\;vnor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2187,7 +2187,7 @@ (define_insn "*fuse_vor_vnor"
> vor %3,%1,%0\;vnor %3,%3,%2
> vor %3,%1,%0\;vnor %3,%3,%2
> vor %4,%1,%0\;vnor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2205,7 +2205,7 @@ (define_insn "*fuse_vorc_vnor"
> vorc %3,%1,%0\;vnor %3,%3,%2
> vorc %3,%1,%0\;vnor %3,%3,%2
> vorc %4,%1,%0\;vnor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2223,7 +2223,7 @@ (define_insn "*fuse_vxor_vnor"
> vxor %3,%1,%0\;vnor %3,%3,%2
> vxor %3,%1,%0\;vnor %3,%3,%2
> vxor %4,%1,%0\;vnor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2241,7 +2241,7 @@ (define_insn "*fuse_vand_vor"
> vand %3,%1,%0\;vor %3,%3,%2
> vand %3,%1,%0\;vor %3,%3,%2
> vand %4,%1,%0\;vor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2259,7 +2259,7 @@ (define_insn "*fuse_vandc_vor"
> vandc %3,%1,%0\;vor %3,%3,%2
> vandc %3,%1,%0\;vor %3,%3,%2
> vandc %4,%1,%0\;vor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2277,7 +2277,7 @@ (define_insn "*fuse_veqv_vor"
> veqv %3,%1,%0\;vor %3,%3,%2
> veqv %3,%1,%0\;vor %3,%3,%2
> veqv %4,%1,%0\;vor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2295,7 +2295,7 @@ (define_insn "*fuse_vnand_vor"
> vnand %3,%1,%0\;vor %3,%3,%2
> vnand %3,%1,%0\;vor %3,%3,%2
> vnand %4,%1,%0\;vor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2313,7 +2313,7 @@ (define_insn "*fuse_vnor_vor"
> vnor %3,%1,%0\;vor %3,%3,%2
> vnor %3,%1,%0\;vor %3,%3,%2
> vnor %4,%1,%0\;vor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2331,7 +2331,7 @@ (define_insn "*fuse_vor_vor"
> vor %3,%1,%0\;vor %3,%3,%2
> vor %3,%1,%0\;vor %3,%3,%2
> vor %4,%1,%0\;vor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2349,7 +2349,7 @@ (define_insn "*fuse_vorc_vor"
> vorc %3,%1,%0\;vor %3,%3,%2
> vorc %3,%1,%0\;vor %3,%3,%2
> vorc %4,%1,%0\;vor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2367,7 +2367,7 @@ (define_insn "*fuse_vxor_vor"
> vxor %3,%1,%0\;vor %3,%3,%2
> vxor %3,%1,%0\;vor %3,%3,%2
> vxor %4,%1,%0\;vor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2385,7 +2385,7 @@ (define_insn "*fuse_vand_vorc"
> vand %3,%1,%0\;vorc %3,%3,%2
> vand %3,%1,%0\;vorc %3,%3,%2
> vand %4,%1,%0\;vorc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2403,7 +2403,7 @@ (define_insn "*fuse_vandc_vorc"
> vandc %3,%1,%0\;vorc %3,%3,%2
> vandc %3,%1,%0\;vorc %3,%3,%2
> vandc %4,%1,%0\;vorc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2421,7 +2421,7 @@ (define_insn "*fuse_veqv_vorc"
> veqv %3,%1,%0\;vorc %3,%3,%2
> veqv %3,%1,%0\;vorc %3,%3,%2
> veqv %4,%1,%0\;vorc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2439,7 +2439,7 @@ (define_insn "*fuse_vnand_vorc"
> vnand %3,%1,%0\;vorc %3,%3,%2
> vnand %3,%1,%0\;vorc %3,%3,%2
> vnand %4,%1,%0\;vorc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2457,7 +2457,7 @@ (define_insn "*fuse_vnor_vorc"
> vnor %3,%1,%0\;vorc %3,%3,%2
> vnor %3,%1,%0\;vorc %3,%3,%2
> vnor %4,%1,%0\;vorc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2475,7 +2475,7 @@ (define_insn "*fuse_vor_vorc"
> vor %3,%1,%0\;vorc %3,%3,%2
> vor %3,%1,%0\;vorc %3,%3,%2
> vor %4,%1,%0\;vorc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2493,7 +2493,7 @@ (define_insn "*fuse_vorc_vorc"
> vorc %3,%1,%0\;vorc %3,%3,%2
> vorc %3,%1,%0\;vorc %3,%3,%2
> vorc %4,%1,%0\;vorc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2511,7 +2511,7 @@ (define_insn "*fuse_vxor_vorc"
> vxor %3,%1,%0\;vorc %3,%3,%2
> vxor %3,%1,%0\;vorc %3,%3,%2
> vxor %4,%1,%0\;vorc %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2529,7 +2529,7 @@ (define_insn "*fuse_vand_vxor"
> vand %3,%1,%0\;vxor %3,%3,%2
> vand %3,%1,%0\;vxor %3,%3,%2
> vand %4,%1,%0\;vxor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2547,7 +2547,7 @@ (define_insn "*fuse_vandc_vxor"
> vandc %3,%1,%0\;vxor %3,%3,%2
> vandc %3,%1,%0\;vxor %3,%3,%2
> vandc %4,%1,%0\;vxor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2565,7 +2565,7 @@ (define_insn "*fuse_veqv_vxor"
> veqv %3,%1,%0\;vxor %3,%3,%2
> veqv %3,%1,%0\;vxor %3,%3,%2
> veqv %4,%1,%0\;vxor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2583,7 +2583,7 @@ (define_insn "*fuse_vnand_vxor"
> vnand %3,%1,%0\;vxor %3,%3,%2
> vnand %3,%1,%0\;vxor %3,%3,%2
> vnand %4,%1,%0\;vxor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2601,7 +2601,7 @@ (define_insn "*fuse_vnor_vxor"
> vnor %3,%1,%0\;vxor %3,%3,%2
> vnor %3,%1,%0\;vxor %3,%3,%2
> vnor %4,%1,%0\;vxor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2619,7 +2619,7 @@ (define_insn "*fuse_vor_vxor"
> vor %3,%1,%0\;vxor %3,%3,%2
> vor %3,%1,%0\;vxor %3,%3,%2
> vor %4,%1,%0\;vxor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2637,7 +2637,7 @@ (define_insn "*fuse_vorc_vxor"
> vorc %3,%1,%0\;vxor %3,%3,%2
> vorc %3,%1,%0\;vxor %3,%3,%2
> vorc %4,%1,%0\;vxor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
>
> @@ -2655,6 +2655,6 @@ (define_insn "*fuse_vxor_vxor"
> vxor %3,%1,%0\;vxor %3,%3,%2
> vxor %3,%1,%0\;vxor %3,%3,%2
> vxor %4,%1,%0\;vxor %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "fused_vector")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
> diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
> index c86c7436a62..ce48fd94f95 100755
> --- a/gcc/config/rs6000/genfusion.pl
> +++ b/gcc/config/rs6000/genfusion.pl
> @@ -135,7 +135,7 @@ sub gen_ld_cmpi_p10
> print " (set (match_dup 2)\n";
> print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
> print " \"\"\n";
> - print " [(set_attr \"type\" \"load\")\n";
> + print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
> print " (set_attr \"cost\" \"8\")\n";
> print " (set_attr \"length\" \"8\")])\n";
> print "\n";
> @@ -159,18 +159,20 @@ sub gen_2logical
> my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, $outer_op,
> $outer_comp, $outer_inv, $outer_rtl, $inner, $inner_comp, $inner_inv,
> $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0,
> - $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn);
> + $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn, $fuse_type);
> KIND: foreach $kind ('scalar','vector') {
> if ( $kind eq 'vector' ) {
> $vchr = "v";
> $mode = "VM";
> $pred = "altivec_register_operand";
> $constraint = "v";
> + $fuse_type = "fused_vector";
> } else {
> $vchr = "";
> $mode = "GPR";
> $pred = "gpc_reg_operand";
> $constraint = "r";
> + $fuse_type = "fused_arith_logical";
> }
> $c4 = "${constraint},${constraint},${constraint},${constraint}";
> OUTER: foreach $outer ( @logicals ) {
> @@ -227,7 +229,7 @@ sub gen_2logical
> ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
> ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
> ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "$fuse_type")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
> EOF
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index c8cdc42533c..801e1014267 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -204,7 +204,9 @@ (define_attr "type"
> vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
> vecfloat,vecfdiv,vecdouble,mtvsr,mfvsr,crypto,
> veclogical,veccmpfx,vecexts,vecmove,
> - htm,htmsimple,dfp,mma"
> + htm,htmsimple,dfp,mma,
> + fused_arith_logical,fused_cmp_isel,fused_carry,fused_load_cmpi,
> + fused_load_load,fused_store_store,fused_addis_load,fused_mtbc,fused_vector"
> (const_string "integer"))
>
> ;; What data size does this instruction work on?
> --
> 2.27.0
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH,rs6000] Add insn types for fusion pairs
2021-04-26 18:04 [PATCH,rs6000] Add insn types for fusion pairs acsawdey
2021-04-26 20:33 ` will schmidt
2021-05-11 13:51 ` Aaron Sawdey
@ 2021-05-19 20:10 ` Segher Boessenkool
2 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2021-05-19 20:10 UTC (permalink / raw)
To: acsawdey; +Cc: gcc-patches, wschmidt, will_schmidt
Hi!
On Mon, Apr 26, 2021 at 01:04:56PM -0500, acsawdey@linux.ibm.com wrote:
> This adds new values for insn attr type for p10 fusion. The genfusion.pl
> script is modified to use them, and fusion.md regenerated to capture
> the new patterns. There are also some formatting only changes to
> fusion.md that apparently weren't captured after a previous commit
> of genfusion.pl.
That is fine, it is a generated file after all.
> @@ -227,7 +229,7 @@ sub gen_2logical
> ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
> ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
> ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2"
> - [(set_attr "type" "logical")
> + [(set_attr "type" "$fuse_type")
> (set_attr "cost" "6")
> (set_attr "length" "8")])
> EOF
You can make the rest use heredocs as well, when you have some time? It
is so much easier to read :-)
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -204,7 +204,9 @@ (define_attr "type"
> vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
> vecfloat,vecfdiv,vecdouble,mtvsr,mfvsr,crypto,
> veclogical,veccmpfx,vecexts,vecmove,
> - htm,htmsimple,dfp,mma"
> + htm,htmsimple,dfp,mma,
> + fused_arith_logical,fused_cmp_isel,fused_carry,fused_load_cmpi,
> + fused_load_load,fused_store_store,fused_addis_load,fused_mtbc,fused_vector"
Maybe you can document what the fused types are for? (Maybe we should
for some of the others as well, but most are trivial thankfully.) You
cannot use inline comments here (we are inside a quoted string), but
maybe you can put something after it? For example, fused_arith_logical
is not for an arith insn fused with a logical insn, like most others are
patterned like.
Oh, and it doesn't hurt to use more lines here, if you can group things
better that would help. And of course you can use whitespace before
names here (you cannot tell from existing entries, but :-) )
Okay for trunk, with or without such improvements. Thanks!
Segher
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-05-19 20:11 UTC | newest]
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2021-04-26 18:04 [PATCH,rs6000] Add insn types for fusion pairs acsawdey
2021-04-26 20:33 ` will schmidt
2021-05-11 13:51 ` Aaron Sawdey
2021-05-19 20:10 ` Segher Boessenkool
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