[PATCH-2, rs6000] Don't widen shift mode when target has rotate/mask instruction on original mode [PR93738]

[PATCH-2, rs6000] Don't widen shift mode when target has rotate/mask instruction on original mode [PR93738]

[HAO CHEN GUI]

Hi,
  The patch relies on the fist patch. The reason of the change is also described
in the first patch. This patch implements the target hook have_rotate_and_mask.
It also modifies some test cases. The regression of rlwimi-2.c is fixed. For
rlwinm-0.c and rlwinm-2.c, one more 32bit rotate/mask instruction is generated
and one less 64bit rotate/mask instruction.

  The patch passed regression test on Power Linux platforms. Test shows the patch
has no performance regression on SPECint.

Thanks
Gui Haochen

ChangeLog
rs6000: implement target hook have_rotate_and_mask

gcc/
	PR target/93738
	* config/rs6000/rs6000.cc (TARGET_HAVE_ROTATE_AND_MASK): Define.
	(rs6000_have_rotate_and_mask): New function.

gcc/testsuite/
	PR target/93738
	* gcc.target/powerpc/rlwimi-2.c: Adjust the number of 64bit and 32bit
	rotate instuctions.
	* gcc.target/powerpc/rlwinm-0.c: Likewise.
	* gcc.target/powerpc/rlwinm-2.c: Likewise.

patch.diff
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 44b448d2ba6..98873afddb4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1764,6 +1764,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
 #undef TARGET_CONST_ANCHOR
 #define TARGET_CONST_ANCHOR 0x8000

+#undef TARGET_HAVE_ROTATE_AND_MASK
+#define TARGET_HAVE_ROTATE_AND_MASK rs6000_have_rotate_and_mask
+
 \f

 /* Processor table.  */
@@ -29097,6 +29100,17 @@ rs6000_opaque_type_invalid_use_p (gimple *stmt)
   return false;
 }

+bool
+rs6000_have_rotate_and_mask (machine_mode mode)
+{
+  gcc_assert (SCALAR_INT_MODE_P (mode));
+
+  if (mode == SImode || mode == DImode)
+    return true;
+
+  return false;
+}
+
 struct gcc_target targetm = TARGET_INITIALIZER;

 #include "gt-rs6000.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
index bafa371db73..62344a95aa0 100644
--- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
@@ -6,10 +6,9 @@
 /* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+mr} 643 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 6728 { target lp64 } } } */

-/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 } } */

 /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c
index 4f4fca2d8ef..b6b1b227c7e 100644
--- a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c
@@ -7,10 +7,10 @@
 /* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 3081 { target lp64 } } } */

 /* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3197 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3093 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3094 { target lp64 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+rotlwi} 154 } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+srwi} 13 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 13 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 12 { target lp64 } } } */


 #define SL
diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c
index bddcfe2b76f..0315ca91dd7 100644
--- a/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c
@@ -7,9 +7,9 @@
 /* { dg-final { scan-assembler-times {(?n)^\s+rldic} 2726 { target lp64 } } } */

 /* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 833 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 720 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 721 { target lp64 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+srwi} 13 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 13 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 12 { target lp64 } } } */

 /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 2518 } } */