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From: Jiufu Guo <guojiufu@linux.ibm.com>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, linkw@gcc.gnu.org,
	rguenther@suse.de, jeffreyalaw@gmail.com
Subject: Re: [PATCH 3/3] Testcases for move sub blocks on param and ret
Date: Tue, 06 Dec 2022 09:58:30 +0800	[thread overview]
Message-ID: <7epmcxnvi1.fsf@pike.rch.stglabs.ibm.com> (raw)
In-Reply-To: <20221205193943.GX25951@gate.crashing.org> (Segher Boessenkool's message of "Mon, 5 Dec 2022 13:39:43 -0600")

Hi Segher,

Thanks for your comments!

Segher Boessenkool <segher@kernel.crashing.org> writes:

> Hi!
>
> Some comments on the testcases:
>
> On Tue, Nov 29, 2022 at 09:45:07PM +0800, Jiufu Guo wrote:
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/powerpc/pr65421-1.c
>> @@ -0,0 +1,25 @@
>> +/* PR target/65421 */
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2" } */
>> +/* { dg-require-effective-target powerpc_elfv2 } */
>> +
>> +typedef struct SA
>> +{
>> +  double a[3];
>> +  long l;
>> +} A;
>> +
>> +/* 2 vec load, 2 vec store.  */
>> +A ret_arg_pt (A *a){return *a;}
>> +
>> +/* 4 std */
>> +A ret_arg (A a) {return a;}
>> +
>> +/* 4 std */
>> +void st_arg (A a, A *p) {*p = a;}
>> +
>> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 2 } } */
>> +/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 2 } } */
>> +/* { dg-final { scan-assembler-times {\mstd\M} 8 } } */
>
> You need at least ISA 2.06 (power7) to have {l,st}xvd2x, and elfv2 does
> not guarantee that.  Have you tested on something old as well (say 970)
> to see if the lvx/stvx is generated as expected?  For that you need to
> have AltiVec enabled as well, so dg-require that?

Thanks a lot for point out this! 
Compiling this case on power7 manually, it does not generate these vector
load/store insns.  To check those insns, power7 is needed.

>
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/powerpc/pr65421.c
>> @@ -0,0 +1,22 @@
>> +/* PR target/65421 */
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2" } */
>> +/* { dg-require-effective-target powerpc_elfv2 } */
>> +
>> +typedef struct SA
>> +{
>> +  double a[3];
>> +} A;
>> +
>> +/* 3 lfd */
>> +A ret_arg_pt (A *a){return *a;}
>> +
>> +/* blr */
>> +A ret_arg (A a) {return a;}
>> +
>> +/* 3 stfd */
>> +void st_arg (A a, A *p) {*p = a;}
>> +
>> +/* { dg-final { scan-assembler-times {\mlfd\M} 3 } } */
>> +/* { dg-final { scan-assembler-times {\mstfd\M} 3 } } */
>> +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 9 } } */
>
> Comment that last one?  Just something as simple as "count insns" is
> enough :-)
Sure, thanks!

BR,
Jeff (Jiufu)

>
>
> Segher

  reply	other threads:[~2022-12-06  2:03 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-29 13:45 [PATCH 1/3] Use sub mode to move block for struct parameter Jiufu Guo
2022-11-29 13:45 ` [PATCH 2/3] Use sub mode to move block for struct returns Jiufu Guo
2022-11-29 13:45 ` [PATCH 3/3] Testcases for move sub blocks on param and ret Jiufu Guo
2022-12-05 19:39   ` Segher Boessenkool
2022-12-06  1:58     ` Jiufu Guo [this message]
2022-12-05  6:30 ` [PATCH 1/3] Use sub mode to move block for struct parameter Jiufu Guo

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