* [PATCH v4] rs6000: Update the vsx-vector-6.* tests.
@ 2023-07-06 15:33 Carl Love
2023-07-07 2:15 ` Kewen.Lin
0 siblings, 1 reply; 3+ messages in thread
From: Carl Love @ 2023-07-06 15:33 UTC (permalink / raw)
To: Kewen.Lin, Segher Boessenkool, David Edelsohn, gcc-patches
Cc: cel, Peter Bergner
GCC maintainers:
Ver 4. Fixed a few typos. Redid the tests to create separate run and
compile tests.
Ver 3. Added __attribute__ ((noipa)) to the test files. Changed some
of the scan-assembler-times checks to cover multiple similar
instructions. Change the function check macro to a macro to generate a
function to do the test and check the results. Retested on the various
processor types and BE/LE versions.
Ver 2. Switched to using code macros to generate the call to the
builtin and test the results. Added in instruction counts for the key
instruction for the builtin. Moved the tests into an additional
function call to ensure the compile doesn't replace the builtin call
code with the statically computed results. The compiler was doing this
for a few of the simpler tests.
The following patch takes the tests in vsx-vector-6-p7.h, vsx-vector-
6-p8.h, vsx-vector-6-p9.h and reorganizes them into a series of smaller
test files by functionality rather than processor version.
Tested the patch on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE with
no regresions.
Please let me know if this patch is acceptable for mainline. Thanks.
Carl
-----------------------------------------------------------------
rs6000: Update the vsx-vector-6.* tests.
The vsx-vector-6.h file is included into the processor specific test files
vsx-vector-6.p7.c, vsx-vector-6.p8.c, and vsx-vector-6.p9.c. The .h file
contains a large number of vsx vector builtin tests. The processor
specific files contain the number of instructions that the tests are
expected to generate for that processor. The tests are compile only.
This patch reworks the tests into a series of files for related tests.
The new tests consist of a runnable test to verify the builtin argument
types and the functional correctness of each builtin. There is also a
compile only test that verifies the builtins generate the expected number
of instructions for the various builtin tests.
gcc/testsuite/
* gcc.target/powerpc/vsx-vector-6-func-1op.h: New test file.
* gcc.target/powerpc/vsx-vector-6-func-1op-run.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-1op-compile.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-2lop.h: New test file.
* gcc.target/powerpc/vsx-vector-6-func-2lop-run.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-2lop-compile.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-2op.h: New test file.
* gcc.target/powerpc/vsx-vector-6-func-2op-run.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-2op-compile.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-3op.h: New test file.
* gcc.target/powerpc/vsx-vector-6-func-3op-run.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-3op-compile.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-cmp-all.h: New test file.
* gcc.target/powerpc/vsx-vector-6-func-cmp-all-run.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-cmp-all-compile.c: New test
file.
* gcc.target/powerpc/vsx-vector-6-func-cmp.h: New test file.
* gcc.target/powerpc/vsx-vector-6-func-cmp-run.c: New test file.
* gcc.target/powerpc/vsx-vector-6-func-cmp-compile.c: New test file.
* gcc.target/powerpc/vsx-vector-6.h: Remove test file.
* gcc.target/powerpc/vsx-vector-6.p7.c: Remove test file.
* gcc.target/powerpc/vsx-vector-6.p8.c: Remove test file.
* gcc.target/powerpc/vsx-vector-6.p9.c: Remove test file.
---
.../powerpc/vsx-vector-6-func-1op-compile.c | 22 ++
.../powerpc/vsx-vector-6-func-1op-run.c | 98 ++++++++
.../powerpc/vsx-vector-6-func-1op.h | 43 ++++
.../powerpc/vsx-vector-6-func-2lop-compile.c | 14 ++
.../powerpc/vsx-vector-6-func-2lop-run.c | 177 ++++++++++++++
.../powerpc/vsx-vector-6-func-2lop.h | 47 ++++
.../powerpc/vsx-vector-6-func-2op-compile.c | 21 ++
.../powerpc/vsx-vector-6-func-2op-run.c | 96 ++++++++
.../powerpc/vsx-vector-6-func-2op.h | 42 ++++
.../powerpc/vsx-vector-6-func-3op-compile.c | 17 ++
.../powerpc/vsx-vector-6-func-3op-run.c | 229 ++++++++++++++++++
.../powerpc/vsx-vector-6-func-3op.h | 73 ++++++
.../vsx-vector-6-func-cmp-all-compile.c | 17 ++
.../powerpc/vsx-vector-6-func-cmp-all-run.c | 147 +++++++++++
.../powerpc/vsx-vector-6-func-cmp-all.h | 76 ++++++
.../powerpc/vsx-vector-6-func-cmp-compile.c | 16 ++
.../powerpc/vsx-vector-6-func-cmp-run.c | 92 +++++++
.../powerpc/vsx-vector-6-func-cmp.h | 40 +++
.../gcc.target/powerpc/vsx-vector-6.h | 154 ------------
.../gcc.target/powerpc/vsx-vector-6.p7.c | 43 ----
.../gcc.target/powerpc/vsx-vector-6.p8.c | 43 ----
.../gcc.target/powerpc/vsx-vector-6.p9.c | 42 ----
22 files changed, 1267 insertions(+), 282 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-compile.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.h
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-compile.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-run.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop.h
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-compile.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-run.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op.h
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-compile.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-run.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op.h
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-compile.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-run.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all.h
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-compile.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-run.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp.h
delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h
delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-compile.c
new file mode 100644
index 00000000000..6b7d73ed66c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-compile.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -save-temps -mvsx" } */
+
+/* This file just generates calls to the various builtins and verifies the
+ expected number of instructions for each builtin were generated. */
+
+#include "vsx-vector-6-func-1op.h"
+
+/* { dg-final { scan-assembler-times {\mxvabssp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrspip\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrspim\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrspi\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrspic\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c
new file mode 100644
index 00000000000..150e372e428
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c
@@ -0,0 +1,98 @@
+/* { dg-do run { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+#define DEBUG 0
+
+/* Functional test of the one operand vector builtins. */
+#include "vsx-vector-6-func-1op.h"
+
+/* Macros to check the results of the builtin tests. */
+#define FLOAT_CHECK(NAME) \
+ f_result = float_##NAME(f_src); \
+ \
+ if ((f_result[0] != f_##NAME##_expected[0]) || \
+ (f_result[1] != f_##NAME##_expected[1]) || \
+ (f_result[2] != f_##NAME##_expected[2]) || \
+ (f_result[3] != f_##NAME##_expected[3])) \
+ { \
+ if (DEBUG) { \
+ printf("ERROR: vec_%s (float) expected value does not match\n", \
+ #NAME); \
+ printf(" expected[0] = %f; result[0] = %f\n", \
+ f_##NAME##_expected[0], f_result[0]); \
+ printf(" expected[1] = %f; result[1] = %f\n", \
+ f_##NAME##_expected[1], f_result[1]); \
+ printf(" expected[2] = %f; result[2] = %f\n", \
+ f_##NAME##_expected[2], f_result[2]); \
+ printf(" expected[3] = %f; result[3] = %f\n", \
+ f_##NAME##_expected[3], f_result[3]); \
+ } else \
+ abort(); \
+ }
+
+#define DOUBLE_CHECK(NAME) \
+ d_result = double_##NAME(d_src); \
+ \
+ if ((d_result[0] != d_##NAME##_expected[0]) \
+ || (d_result[1] != d_##NAME##_expected[1])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (double) expected value does not match\n", \
+ #NAME); \
+ printf(" expected[0] = %f; result[0] = %f\n", \
+ d_##NAME##_expected[0], d_result[0]); \
+ printf(" expected[1] = %f; result[1] = %f\n", \
+ d_##NAME##_expected[1], d_result[1]); \
+ } \
+ else \
+ abort(); \
+ }
+
+int
+main () {
+ vector float f_src = { 125.44, 23.04, -338.56, 17.64};
+ vector float f_result;
+ vector float f_abs_expected = { 125.44, 23.04, 338.56, 17.64};
+ vector float f_ceil_expected = { 126.0, 24.0, -338, 18.0};
+ vector float f_floor_expected = { 125.0, 23.0, -339, 17.0};
+ vector float f_nearbyint_expected = { 125.0, 23.0, -339, 18.0};
+ vector float f_rint_expected = { 125.0, 23.0, -339, 18.0};
+ vector float f_sqrt_expected = { 11.2, 4.8, 18.4, 4.2};
+ vector float f_trunc_expected = { 125.0, 23.0, -338, 17};
+
+ vector double d_src = { 125.44, -338.56};
+ vector double d_src_sqrt = { 125.44, 338.56};
+ vector double d_abs_src;
+ vector double d_result;
+ vector double d_abs_expected = { 125.44, 338.56};
+ vector double d_ceil_expected = { 126.0, -338.0};
+ vector double d_floor_expected = { 125.0, -339.0};
+ vector double d_nearbyint_expected = { 125.0, -339.0};
+ vector double d_rint_expected = { 125.0, -339.0};
+ vector double d_sqrt_expected = { 11.2, 18.4};
+ vector double d_trunc_expected = { 125.0, -338.0};
+
+ /* Run tests. */
+ FLOAT_CHECK (abs)
+ FLOAT_CHECK (ceil)
+ FLOAT_CHECK (floor)
+ FLOAT_CHECK (nearbyint)
+ FLOAT_CHECK (rint)
+ FLOAT_CHECK (trunc)
+
+ DOUBLE_CHECK (abs)
+ DOUBLE_CHECK (ceil)
+ DOUBLE_CHECK (floor)
+ DOUBLE_CHECK (nearbyint)
+ DOUBLE_CHECK (rint)
+ DOUBLE_CHECK (trunc)
+
+ /* Need to make sure the arguments for sqrt are always positive. Do this
+ test last as we have to change the input for the test. */
+ d_src = vec_abs (d_src);
+ DOUBLE_CHECK (sqrt)
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.h
new file mode 100644
index 00000000000..3b818fbbc66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.h
@@ -0,0 +1,43 @@
+/* The goal is to have both compile tests which verify the desired instruction
+ generation and to functionally test the builtins for correctness. This is
+ done in separate test files, vsx-vector-6-func-1op-compile.c and
+ vsx-vector-6-func-1op-run.c. The vsx-vector-6-func-1op-compile.c test file
+ only generates the calls so the instruction counts do not include the counts
+ of the instructions generated as part of the result testing. The result
+ checking code differs for BE/LE. */
+
+#include <altivec.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+void abort (void);
+
+#define FLOAT_TEST(NAME) \
+ vector float __attribute__ ((noipa)) \
+ float_##NAME (vector float f_src) \
+ { \
+ return vec_##NAME(f_src); \
+ }
+
+FLOAT_TEST (abs)
+FLOAT_TEST (ceil)
+FLOAT_TEST (floor)
+FLOAT_TEST (nearbyint)
+FLOAT_TEST (rint)
+FLOAT_TEST (trunc)
+
+#define DOUBLE_TEST(NAME) \
+ vector double __attribute__ ((noipa)) \
+ double_##NAME (vector double d_src) \
+ { \
+ return vec_##NAME(d_src); \
+ }
+
+
+DOUBLE_TEST (abs)
+DOUBLE_TEST (ceil)
+DOUBLE_TEST (floor)
+DOUBLE_TEST (nearbyint)
+DOUBLE_TEST (rint)
+DOUBLE_TEST (trunc)
+DOUBLE_TEST (sqrt)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-compile.c
new file mode 100644
index 00000000000..9828cee8893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-compile.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -save-temps -mvsx" } */
+
+/* This file just generates calls to the various builtins and verifies the
+ expected number of instructions for each builtin were generated. */
+
+#include "vsx-vector-6-func-2lop.h"
+
+/* { dg-final { scan-assembler-times {\mxxland\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxlandc\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxlnor\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxlxor\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxlor\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-run.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-run.c
new file mode 100644
index 00000000000..d1f4ecbc5bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-run.c
@@ -0,0 +1,177 @@
+/* { dg-do run { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+#define DEBUG 0
+
+/* Functional test of the two operand logical vector builtins. */
+#include "vsx-vector-6-func-2lop.h"
+
+/* Macros to check the results of the builtin tests. */
+#define FLOAT_CHECK(NAME) \
+ f_result = vec_##NAME (f_src_a, f_src_b); \
+ \
+ if ((f_result[0] != f_##NAME##_expected[0]) \
+ || (f_result[1] != f_##NAME##_expected[1]) \
+ || (f_result[2] != f_##NAME##_expected[2]) \
+ || (f_result[3] != f_##NAME##_expected[3])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (float) expected value does not match\n", \
+ #NAME); \
+ for (i = 0; i < 4; i++) \
+ { \
+ conv_result.f[i] = f_result[i]; \
+ printf(" expected[%d] = 0x%x; result[%d] = 0x%x\n", i, \
+ conv_exp.u[i], i, conv_result.u[i]); \
+ } \
+ } \
+ else \
+ abort(); \
+ }
+
+#define DOUBLE_CHECK(NAME) \
+ d_result = vec_##NAME (d_src_a, d_src_b); \
+ \
+ if ((d_result[0] != d_##NAME##_expected[0]) \
+ || (d_result[1] != d_##NAME##_expected[1])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (double) expected value does not match\n", \
+ #NAME); \
+ for (i = 0; i < 2; i++) \
+ { \
+ conv_result.d[i] = d_result[i]; \
+ printf(" expected[%d] = 0x%lx; result[%d] = 0x%lx\n", i, \
+ conv_exp.ul, i, conv_result.ul); \
+ } \
+ } \
+ else \
+ abort(); \
+ }
+
+int
+main () {
+ int i;
+
+ vector float f_src_a = { 1.0, 2.0, 3.0, 4.0};
+ vector float f_src_b = { 1.0, 3.0, -3.0, 2.0};
+ vector float f_and_expected, f_andc_expected, f_nor_expected, f_or_expected;
+ vector float f_xor_expected;
+ vector float f_result;
+
+ vector double d_src_a = { 8.0, 10.0};
+ vector double d_src_b = { 12.0, 2.0};
+ vector double d_and_expected, d_andc_expected, d_nor_expected;
+ vector double d_result;
+ vector double d_or_expected, d_xor_expected;
+
+ /* Calculate expected results. */
+ /* AND, float */
+ for (i = 0; i < 4; i++)
+ {
+ conv_src_a.f[i] = f_src_a[i];
+ conv_src_b.f[i] = f_src_b[i];
+ conv_exp.u[i] = conv_src_a.u[i] & conv_src_b.u[i];
+ f_and_expected[i] = conv_exp.f[i];
+ }
+
+ /* ANDC, float */
+ for (i = 0; i < 4; i++)
+ {
+ conv_src_a.f[i] = f_src_a[i];
+ conv_src_b.f[i] = f_src_b[i];
+ conv_exp.u[i] = conv_src_a.u[i] & ~conv_src_b.u[i];
+ f_andc_expected[i] = conv_exp.f[i];
+ }
+
+ /* NOR, max */
+ for (i = 0; i < 4; i++)
+ {
+ conv_src_a.f[i] = f_src_a[i];
+ conv_src_b.f[i] = f_src_b[i];
+ conv_exp.u[i] = ~(conv_src_a.u[i] | conv_src_b.u[i]);
+ f_nor_expected[i] = conv_exp.f[i];
+ }
+
+ /* OR, float */
+ for (i = 0; i < 4; i++)
+ {
+ conv_src_a.f[i] = f_src_a[i];
+ conv_src_b.f[i] = f_src_b[i];
+ conv_exp.u[i] = conv_src_a.u[i] | conv_src_b.u[i];
+ f_or_expected[i] = conv_exp.f[i];
+ }
+
+ /* XOR, float */
+ for (i = 0; i < 4; i++)
+ {
+ conv_src_a.f[i] = f_src_a[i];
+ conv_src_b.f[i] = f_src_b[i];
+ conv_exp.u[i] = conv_src_a.u[i] ^ conv_src_b.u[i];
+ f_xor_expected[i] = conv_exp.f[i];
+ }
+
+ /* AND, double */
+ for (i = 0; i < 2; i++)
+ {
+ conv_src_a.d[i] = d_src_a[i];
+ conv_src_b.d[i] = d_src_b[i];
+ conv_exp.ul[i] = conv_src_a.ul[i] & conv_src_b.ul[i];
+ d_and_expected[i] = conv_exp.d[i];
+ }
+
+ /* ANDC, double */
+ for (i = 0; i < 2; i++)
+ {
+ conv_src_a.d[i] = d_src_a[i];
+ conv_src_b.d[i] = d_src_b[i];
+ conv_exp.ul[i] = conv_src_a.ul[i] & ~conv_src_b.ul[i];
+ d_andc_expected[i] = conv_exp.d[i];
+ }
+
+ /* NOR, double */
+ for (i = 0; i < 2; i++)
+ {
+ conv_src_a.d[i] = d_src_a[i];
+ conv_src_b.d[i] = d_src_b[i];
+ conv_exp.ul[i] = ~(conv_src_a.ul[i] | conv_src_b.ul[i]);
+ d_nor_expected[i] = conv_exp.d[i];
+ }
+
+ /* OR, double */
+ for (i = 0; i < 2; i++)
+ {
+ conv_src_a.d[i] = d_src_a[i];
+ conv_src_b.d[i] = d_src_b[i];
+ conv_exp.ul[i] = conv_src_a.ul[i] | conv_src_b.ul[i];
+ d_or_expected[i] = conv_exp.d[i];
+ }
+
+ /* XOR, double */
+ for (i = 0; i < 2; i++)
+ {
+ conv_src_a.d[i] = d_src_a[i];
+ conv_src_b.d[i] = d_src_b[i];
+ conv_exp.ul[i] = conv_src_a.ul[i] ^ conv_src_b.ul[i];
+ d_xor_expected[i] = conv_exp.d[i];
+ }
+
+ /* Run tests. */
+ FLOAT_CHECK (and)
+ FLOAT_CHECK (andc)
+ FLOAT_CHECK (nor)
+ FLOAT_CHECK (or)
+ FLOAT_CHECK (xor)
+
+ DOUBLE_CHECK (and)
+ DOUBLE_CHECK (andc)
+ DOUBLE_CHECK (nor)
+ DOUBLE_CHECK (or)
+ DOUBLE_CHECK (xor)
+
+ return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop.h
new file mode 100644
index 00000000000..064bbb66c10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop.h
@@ -0,0 +1,47 @@
+/* The goal is to have both compile tests which verify the desired instruction
+ generation and to functionally test the builtins for correctness. This is
+ done in separate test files, vsx-vector-6-func-2lop-compile.c and
+ vsx-vector-6-func-2lop-run.c. The vsx-vector-6-func-2lop-compile.c test
+ file only generates the calls so the instruction counts do not include the
+ counts of the instructions generated as part of the result testing. The
+ result checking code differs for BE/LE. */
+
+
+#include <altivec.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+union conv_t {
+ vector float f;
+ vector unsigned int u;
+ vector double d;
+ vector unsigned long ul;
+} conv_result, conv_exp, conv_src_a, conv_src_b;
+
+void abort (void);
+
+#define FLOAT_TEST(NAME) \
+ vector float __attribute__ ((noipa)) \
+ float_##NAME (vector float f_src_a, vector float f_src_b) \
+ { \
+ return vec_##NAME (f_src_a, f_src_b); \
+ }
+
+FLOAT_TEST (and)
+FLOAT_TEST (andc)
+FLOAT_TEST (nor)
+FLOAT_TEST (or)
+FLOAT_TEST (xor)
+
+#define DOUBLE_TEST(NAME) \
+ vector double __attribute__ ((noipa)) \
+ double_##NAME (vector double d_src_a, vector double d_src_b) \
+ { \
+ return vec_##NAME (d_src_a, d_src_b); \
+ }
+
+DOUBLE_TEST (and)
+DOUBLE_TEST (andc)
+DOUBLE_TEST (nor)
+DOUBLE_TEST (or)
+DOUBLE_TEST (xor)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-compile.c
new file mode 100644
index 00000000000..d502b42a792
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-compile.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -save-temps -mvsx" } */
+
+/* This file just generates calls to the various builtins and verifies the
+ expected number of instructions for each builtin were generated. */
+
+#include "vsx-vector-6-func-2op.h"
+
+/* { dg-final { scan-assembler-times {\mxvaddsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvdivsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmulsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvsubsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvadddp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvdivdp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmindp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmuldp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvsubdp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmaxsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvminsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmaxdp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-run.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-run.c
new file mode 100644
index 00000000000..05e1fc13f1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-run.c
@@ -0,0 +1,96 @@
+/* { dg-do run { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+#define DEBUG 0
+
+/* Functional test of the two operand vector builtins. */
+#include "vsx-vector-6-func-2op.h"
+
+/* Macros to check the results of the builtin tests. */
+#define FLOAT_CHECK(NAME) \
+ f_result = float_##NAME(f_src_a, f_src_b); \
+ \
+ if ((f_result[0] != f_##NAME##_expected[0]) \
+ || (f_result[1] != f_##NAME##_expected[1]) \
+ || (f_result[2] != f_##NAME##_expected[2]) \
+ || (f_result[3] != f_##NAME##_expected[3])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (float) expected value does not match\n", \
+ #NAME); \
+ printf(" expected[0] = %f; result[0] = %f\n", \
+ f_##NAME##_expected[0], f_result[0]); \
+ printf(" expected[1] = %f; result[1] = %f\n", \
+ f_##NAME##_expected[1], f_result[1]); \
+ printf(" expected[2] = %f; result[2] = %f\n", \
+ f_##NAME##_expected[2], f_result[2]); \
+ printf(" expected[3] = %f; result[3] = %f\n", \
+ f_##NAME##_expected[3], f_result[3]); \
+ } \
+ else \
+ abort(); \
+ }
+
+#define DOUBLE_CHECK(NAME) \
+ d_result = vec_##NAME (d_src_a, d_src_b); \
+ \
+ if ((d_result[0] != d_##NAME##_expected[0]) \
+ || (d_result[1] != d_##NAME##_expected[1])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s(double) expected value does not match\n", \
+ #NAME); \
+ printf(" expected[0] = %f; result[0] = %f\n", \
+ d_##NAME##_expected[0], d_result[0]); \
+ printf(" expected[1] = %f; result[1] = %f\n", \
+ d_##NAME##_expected[1], d_result[1]); \
+ } \
+ else \
+ abort(); \
+ }
+
+void abort (void);
+
+int
+main () {
+ int i;
+ vector float f_src_a = { 126.0, 23.0, -338.0, 17.0};
+ vector float f_src_b = { 2.00, -4.0, 1.0, 4.0};
+ vector float f_result;
+ vector float f_add_expected = { 128.0, 19.0, -337.0, 21.0};
+ vector float f_div_expected = { 63.0, -5.75, -338, 4.25};
+ vector float f_max_expected = { 126.0, 23.0, 1.0, 17.0};
+ vector float f_min_expected = { 2.0, -4.0, -338.0, 4.0};
+ vector float f_mul_expected = { 252, -92.0, -338, 68.0};
+ vector float f_sub_expected = { 124.0, 27.0, -339.0, 13.0};
+
+ vector double d_src_a = { 125.44, -338.56};
+ vector double d_src_b = { 4.0, -2.0};
+ vector double d_result;
+ vector double d_add_expected = { 129.44, -340.56};
+ vector double d_div_expected = { 31.360000, 169.280000};
+ vector double d_max_expected = { 125.44, -2.0};
+ vector double d_min_expected = { 4.0, -338.56};
+ vector double d_mul_expected = { 501.760000, 677.120000};
+ vector double d_sub_expected = { 121.440000, -336.560000};
+
+ /* Run tests. */
+ FLOAT_CHECK (add)
+ FLOAT_CHECK (div)
+ FLOAT_CHECK (max)
+ FLOAT_CHECK (min)
+ FLOAT_CHECK (mul)
+ FLOAT_CHECK (sub)
+
+ DOUBLE_CHECK (add)
+ DOUBLE_CHECK (div)
+ DOUBLE_CHECK (max)
+ DOUBLE_CHECK (min)
+ DOUBLE_CHECK (mul)
+ DOUBLE_CHECK (sub)
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op.h
new file mode 100644
index 00000000000..537737a2389
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op.h
@@ -0,0 +1,42 @@
+/* The goal is to have both compile tests which verify the desired instruction
+ generation and to functionally test the builtins for correctness. This is
+ done in separate test files, vsx-vector-6-func-2op-compile.c and
+ vsx-vector-6-func-2op-run.c. The vsx-vector-6-func-2op-compile.c test file
+ only generates the calls so the instruction counts do not include the counts
+ of the instructions generated as part of the result testing. The result
+ checking code differs for BE/LE. */
+
+
+#include <altivec.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+void abort (void);
+
+#define FLOAT_TEST(NAME) \
+ vector float __attribute__ ((noipa)) \
+ float_##NAME(vector float f_src_a, vector float f_src_b) \
+ { \
+ return vec_##NAME (f_src_a, f_src_b); \
+ }
+
+FLOAT_TEST (add)
+FLOAT_TEST (div)
+FLOAT_TEST (max)
+FLOAT_TEST (min)
+FLOAT_TEST (mul)
+FLOAT_TEST (sub)
+
+#define DOUBLE_TEST(NAME) \
+ vector double __attribute__ ((noipa)) \
+ double_##NAME(vector double d_src_a, vector double d_src_b) \
+ { \
+ return vec_##NAME (d_src_a, d_src_b); \
+ }
+
+DOUBLE_TEST (add)
+DOUBLE_TEST (div)
+DOUBLE_TEST (max)
+DOUBLE_TEST (min)
+DOUBLE_TEST (mul)
+DOUBLE_TEST (sub)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-compile.c
new file mode 100644
index 00000000000..a6d4364c10d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-compile.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -save-temps -mvsx" } */
+
+/* This file just generates calls to the various builtins and verifies the
+ expected number of instructions for each builtin were generated. */
+
+#include "vsx-vector-6-func-3op.h"
+
+/* { dg-final { scan-assembler-times {\mvmsumshs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvmsumuhs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmaddmsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmaddmdp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmsubmsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvmsubmdp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\m(?:v|xx)permr?\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxxsel\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-run.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-run.c
new file mode 100644
index 00000000000..32c0f2807c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-run.c
@@ -0,0 +1,229 @@
+/* { dg-do run { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+#define DEBUG 0
+
+/* Functional test of the one operand vector builtins. */
+#include "vsx-vector-6-func-3op.h"
+
+/* Macros to check the results of the builtin tests. */
+#define FLOAT_CHECK(NAME) \
+ f_result = vec_##NAME (f_src_a, f_src_b, f_src_c); \
+ \
+ if ((f_result[0] != f_##NAME##_expected[0]) \
+ || (f_result[1] != f_##NAME##_expected[1]) \
+ || (f_result[2] != f_##NAME##_expected[2]) \
+ || (f_result[3] != f_##NAME##_expected[3])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (float) expected value does not match\n", \
+ #NAME); \
+ printf(" expected[0] = %f; result[0] = %f\n", \
+ f_##NAME##_expected[0], f_result[0]); \
+ printf(" expected[1] = %f; result[1] = %f\n", \
+ f_##NAME##_expected[1], f_result[1]); \
+ printf(" expected[2] = %f; result[2] = %f\n", \
+ f_##NAME##_expected[2], f_result[2]); \
+ printf(" expected[3] = %f; result[3] = %f\n", \
+ f_##NAME##_expected[3], f_result[3]); \
+ } \
+ else \
+ abort(); \
+ }
+
+#define DOUBLE_CHECK(NAME) \
+ d_result = vec_##NAME (d_src_a, d_src_b, d_src_c); \
+ \
+ if ((d_result[0] != d_##NAME##_expected[0]) \
+ || (d_result[1] != d_##NAME##_expected[1])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (double) expected value does not match\n", \
+ #NAME); \
+ printf(" expected[0] = %f; result[0] = %f\n", \
+ d_##NAME##_expected[0], d_result[0]); \
+ printf(" expected[1] = %f; result[1] = %f\n", \
+ d_##NAME##_expected[1], d_result[1]); \
+ } \
+ else \
+ abort(); \
+ }
+
+void __attribute__ ((noipa))
+short_tests (vector short ss_src_a, vector short ss_src_b, vector int si_src_c,
+ vector unsigned short us_src_a, vector unsigned short us_src_b,
+ vector unsigned int ui_src_c, vector int si_expected,
+ vector unsigned int ui_expected)
+{
+ /* These tests were put into a function to ensure the compiler doesn't try to
+ compute the results at compile time. */
+ vector int si_result;
+ vector unsigned int ui_result;
+
+ /* Vector multiply-sum saturated */
+ ui_result = short_msums_unsigned (us_src_a, us_src_b, ui_src_c);
+ if ((ui_result[0] != ui_expected[0])
+ || (ui_result[1] != ui_expected[1])
+ || (ui_result[2] != ui_expected[2])
+ || (ui_result[3] != ui_expected[3]))
+#if DEBUG
+ {
+ printf("ERROR: vec_msums (unsigned) expected value does not match\n");
+ printf(" expected[0] = %d; result[0] = %d\n",
+ ui_expected[0], ui_result[0]);
+ printf(" expected[1] = %d; result[1] = %d\n",
+ ui_expected[1], ui_result[1]);
+ printf(" expected[2] = %d; result[2] = %d\n",
+ ui_expected[2], ui_result[2]);
+ printf(" expected[3] = %d; result[3] = %d\n",
+ ui_expected[3], ui_result[3]);
+ }
+#else
+ abort();
+#endif
+
+ si_result = short_msums_signed (ss_src_a, ss_src_b, si_src_c);
+ if ((si_result[0] != si_expected[0])
+ || (si_result[1] != si_expected[1])
+ || (si_result[2] != si_expected[2])
+ || (si_result[3] != si_expected[3]))
+#if DEBUG
+ {
+ printf("ERROR: vec_msums (signed) expected value does not match\n");
+ printf(" expected[0] = %d; result[0] = %d\n",
+ si_expected[0], si_result[0]);
+ printf(" expected[1] = %d; result[1] = %d\n",
+ si_expected[1], si_result[1]);
+ printf(" expected[2] = %d; result[2] = %d\n",
+ si_expected[2], si_result[2]);
+ printf(" expected[3] = %d; result[3] = %d\n",
+ si_expected[3], si_result[3]);
+ }
+#else
+ abort();
+#endif
+}
+
+void __attribute__ ((noipa))
+vector_sel_test (vector double d_src_a, vector double d_src_b,
+ vector unsigned long long ull_src_c,
+ vector bool long long bll_src_c ,
+ vector double d_selectb_expected,
+ vector double d_selectu_expected)
+{
+ vector double d_result;
+
+ /* Vector select */
+ d_result = double_sel_test (d_src_a, d_src_b, ull_src_c);
+
+ if ((d_result[0] != d_selectu_expected[0])
+ || (d_result[1] != d_selectu_expected[1]))
+#if DEBUG
+ {
+ printf("ERROR: vec_sel (double, unsigned long long) expected value does not match\n");
+ printf(" expected[0] = %f; result[0] = %f\n",
+ d_selectu_expected[0], d_result[0]);
+ printf(" expected[1] = %f; result[1] = %f\n",
+ d_selectu_expected[1], d_result[1]);
+ }
+#else
+ abort();
+#endif
+
+ d_result = bool_sel_test (d_src_a, d_src_b, bll_src_c);
+
+ if ((d_result[0] != d_selectb_expected[0])
+ || (d_result[1] != d_selectb_expected[1]))
+#if DEBUG
+ {
+ printf("ERROR: vec_sel (double, bool long long) expected value does not match\n");
+ printf(" expected[0] = %f; result[0] = %f\n",
+ d_selectb_expected[0], d_result[0]);
+ printf(" expected[1] = %f; result[1] = %f\n",
+ d_selectb_expected[1], d_result[1]);
+ }
+#else
+ abort();
+#endif
+}
+
+void __attribute__ ((noipa))
+vector_permute_test (vector double d_src_a, vector double d_src_b,
+ vector unsigned char uc_src_c,
+ vector double d_perm_expected)
+{
+ vector double d_result;
+
+ /* Vector permute */
+ d_result = double_permute_test (d_src_a, d_src_b, uc_src_c);
+
+ if ((d_result[0] != d_perm_expected[0])
+ || (d_result[1] != d_perm_expected[1]))
+#if DEBUG
+ {
+ printf("ERROR: vec_perm (double, unsigned char) expected value does not match\n");
+ printf(" expected[0] = %f; result[0] = %f\n",
+ d_perm_expected[0], d_result[0]);
+ printf(" expected[1] = %f; result[1] = %f\n",
+ d_perm_expected[1], d_result[1]);
+ }
+#else
+ abort();
+#endif
+
+}
+
+int
+main () {
+ int i;
+
+ vector unsigned char uc_src_c = {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
+ 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF};
+ vector short ss_src_a = { 1, 2, 3, 4, 5, 6, 7, 8};
+ vector short ss_src_b = { -10, 20, 30, 40, 50, 60, 70, 80};
+ vector int si_src_c = { 13, -27, 39, 48};
+ vector int si_expected = {43, 223, 649, 1178};
+ vector unsigned short us_src_a = { 31, 32, 33, 34, 1, 2, 3, 4};
+ vector unsigned short us_src_b = { 11, 7, 30, 90, 39, 48, 28, 64};
+ vector unsigned int ui_src_c = { 13, 17, 39, 91};
+
+ vector unsigned int ui_expected = {578, 4067, 174, 431};
+ vector float f_src_a = { 126.0, 23.0, -338.0, 17.0};
+ vector float f_src_b = { 2.0, -4.0, 1.0, 4.0};
+ vector float f_src_c = { 6.0, -8.0, 7.0, 5.0};
+ vector float f_madd_expected = { 258.0, -100.0, -331.0, 73.0};
+ vector float f_msub_expected = { 246.0, -84.0, -345.0, 63.0};
+ vector float f_result;
+
+ vector unsigned long long ull_src_c = {0xFFFFFFFFFFFFFFFF,
+ 0xFFFFFFFFFFFFFFFF};
+ vector bool long long bll_src_c = {0, 0};
+ vector double d_src_a = { 125.44, -338.56};
+ vector double d_src_b = { 4.0, -2.0};
+ vector double d_src_c = { 7.0, -3.0};
+ vector double d_madd_expected = { 508.76, 674.12};
+ vector double d_msub_expected = { 494.76, 680.12};
+ vector double d_selectb_expected = { 125.44, -338.56};
+ vector double d_selectu_expected = { 4.0, -2.0};
+ vector double d_perm_expected = { 125.44, -338.56};
+ vector double d_result;
+
+ /* Run tests. */
+ short_tests (ss_src_a, ss_src_b, si_src_c, us_src_a, us_src_b,
+ ui_src_c, si_expected, ui_expected);
+
+ FLOAT_CHECK (madd)
+ FLOAT_CHECK (msub)
+
+ DOUBLE_CHECK (madd)
+ DOUBLE_CHECK (msub)
+
+ vector_sel_test (d_src_a, d_src_b, ull_src_c, bll_src_c, d_selectb_expected,
+ d_selectu_expected);
+ vector_permute_test (d_src_a, d_src_b, uc_src_c, d_perm_expected);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op.h
new file mode 100644
index 00000000000..c326d62c12d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op.h
@@ -0,0 +1,73 @@
+/* The goal is to have both compile tests which verify the desired instruction
+ generation and to functionally test the builtins for correctness. This is
+ done in separate test files, vsx-vector-6-func-3op-compile.c and
+ vsx-vector-6-func-3op-run.c. The vsx-vector-6-func-3op-compile.c test file
+ only generates the calls so the instruction counts do not include the counts
+ of the instructions generated as part of the result testing. The result
+ checking code differs for BE/LE. */
+
+#include <altivec.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+void abort (void);
+
+/* Macro to create call to builtin. */
+#define FLOAT_TEST(NAME) \
+ vector float __attribute__ ((noipa)) \
+ float_##NAME(vector float f_src_a, vector float f_src_b, \
+ vector float f_src_c) \
+ { \
+ return vec_##NAME (f_src_a, f_src_b, f_src_c); \
+ }
+
+FLOAT_TEST (madd)
+FLOAT_TEST (msub)
+
+#define DOUBLE_TEST(NAME) \
+ vector double __attribute__ ((noipa)) \
+ double_##NAME(vector double d_src_a, vector double d_src_b, \
+ vector double d_src_c) \
+ { \
+ return vec_##NAME (d_src_a, d_src_b, d_src_c); \
+ }
+
+DOUBLE_TEST (madd)
+DOUBLE_TEST (msub)
+
+vector unsigned int __attribute__ ((noipa))
+short_msums_unsigned (vector unsigned short us_src_a,
+ vector unsigned short us_src_b,
+ vector unsigned int ui_src_c)
+{
+ return vec_msums (us_src_a, us_src_b, ui_src_c);
+}
+
+vector int __attribute__ ((noipa))
+short_msums_signed (vector short ss_src_a, vector short ss_src_b,
+ vector int si_src_c)
+{
+ return vec_msums (ss_src_a, ss_src_b, si_src_c);
+}
+
+vector double __attribute__ ((noipa))
+double_sel_test (vector double d_src_a, vector double d_src_b,
+ vector unsigned long long ull_src_c)
+{
+ return vec_sel (d_src_a, d_src_b, ull_src_c);
+ }
+
+vector double __attribute__ ((noipa))
+bool_sel_test (vector double d_src_a, vector double d_src_b,
+ vector bool long long bll_src_c)
+{
+ return vec_sel (d_src_a, d_src_b, bll_src_c);
+}
+
+vector double __attribute__ ((noipa))
+double_permute_test (vector double d_src_a, vector double d_src_b,
+ vector unsigned char uc_src_c)
+{
+ return vec_perm (d_src_a, d_src_b, uc_src_c);
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-compile.c
new file mode 100644
index 00000000000..d546bbdeecb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-compile.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -save-temps -mvsx" } */
+
+/* This file just generates calls to the various builtins and verifies the
+ expected number of instructions for each builtin were generated. */
+
+#include "vsx-vector-6-func-cmp-all.h"
+
+/* { dg-final { scan-assembler-times {\mxvcmpeqsp\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtsp\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgesp\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpeqdp\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgedp\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtdp\M} 4 } } */
+
+
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-run.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-run.c
new file mode 100644
index 00000000000..736c727d4ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-run.c
@@ -0,0 +1,147 @@
+/* { dg-do run { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -save-temps -mvsx" } */
+
+#define DEBUG 0
+
+#include "vsx-vector-6-func-cmp-all.h"
+
+#define FLOAT_1ARG_CHECK(NAME) \
+ f_result = vec_##NAME (f_src); \
+ \
+ if (f_result != f_##NAME##_expected) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (float) expected value does not match\n", \
+ #NAME); \
+ printf(" expected = %d; result = %d\n", \
+ f_##NAME##_expected, f_result); \
+ } \
+ else \
+ abort(); \
+ }
+
+#define FLOAT_2ARG_CHECK(NAME) \
+ f_result = vec_##NAME (f_src_a, f_src_b); \
+ \
+ if (f_result != f_##NAME##_expected) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (float, float) expected value does not match\n", \
+ #NAME); \
+ printf(" expected = %d; result = %d\n", \
+ f_##NAME##_expected, f_result); \
+ } \
+ else \
+ abort(); \
+ }
+
+#define DOUBLE_1ARG_CHECK(NAME ) \
+ d_result = vec_##NAME (d_src); \
+ \
+ if (d_result != d_##NAME##_expected) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (double) expected value does not match\n", \
+ #NAME); \
+ printf(" expected = %d; result = %d\n", \
+ d_##NAME##_expected, d_result); \
+ } \
+ else \
+ abort(); \
+ }
+
+#define DOUBLE_2ARG_CHECK(NAME) \
+ d_result = vec_##NAME (d_src_a, d_src_b); \
+ \
+ if (d_result != d_##NAME##_expected) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (double, double) expected value does not match\n", \
+ #NAME); \
+ printf(" expected = %d; result = %d\n", \
+ d_##NAME##_expected, d_result); \
+ } \
+ else \
+ abort(); \
+ }
+
+int
+main () {
+ vector float f_src = {126.0, 23.0, -338.0, 17.0};
+ vector float f_src_a = {126.0, 23.0, -338.0, 17.0};
+ vector float f_src_b = {2.00, 23.0, 1.0, 4.0};
+ bool f_result;
+ bool f_all_eq_expected = 0;
+ bool f_all_gt_expected = 0;
+ bool f_all_ge_expected = 0;
+ bool f_all_lt_expected = 0;
+ bool f_all_le_expected = 0;
+ bool f_all_nan_expected = 0;
+ bool f_all_numeric_expected = 1;
+ bool f_any_eq_expected = 1;
+ bool f_any_gt_expected = 1;
+ bool f_any_ge_expected = 1;
+ bool f_any_lt_expected = 1;
+ bool f_any_le_expected = 1;
+ bool f_any_nan_expected = 0;
+ bool f_any_numeric_expected = 1;
+
+ vector double d_src = { 125.44, -338.56};
+ vector double d_src_a = { 125.44, -338.56};
+ vector double d_src_b = d_src_a;
+ bool d_result;
+ bool d_all_eq_expected = 1;
+ bool d_all_gt_expected = 0;
+ bool d_all_ge_expected = 1;
+ bool d_all_lt_expected = 0;
+ bool d_all_le_expected = 1;
+ bool d_all_nan_expected = 0;
+ bool d_all_numeric_expected = 1;
+ bool d_any_eq_expected = 1;
+ bool d_any_gt_expected = 0;
+ bool d_any_ge_expected = 1;
+ bool d_any_lt_expected = 0;
+ bool d_any_le_expected = 1;
+ bool d_any_nan_expected = 0;
+ bool d_any_numeric_expected = 1;
+
+ /* Run tests. */
+ FLOAT_1ARG_CHECK (all_nan)
+ FLOAT_1ARG_CHECK (all_numeric)
+ FLOAT_1ARG_CHECK (any_nan)
+ FLOAT_1ARG_CHECK (any_numeric)
+
+ FLOAT_2ARG_CHECK (all_eq)
+ FLOAT_2ARG_CHECK (all_gt)
+ FLOAT_2ARG_CHECK (all_ge)
+ FLOAT_2ARG_CHECK (all_lt)
+ FLOAT_2ARG_CHECK (all_le)
+ FLOAT_2ARG_CHECK (any_eq)
+ FLOAT_2ARG_CHECK (any_gt)
+ FLOAT_2ARG_CHECK (any_ge)
+ FLOAT_2ARG_CHECK (any_lt)
+ FLOAT_2ARG_CHECK (any_le)
+
+ DOUBLE_1ARG_CHECK (all_nan)
+ DOUBLE_1ARG_CHECK (all_numeric)
+ DOUBLE_1ARG_CHECK (any_nan)
+ DOUBLE_1ARG_CHECK (any_numeric)
+
+ DOUBLE_2ARG_CHECK (all_eq)
+ DOUBLE_2ARG_CHECK (all_gt)
+ DOUBLE_2ARG_CHECK (all_ge)
+ DOUBLE_2ARG_CHECK (all_lt)
+ DOUBLE_2ARG_CHECK (all_le)
+ DOUBLE_2ARG_CHECK (any_eq)
+ DOUBLE_2ARG_CHECK (any_gt)
+ DOUBLE_2ARG_CHECK (any_ge)
+ DOUBLE_2ARG_CHECK (any_lt)
+ DOUBLE_2ARG_CHECK (any_le)
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all.h
new file mode 100644
index 00000000000..fd6d176897a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all.h
@@ -0,0 +1,76 @@
+/* The goal is to have both compile tests which verify the desired instruction
+ generation and to functionally test the builtins for correctness. This is
+ done in separate test files, vsx-vector-6-func-cmp-all-compile.c and
+ vsx-vector-6-func-cmp-all-run.c. The vsx-vector-6-func-cmp-all-compile.c
+ test file only generates the calls so the instruction counts do not include
+ the counts of the instructions generated as part of the result testing. The
+ result checking code differs for BE/LE. */
+
+#include <altivec.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+
+void abort (void);
+
+#define FLOAT_1ARG_TEST(NAME) \
+ bool __attribute__ ((noipa)) \
+ float_1arg_##NAME (vector float f_src, bool f_##NAME##_expected) \
+ { \
+ return vec_##NAME (f_src); \
+ }
+
+FLOAT_1ARG_TEST (all_nan)
+FLOAT_1ARG_TEST (all_numeric)
+FLOAT_1ARG_TEST (any_nan)
+FLOAT_1ARG_TEST (any_numeric)
+
+#define FLOAT_2ARG_TEST(NAME) \
+ bool __attribute__ ((noipa)) \
+ float_2arg_##NAME (vector float f_src_a, vector float f_src_b, \
+ bool f_##NAME##_expected) \
+ { \
+ return vec_##NAME (f_src_a, f_src_b); \
+ }
+
+FLOAT_2ARG_TEST (all_eq)
+FLOAT_2ARG_TEST (all_gt)
+FLOAT_2ARG_TEST (all_ge)
+FLOAT_2ARG_TEST (all_lt)
+FLOAT_2ARG_TEST (all_le)
+FLOAT_2ARG_TEST (any_eq)
+FLOAT_2ARG_TEST (any_gt)
+FLOAT_2ARG_TEST (any_ge)
+FLOAT_2ARG_TEST (any_lt)
+FLOAT_2ARG_TEST (any_le)
+
+#define DOUBLE_1ARG_TEST(NAME ) \
+ bool __attribute__ ((noipa)) \
+ double_1arg_##NAME (vector double d_src, bool d_##NAME##_expected) \
+ { \
+ return vec_##NAME (d_src); \
+ }
+
+DOUBLE_1ARG_TEST (all_nan)
+DOUBLE_1ARG_TEST (all_numeric)
+DOUBLE_1ARG_TEST (any_nan)
+DOUBLE_1ARG_TEST (any_numeric)
+
+#define DOUBLE_2ARG_TEST(NAME) \
+ bool __attribute__ ((noipa)) \
+ double_2arg_##NAME (vector double d_src_a, vector double d_src_b, \
+ bool d_##NAME##_expected) \
+ { \
+ return vec_##NAME (d_src_a, d_src_b); \
+ }
+
+DOUBLE_2ARG_TEST (all_eq)
+DOUBLE_2ARG_TEST (all_gt)
+DOUBLE_2ARG_TEST (all_ge)
+DOUBLE_2ARG_TEST (all_lt)
+DOUBLE_2ARG_TEST (all_le)
+DOUBLE_2ARG_TEST (any_eq)
+DOUBLE_2ARG_TEST (any_gt)
+DOUBLE_2ARG_TEST (any_ge)
+DOUBLE_2ARG_TEST (any_lt)
+DOUBLE_2ARG_TEST (any_le)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-compile.c
new file mode 100644
index 00000000000..699154f7636
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-compile.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -save-temps -mvsx" } */
+
+
+/* This file just generates calls to the various builtins and verifies the
+ expected number of instructions for each builtin were generated. */
+
+#include "vsx-vector-6-func-cmp.h"
+
+/* { dg-final { scan-assembler-times {\mxvcmpeqsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtsp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgesp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpeqdp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgedp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtdp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-run.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-run.c
new file mode 100644
index 00000000000..0a17cd99a8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-run.c
@@ -0,0 +1,92 @@
+/* { dg-do run { target lp64 } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+#define DEBUG 0
+
+/* This file just generates calls to the various builtins and verifies the
+ expected number of instructions for each builtin were generated. */
+
+#include "vsx-vector-6-func-cmp.h"
+
+/* Macros to check the results of the builtin tests. */
+#define FLOAT_CHECK(NAME) \
+ f_result = vec_##NAME (f_src_a, f_src_b); \
+ \
+ if ((f_result[0] != f_##NAME##_expected[0]) \
+ || (f_result[1] != f_##NAME##_expected[1]) \
+ || (f_result[2] != f_##NAME##_expected[2]) \
+ || (f_result[3] != f_##NAME##_expected[3])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (float) expected value does not match\n", \
+ #NAME); \
+ printf(" expected[0] = 0x%x; result[0] =0x%x\n", \
+ f_##NAME##_expected[0], f_result[0]); \
+ printf(" expected[1] = 0x%x; result[1] = 0x%x\n", \
+ f_##NAME##_expected[1], f_result[1]); \
+ printf(" expected[2] = 0x%x; result[2] = 0x%x\n", \
+ f_##NAME##_expected[2], f_result[2]); \
+ printf(" expected[3] = 0x%x; result[3] = 0x%x\n", \
+ f_##NAME##_expected[3], f_result[3]); \
+ } \
+ else \
+ abort(); \
+ }
+
+#define DOUBLE_CHECK(NAME) \
+ d_result = vec_##NAME (d_src_a, d_src_b); \
+ \
+ if ((d_result[0] != d_##NAME##_expected[0]) \
+ || (d_result[1] != d_##NAME##_expected[1])) \
+ { \
+ if (DEBUG) \
+ { \
+ printf("ERROR: vec_%s (double) expected value does not match\n", \
+ #NAME); \
+ printf(" expected[0] = 0x%lx; result[0] = 0x%lx\n", \
+ d_##NAME##_expected[0], d_result[0]); \
+ printf(" expected[1] = 0x%lx; result[1] = 0x%lx\n", \
+ d_##NAME##_expected[1], d_result[1]); \
+ } \
+ else \
+ abort(); \
+ }
+
+int
+main () {
+ int i;
+ vector float f_src_a = { 126.0, 23.0, -338.0, 17.0};
+ vector float f_src_b = { 2.00, 23.0, 1.0, 4.0};
+ vector bool f_result;
+ vector bool int f_cmpeq_expected = {0x0, 0xFFFFFFFF, 0x0, 0x0};
+ vector bool int f_cmpgt_expected = {0xFFFFFFFF, 0x0, 0x0, 0xFFFFFFFF};
+ vector bool int f_cmpge_expected = {0xFFFFFFFF, 0xFFFFFFFF, 0x0, 0xFFFFFFFF};
+ vector bool int f_cmplt_expected = {0x0, 0x0, 0xFFFFFFFF, 0x0};
+ vector bool int f_cmple_expected = {0x0, 0xFFFFFFFF, 0xFFFFFFFF, 0x0};
+
+ vector double d_src_a = { 125.44, -338.56};
+ vector double d_src_b = { 4.0, -338.56};
+ vector bool long long d_result;
+ vector bool long long d_cmpeq_expected = {0x0, 0xFFFFFFFFFFFFFFFF};
+ vector bool long long d_cmpgt_expected = {0xFFFFFFFFFFFFFFFF, 0x0};
+ vector bool long long d_cmpge_expected = {0xFFFFFFFFFFFFFFFF,
+ 0xFFFFFFFFFFFFFFFF};
+ vector bool long long d_cmplt_expected = {0x0, 0x0};
+ vector bool long long d_cmple_expected = {0x0, 0xFFFFFFFFFFFFFFFF};
+
+ FLOAT_CHECK (cmpeq)
+ FLOAT_CHECK (cmpgt)
+ FLOAT_CHECK (cmpge)
+ FLOAT_CHECK (cmplt)
+ FLOAT_CHECK (cmple)
+
+ DOUBLE_CHECK (cmpeq)
+ DOUBLE_CHECK (cmpgt)
+ DOUBLE_CHECK (cmpge)
+ DOUBLE_CHECK (cmplt)
+ DOUBLE_CHECK (cmple)
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp.h
new file mode 100644
index 00000000000..a987847fb9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp.h
@@ -0,0 +1,40 @@
+/* The goal is to have both compile tests which verify the desired instruction
+ generation and to functionally test the builtins for correctness. This is
+ done in separate test files, vsx-vector-6-func-cmp-compile.c and
+ vsx-vector-6-func-cmp-run.c. The vsx-vector-6-func-cmp-compile.c test file
+ only generates the calls so the instruction counts do not include the counts
+ of the instructions generated as part of the result testing. The result
+ checking code differs for BE/LE. */
+
+#include <altivec.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+void abort (void);
+
+#define FLOAT_TEST(NAME) \
+ vector bool int __attribute__ ((noipa)) \
+ float_##NAME (vector float f_src_a, vector float f_src_b) \
+ { \
+ return vec_##NAME (f_src_a, f_src_b); \
+ }
+
+FLOAT_TEST (cmpeq)
+FLOAT_TEST (cmpgt)
+FLOAT_TEST (cmpge)
+FLOAT_TEST (cmplt)
+FLOAT_TEST (cmple)
+
+#define DOUBLE_TEST(NAME) \
+ vector bool long long __attribute__ ((noipa)) \
+ double_##NAME (vector double d_src_a, vector double d_src_b) \
+ { \
+ return vec_##NAME (d_src_a, d_src_b); \
+ }
+
+DOUBLE_TEST (cmpeq)
+DOUBLE_TEST (cmpgt)
+DOUBLE_TEST (cmpge)
+DOUBLE_TEST (cmplt)
+DOUBLE_TEST (cmple)
+
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h
deleted file mode 100644
index 0106e8d2901..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/* This test code is included into vsx-vector-6.p7.c, vsx-vector-6.p8.c
- and vsx-vector-6.p9.c. The .c files have the tests for the number
- of instructions generated for each cpu type. */
-
-#include <altivec.h>
-
-typedef struct {
- vector double d;
- vector float f;
- vector long sl;
- vector int si;
- vector short ss;
- vector char sc;
- vector unsigned int ui;
- vector unsigned short int us;
- vector unsigned char uc;
- vector bool long long bll;
- vector bool long bl;
- vector bool int bi;
- vector bool short bs;
- vector bool char bc;
-} opnd_t;
-
-void
-func_1op (opnd_t *dst, opnd_t *src)
-{
- dst[0].d = vec_abs (src[0].d);
- dst[1].d = vec_ceil (src[1].d);
- dst[2].d = vec_floor (src[2].d);
- dst[3].d = vec_nearbyint (src[3].d);
- dst[4].d = vec_rint (src[4].d);
- dst[5].d = vec_sqrt (src[5].d);
- dst[6].d = vec_trunc (src[6].d);
- dst[7].f = vec_trunc (src[7].f);
-}
-
-void
-func_2op (opnd_t *dst, opnd_t *src0, opnd_t *src1)
-{
- dst[0].d = vec_add (src0[0].d, src1[0].d);
- dst[1].d = vec_div (src0[1].d, src1[1].d);
- dst[2].d = vec_max (src0[2].d, src1[2].d);
- dst[3].uc = vec_max (src0[3].uc, src1[3].uc);
- dst[4].d = vec_min (src0[4].d, src1[4].d);
- dst[5].d = vec_mul (src0[5].d, src1[5].d);
- dst[6].d = vec_sub (src0[6].d, src1[6].d);
-}
-
-void
-func_2lop (opnd_t *dst, opnd_t *src0, opnd_t *src1)
-{
- dst[0].d = vec_and (src0[0].d, src1[0].d);
- dst[1].d = vec_and (src0[1].d, src1[1].bl);
- dst[2].d = vec_and (src0[2].bl, src1[2].d);
-
- dst[3].d = vec_andc (src0[3].d, src1[3].d);
- dst[4].d = vec_andc (src0[4].d, src1[4].bl);
- dst[5].d = vec_andc (src0[5].bl, src1[5].d);
- dst[6].d = vec_andc (src0[6].bll, src1[6].d);
- dst[7].d = vec_andc (src0[7].d, src1[7].bll);
- dst[8].bi = vec_andc (src0[8].bi, src1[8].bi);
- dst[9].bs = vec_andc (src0[9].bs, src1[9].bs);
- dst[10].bc = vec_andc (src0[10].bc, src1[10].bc);
- dst[11].f = vec_andc (src0[11].f, src1[11].f);
- dst[12].f = vec_andc (src0[12].bi, src1[12].f);
- dst[13].f = vec_andc (src0[13].f, src1[13].bi);
- dst[14].d = vec_andc (src0[14].bll, src1[14].d);
- dst[15].d = vec_andc (src0[15].d, src1[15].bll);
-
- dst[16].d = vec_nor (src0[16].d, src1[16].d);
- dst[17].f = vec_nor (src0[17].f, src1[17].f);
- dst[18].bi = vec_nor (src0[18].bi, src1[18].bi);
- dst[19].bs = vec_nor (src0[19].bs, src1[19].bs);
- dst[20].bc = vec_nor (src0[20].bc, src1[20].bc);
-
- dst[21].d = vec_or (src0[21].d, src1[21].d);
- dst[22].d = vec_or (src0[22].d, src1[22].bl);
- dst[23].d = vec_or (src0[23].bl, src1[23].d);
- dst[24].d = vec_or (src0[24].bll, src1[24].d);
- dst[25].d = vec_or (src0[25].d, src1[25].bll);
- dst[26].f = vec_or (src0[26].f, src1[26].f);
- dst[27].bi = vec_or (src0[27].bi, src1[27].bi);
- dst[28].bs = vec_or (src0[28].bs, src1[28].bs);
- dst[29].bc = vec_or (src0[29].bc, src1[29].bc);
-
- dst[30].d = vec_xor (src0[30].d, src1[30].d);
- dst[31].d = vec_xor (src0[31].d, src1[31].bl);
- dst[32].d = vec_xor (src0[32].bl, src1[32].d);
-}
-
-void
-func_cmp (opnd_t *dst, opnd_t *src0, opnd_t *src1)
-{
- dst[0].bl = vec_cmpeq (src0[0].d, src1[0].d);
- dst[1].bl = vec_cmpgt (src0[1].d, src1[1].d);
- dst[2].bl = vec_cmpge (src0[2].d, src1[2].d);
- dst[3].bl = vec_cmplt (src0[3].d, src1[3].d);
- dst[4].bl = vec_cmple (src0[4].d, src1[4].d);
-}
-
-void
-func_all_cmp (int *dst, opnd_t *src0, opnd_t *src1)
-{
- dst[0] = vec_all_eq (src0[0].d, src1[0].d);
- dst[1] = vec_all_ge (src0[1].d, src1[1].d);
- dst[2] = vec_all_gt (src0[2].d, src1[2].d);
- dst[3] = vec_all_le (src0[3].d, src1[3].d);
- dst[4] = vec_all_lt (src0[4].d, src1[4].d);
- dst[5] = vec_all_nan (src0[5].d);
- dst[6] = vec_all_ne (src0[6].d, src1[6].d);
- dst[7] = vec_all_nge (src0[7].d, src1[7].d);
- dst[8] = vec_all_ngt (src0[8].d, src1[8].d);
- dst[9] = vec_all_nle (src0[9].d, src1[9].d);
- dst[10] = vec_all_nlt (src0[10].d, src1[10].d);
- dst[11] = vec_all_numeric (src0[11].d);
- dst[12] = vec_any_eq (src0[12].d, src1[12].d);
- dst[13] = vec_any_ge (src0[13].d, src1[13].d);
- dst[14] = vec_any_gt (src0[14].d, src1[14].d);
- dst[15] = vec_any_le (src0[15].d, src1[15].d);
- dst[16] = vec_any_lt (src0[16].d, src1[16].d);
- dst[17] = vec_any_nan (src0[17].d);
- dst[18] = vec_any_ne (src0[18].d, src1[18].d);
- dst[19] = vec_any_nge (src0[19].d, src1[19].d);
- dst[20] = vec_any_ngt (src0[20].d, src1[20].d);
- dst[21] = vec_any_nle (src0[21].d, src1[21].d);
- dst[22] = vec_any_nlt (src0[22].d, src1[22].d);
- dst[23] = vec_any_numeric (src0[23].d);
-}
-
-void
-func_3op (opnd_t *dst, opnd_t *src0, opnd_t *src1, opnd_t *src2)
-{
- dst[0].d = vec_madd (src0[0].d, src1[0].d, src2[0].d);
- dst[1].d = vec_msub (src0[1].d, src1[1].d, src2[1].d);
- dst[2].d = vec_nmadd (src0[2].d, src1[2].d, src2[2].d);
- dst[3].d = vec_nmsub (src0[3].d, src1[3].d, src2[3].d);
-
- dst[4].f = vec_madd (src0[4].f, src1[4].f, src2[4].f);
- dst[5].f = vec_msub (src0[5].f, src1[5].f, src2[5].f);
- dst[6].f = vec_nmsub (src0[6].f, src1[6].f, src2[6].f);
- dst[7].f = vec_nmadd (src0[7].f, src1[7].f, src2[7].f);
-
-#if defined (__BIG_ENDIAN__) || defined (_ARCH_PWR9)
- dst[8].d = vec_perm (src0[8].d, src1[8].d, src2[8].uc);
-#else
- dst[8].d = vec_perm (src0[8].d, src1[8].d, ~src2[8].uc);
-#endif
-
- dst[9].d = vec_sel (src0[9].d, src1[9].d, src2[9].d);
- dst[10].d = vec_sel (src0[10].d, src1[10].d, src2[10].bl);
-
- dst[11].si = vec_msums(src0[11].ss, src1[11].ss, src2[11].si);
- dst[12].ui = vec_msums(src0[12].us, src1[12].us, src2[12].ui);
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
deleted file mode 100644
index ff560dd8d4f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power7" } */
-
-/* Source code for the test in vsx-vector-6.h */
-#include "vsx-vector-6.h"
-
-/* { dg-final { scan-assembler-times {\mvmaxub\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvmsumshs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvmsumuhs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvadddp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpeqdp\M} 9 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpgedp\M} 10 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpgtdp\M} 10 } } */
-/* { dg-final { scan-assembler-times {\mxvdivdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmadd[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmadd[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmaxdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmindp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmsub[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmsub[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmuldp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmadd[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmadd[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmsub[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmsub[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvsubdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M} 13 } } */
-/* { dg-final { scan-assembler-times {\mxxlnor\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxlor\M} 9 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxsel\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
deleted file mode 100644
index 49f5bf52af5..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
-
-/* Source code for the test in vsx-vector-6.h */
-#include "vsx-vector-6.h"
-
-/* { dg-final { scan-assembler-times {\mvmaxub\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvmsumshs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvmsumuhs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvadddp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpeqdp\M} 9 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpgedp\M} 10 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpgtdp\M} 10 } } */
-/* { dg-final { scan-assembler-times {\mxvdivdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmadd[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmadd[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmaxdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmindp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmsub[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmsub[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmuldp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmadd[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmadd[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmsub[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmsub[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvsubdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M} 13 } } */
-/* { dg-final { scan-assembler-times {\mxxlnor\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxlor\M} 9 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxsel\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
deleted file mode 100644
index 3fdd9f62a4c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
-
-/* Source code for the test in vsx-vector-6.h */
-#include "vsx-vector-6.h"
-
-/* { dg-final { scan-assembler-times {\mvmaxub\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvmsumshs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvmsumuhs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\m(?:v|xx)permr?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvadddp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpeqdp\M} 9 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpgedp\M} 10 } } */
-/* { dg-final { scan-assembler-times {\mxvcmpgtdp\M} 10 } } */
-/* { dg-final { scan-assembler-times {\mxvdivdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmadd[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmadd[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmaxdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmindp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmsub[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmuldp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmadd[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmadd[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmsub[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvnmsub[am]sp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmsub[am]dp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M} 13 } } */
-/* { dg-final { scan-assembler-times {\mxxlnor\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxlor\M} 9 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxsel\M} 2 } } */
--
2.37.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4] rs6000: Update the vsx-vector-6.* tests.
2023-07-06 15:33 [PATCH v4] rs6000: Update the vsx-vector-6.* tests Carl Love
@ 2023-07-07 2:15 ` Kewen.Lin
2023-07-07 20:36 ` Carl Love
0 siblings, 1 reply; 3+ messages in thread
From: Kewen.Lin @ 2023-07-07 2:15 UTC (permalink / raw)
To: Carl Love; +Cc: Peter Bergner, Segher Boessenkool, David Edelsohn, gcc-patches
Hi Carl,
on 2023/7/6 23:33, Carl Love wrote:
> GCC maintainers:
>
> Ver 4. Fixed a few typos. Redid the tests to create separate run and
> compile tests.
Thanks! This new version looks good, excepting that we need vsx_hw
for run and two nits, see below.
>
> Ver 3. Added __attribute__ ((noipa)) to the test files. Changed some
> of the scan-assembler-times checks to cover multiple similar
> instructions. Change the function check macro to a macro to generate a
> function to do the test and check the results. Retested on the various
> processor types and BE/LE versions.
>
> Ver 2. Switched to using code macros to generate the call to the
> builtin and test the results. Added in instruction counts for the key
> instruction for the builtin. Moved the tests into an additional
> function call to ensure the compile doesn't replace the builtin call
> code with the statically computed results. The compiler was doing this
> for a few of the simpler tests.
>
> The following patch takes the tests in vsx-vector-6-p7.h, vsx-vector-
> 6-p8.h, vsx-vector-6-p9.h and reorganizes them into a series of smaller
> test files by functionality rather than processor version.
>
> Tested the patch on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE with
> no regresions.
>
> Please let me know if this patch is acceptable for mainline. Thanks.
>
> Carl
>
>
>
> -----------------------------------------------------------------
> rs6000: Update the vsx-vector-6.* tests.
>
> The vsx-vector-6.h file is included into the processor specific test files
> vsx-vector-6.p7.c, vsx-vector-6.p8.c, and vsx-vector-6.p9.c. The .h file
> contains a large number of vsx vector builtin tests. The processor
> specific files contain the number of instructions that the tests are
> expected to generate for that processor. The tests are compile only.
>
> This patch reworks the tests into a series of files for related tests.
> The new tests consist of a runnable test to verify the builtin argument
> types and the functional correctness of each builtin. There is also a
> compile only test that verifies the builtins generate the expected number
> of instructions for the various builtin tests.
>
> gcc/testsuite/
> * gcc.target/powerpc/vsx-vector-6-func-1op.h: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-1op-run.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-1op-compile.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-2lop.h: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-2lop-run.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-2lop-compile.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-2op.h: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-2op-run.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-2op-compile.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-3op.h: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-3op-run.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-3op-compile.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-cmp-all.h: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-cmp-all-run.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-cmp-all-compile.c: New test
> file.
> * gcc.target/powerpc/vsx-vector-6-func-cmp.h: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-cmp-run.c: New test file.
> * gcc.target/powerpc/vsx-vector-6-func-cmp-compile.c: New test file.
> * gcc.target/powerpc/vsx-vector-6.h: Remove test file.
> * gcc.target/powerpc/vsx-vector-6.p7.c: Remove test file.
> * gcc.target/powerpc/vsx-vector-6.p8.c: Remove test file.
> * gcc.target/powerpc/vsx-vector-6.p9.c: Remove test file.
> ---
> .../powerpc/vsx-vector-6-func-1op-compile.c | 22 ++
> .../powerpc/vsx-vector-6-func-1op-run.c | 98 ++++++++
> .../powerpc/vsx-vector-6-func-1op.h | 43 ++++
> .../powerpc/vsx-vector-6-func-2lop-compile.c | 14 ++
> .../powerpc/vsx-vector-6-func-2lop-run.c | 177 ++++++++++++++
> .../powerpc/vsx-vector-6-func-2lop.h | 47 ++++
> .../powerpc/vsx-vector-6-func-2op-compile.c | 21 ++
> .../powerpc/vsx-vector-6-func-2op-run.c | 96 ++++++++
> .../powerpc/vsx-vector-6-func-2op.h | 42 ++++
> .../powerpc/vsx-vector-6-func-3op-compile.c | 17 ++
> .../powerpc/vsx-vector-6-func-3op-run.c | 229 ++++++++++++++++++
> .../powerpc/vsx-vector-6-func-3op.h | 73 ++++++
> .../vsx-vector-6-func-cmp-all-compile.c | 17 ++
> .../powerpc/vsx-vector-6-func-cmp-all-run.c | 147 +++++++++++
> .../powerpc/vsx-vector-6-func-cmp-all.h | 76 ++++++
> .../powerpc/vsx-vector-6-func-cmp-compile.c | 16 ++
> .../powerpc/vsx-vector-6-func-cmp-run.c | 92 +++++++
> .../powerpc/vsx-vector-6-func-cmp.h | 40 +++
> .../gcc.target/powerpc/vsx-vector-6.h | 154 ------------
> .../gcc.target/powerpc/vsx-vector-6.p7.c | 43 ----
> .../gcc.target/powerpc/vsx-vector-6.p8.c | 43 ----
> .../gcc.target/powerpc/vsx-vector-6.p9.c | 42 ----
> 22 files changed, 1267 insertions(+), 282 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-compile.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op.h
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-compile.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop-run.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2lop.h
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-compile.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op-run.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-2op.h
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-compile.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op-run.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-3op.h
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-compile.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all-run.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-all.h
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-compile.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp-run.c
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-cmp.h
> delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h
> delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
> delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
> delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-compile.c
> new file mode 100644
> index 00000000000..6b7d73ed66c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-compile.c
Nit: Maybe remove "-compile" from the name as when there is "-run" variant people
are easy to realize this is for compilation, the name without "-compile" seems
more neat. With this name change, you have to update the comment referring it in
its related header file accordingly. ("sed -i 's/-compile//g' vsx-vector-6-func-*.h"
recommended, similar patterns could be used for the two other comments below.)
> @@ -0,0 +1,22 @@
> +/* { dg-do compile { target lp64 } } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -save-temps -mvsx" } */
Nit: We don't need "-save-temps" any more for all the test cases in this patch.
> +
> +/* This file just generates calls to the various builtins and verifies the
> + expected number of instructions for each builtin were generated. */
> +
> +#include "vsx-vector-6-func-1op.h"
> +
> +/* { dg-final { scan-assembler-times {\mxvabssp\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrspip\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrspim\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrspi\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrspic\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */
> +/* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c
> new file mode 100644
> index 00000000000..150e372e428
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c
> @@ -0,0 +1,98 @@
> +/* { dg-do run { target lp64 } } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
We need vsx_hw for those *-run.c cases instead, as powerpc_vsx_ok
doesn't guarantee the test env can support vsx instructions, it just
ensures it can be compiled.
/* { dg-require-effective-target vsx_hw } */
All "*-run.c" cases need changes.
BR,
Kewen
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4] rs6000: Update the vsx-vector-6.* tests.
2023-07-07 2:15 ` Kewen.Lin
@ 2023-07-07 20:36 ` Carl Love
0 siblings, 0 replies; 3+ messages in thread
From: Carl Love @ 2023-07-07 20:36 UTC (permalink / raw)
To: Kewen.Lin; +Cc: Peter Bergner, Segher Boessenkool, David Edelsohn, gcc-patches
On Fri, 2023-07-07 at 10:15 +0800, Kewen.Lin wrote:
<snip>
>
> > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-
> > 1op-compile.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-
> > 1op-compile.c
> > new file mode 100644
> > index 00000000000..6b7d73ed66c
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-
> > compile.c
>
> Nit: Maybe remove "-compile" from the name as when there is "-run"
> variant people
> are easy to realize this is for compilation, the name without "-
> compile" seems
> more neat. With this name change, you have to update the comment
> referring it in
> its related header file accordingly. ("sed -i 's/-compile//g' vsx-
> vector-6-func-*.h"
> recommended, similar patterns could be used for the two other
> comments below.)
Changed the compile only file names as requested. Updated the file
names in the .h files. Updated the Change Log file names.
>
> > @@ -0,0 +1,22 @@
> > +/* { dg-do compile { target lp64 } } */
> > +/* { dg-require-effective-target powerpc_vsx_ok } */
> > +/* { dg-options "-O2 -save-temps -mvsx" } */
>
> Nit: We don't need "-save-temps" any more for all the test cases in
> this patch.
>
Yup, -save-temps is on automatically for compile only and we are not
checking instructions in the run file. Removed all of the -save-temp
directives.
> > +
> > +/* This file just generates calls to the various builtins and
> > verifies the
> > + expected number of instructions for each builtin were
> > generated. */
> > +
> > +#include "vsx-vector-6-func-1op.h"
> > +
> > +/* { dg-final { scan-assembler-times {\mxvabssp\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrspip\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrspim\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrspi\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrspic\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrspiz\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrdpip\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrdpim\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrdpic\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvrdpiz\M} 1 } } */
> > +/* { dg-final { scan-assembler-times {\mxvsqrtdp\M} 1 } } */
> > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-
> > 1op-run.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-
> > run.c
> > new file mode 100644
> > index 00000000000..150e372e428
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-func-1op-run.c
> > @@ -0,0 +1,98 @@
> > +/* { dg-do run { target lp64 } } */
> > +/* { dg-require-effective-target powerpc_vsx_ok } */
>
> We need vsx_hw for those *-run.c cases instead, as powerpc_vsx_ok
> doesn't guarantee the test env can support vsx instructions, it just
> ensures it can be compiled.
>
> /* { dg-require-effective-target vsx_hw } */
>
> All "*-run.c" cases need changes.
Updated the run cases to use vsx_hw, removed powerpc_vsx_ok.
Carl
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-07-07 20:36 UTC | newest]
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2023-07-06 15:33 [PATCH v4] rs6000: Update the vsx-vector-6.* tests Carl Love
2023-07-07 2:15 ` Kewen.Lin
2023-07-07 20:36 ` Carl Love
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