* [PATCH 1/2] RISC-V: delete all the vector psabi checking.
@ 2024-01-15 6:00 yanzhang.wang
2024-01-15 6:00 ` [PATCH 2/2] RISC-V: delete vector abi checking in all relevant tests yanzhang.wang
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: yanzhang.wang @ 2024-01-15 6:00 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, lehua.ding, yanzhang.wang
From: Yanzhang Wang <yanzhang.wang@intel.com>
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete.
(riscv_init_cumulative_args): Delete the checking.
(riscv_get_arg_info): Delete the checking.
(riscv_function_value): Delete the checking.
* config/riscv/riscv.h: Delete the member for checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the -Wno-psabi.
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
---
Have tested the two patches on my local and there's no regression.
---
gcc/config/riscv/riscv.cc | 80 +------------------
gcc/config/riscv/riscv.h | 2 -
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vector-abi-1.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-2.c | 15 ----
.../gcc.target/riscv/rvv/base/vector-abi-3.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-4.c | 16 ----
.../gcc.target/riscv/rvv/base/vector-abi-5.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-6.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-7.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-8.c | 14 ----
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../base/zero_base_load_store_optimization.c | 2 +-
.../riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +-
24 files changed, 15 insertions(+), 222 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e7f7ce605db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4844,59 +4844,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}
-/* Return true if a vector type is included in the type TYPE. */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
- if (riscv_v_ext_mode_p (TYPE_MODE (type)))
- return true;
-
- if (!COMPLETE_TYPE_P (type))
- return false;
-
- switch (TREE_CODE (type))
- {
- case RECORD_TYPE:
- /* If it is a record, it is further determined whether its fields have
- vector type. */
- for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
- if (TREE_CODE (f) == FIELD_DECL)
- {
- tree field_type = TREE_TYPE (f);
- if (!TYPE_P (field_type))
- break;
-
- if (riscv_arg_has_vector (field_type))
- return true;
- }
- break;
- case ARRAY_TYPE:
- return riscv_arg_has_vector (TREE_TYPE (type));
- default:
- break;
- }
-
- return false;
-}
-
-/* Pass the type to check whether it's a vector type or contains vector type.
- Only check the value type and no checking for vector pointer type. */
-
-static void
-riscv_pass_in_vector_p (const_tree type)
-{
- static int warned = 0;
-
- if (type && riscv_vector::lookup_vector_type_attribute (type) && !warned)
- {
- warning (OPT_Wpsabi,
- "ABI for the vector type is currently in experimental stage and "
- "may changes in the upcoming version of GCC.");
- warned = 1;
- }
-}
-
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0. */
@@ -4914,15 +4861,6 @@ riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
cum->variant_cc = (riscv_cc) fntype_abi (fntype).id ();
else
cum->variant_cc = RISCV_CC_BASE;
-
- if (fndecl)
- {
- const tree_function_decl &fn
- = FUNCTION_DECL_CHECK (fndecl)->function_decl;
-
- if (fn.built_in_class == NOT_BUILT_IN)
- cum->rvv_psabi_warning = 1;
- }
}
/* Return true if TYPE is a vector type that can be passed in vector registers.
@@ -5039,12 +4977,6 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
- if (cum->rvv_psabi_warning)
- {
- /* Only check existing of vector type. */
- riscv_pass_in_vector_p (type);
- }
-
/* When disable vector_abi or scalable vector argument is anonymous, this
argument is passed by reference. */
if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named))
@@ -5222,17 +5154,7 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
memset (&args, 0, sizeof args);
- const_tree arg_type = type;
- if (func && DECL_RESULT (func))
- {
- const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
- if (fn.built_in_class == NOT_BUILT_IN)
- args.rvv_psabi_warning = 1;
-
- arg_type = TREE_TYPE (DECL_RESULT (func));
- }
-
- return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
+ return riscv_get_arg_info (&info, &args, mode, type, true, true);
}
/* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index b13ccc5aba9..d97bed5c029 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -733,8 +733,6 @@ typedef struct {
/* Number of floating-point registers used so far, likewise. */
unsigned int num_fprs;
- int rvv_psabi_warning;
-
/* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */
unsigned int num_mrs;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index cc373465957..809b185dd65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include "riscv_vector.h"
vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 2942e0b2e53..1bca8467a16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index a6df1215c60..57d0241675a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 276173d02db..9563c8d27fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index c1df69ace57..e8b5bf8c714 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 9c310bbf590..80ee1b5f0c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index 89c96c8ef5e..d37857e24ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index 484a2510885..d9362ecd41b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index 5464a297670..ec673575b4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
deleted file mode 100644
index 114ee6de483..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
deleted file mode 100644
index 0b24ccb8312..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
-
-#include "riscv_vector.h"
-
-vint32m1_t
-fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
deleted file mode 100644
index 844a5db4027..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1_t*
-fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
deleted file mode 100644
index a5dc2dffaac..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-typedef int v4si __attribute__ ((vector_size (16)));
-
-v4si
-fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- v4si a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
deleted file mode 100644
index 9dc69518b5d..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; int b; };
-
-void foo (int b);
-
-void
-fun (struct A a) {
-
- foo (a.b);
-} /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- struct A a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
deleted file mode 100644
index 3a65f2c60ab..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-#include "riscv_vector.h"
-
-void
-foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
- size_t n, int cond) {
- size_t vl;
- if (cond)
- vl = __riscv_vsetvlmax_e32m1();
- else
- vl = __riscv_vsetvlmax_e16mf2();
- for (size_t i = 0; i < n; i += 1)
- {
- vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
- vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
- vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
- __riscv_vse32_v_i32m1(out, c, vl);
- }
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
deleted file mode 100644
index 2795fd4f9fb..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
deleted file mode 100644
index 9cf68d4da9c..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1x3_t*
-fun (vint32m1x3_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 51f4fac0a8b..501d98c5897 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index b27e5ccad09..fbcfb7b8501 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index 0e7c7cdbdd5..c951644de4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 9ae79663adf..1d82cc8de2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index c3519cedba7..be31df1d84b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
--
2.42.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] RISC-V: delete vector abi checking in all relevant tests.
2024-01-15 6:00 [PATCH 1/2] RISC-V: delete all the vector psabi checking yanzhang.wang
@ 2024-01-15 6:00 ` yanzhang.wang
2024-01-15 6:19 ` [PATCH 1/2] RISC-V: delete all the vector psabi checking juzhe.zhong
2024-01-15 9:55 ` juzhe.zhong
2 siblings, 0 replies; 7+ messages in thread
From: yanzhang.wang @ 2024-01-15 6:00 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, lehua.ding, yanzhang.wang
From: Yanzhang Wang <yanzhang.wang@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-call-args-1-run.c: Delete the
-Wno-psabi.
* gcc.target/riscv/rvv/base/abi-call-args-1.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-args-2-run.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-args-2.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-args-3-run.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-args-3.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-args-4-run.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-args-4.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-error-1.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-return-run.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-return.c: Ditto.
* gcc.target/riscv/rvv/base/abi-call-variant_cc.c: Ditto.
* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Ditto.
* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Ditto.
* gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c: Ditto.
* gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: Ditto.
* gcc.target/riscv/rvv/base/abi-callee-saved-1.c: Ditto.
* gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c: Ditto.
* gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: Ditto.
* gcc.target/riscv/rvv/base/abi-callee-saved-2.c: Ditto.
* gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c: Ditto.
* gcc.target/riscv/rvv/base/fixed-point-vxrm.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-cvt-f.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-cvt-x.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-cvt-xu.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-1.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-10.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-11.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-14.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-15.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-16.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-17.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-18.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-19.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-2.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-20.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-21.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-22.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-23.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-24.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-25.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-26.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-27.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-28.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-29.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-3.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-31.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-32.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-4.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-5.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-6.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-63.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-7.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-72.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-73.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-76.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-8.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-9.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-error.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-1.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-2.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-3.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-4.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-5.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-8.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-insert-9.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-run-2.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-run-3.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-run-4.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm-run-5.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-frm.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-fwmacc.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-macc.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-madd.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-msac.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-msub.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-ncvt-f.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-ncvt-x.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-ncvt-xu.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-nmacc.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-nmadd.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-nmsac.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-nmsub.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-rec7.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-redosum.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-redusum.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-single-div.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-single-mul.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-single-rdiv.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-single-rsub.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-sqrt.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-wcvt-x.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-wcvt-xu.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-widening-add.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-widening-mul.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-widening-sub.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-wmsac.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-wnmacc.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-wnmsac.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-wredosum.c: Ditto.
* gcc.target/riscv/rvv/base/float-point-wredusum.c: Ditto.
* gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c: Ditto.
* gcc.target/riscv/rvv/base/no-honor-frm-1.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c: Ditto.
* gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c: Ditto.
* gcc.target/riscv/rvv/base/pr110119-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
* gcc.target/riscv/rvv/base/pr110265-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr110265-2.c: Ditto.
* gcc.target/riscv/rvv/base/pr110265-3.c: Ditto.
* gcc.target/riscv/rvv/base/pr110277-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr110277-2.c: Ditto.
* gcc.target/riscv/rvv/base/pr110299-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr110299-2.c: Ditto.
* gcc.target/riscv/rvv/base/pr110299-3.c: Ditto.
* gcc.target/riscv/rvv/base/pr110299-4.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-0.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-10.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-2.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-3.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-4.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-5.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-6.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-7.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-8.c: Ditto.
* gcc.target/riscv/rvv/base/pr111720-9.c: Ditto.
* gcc.target/riscv/rvv/base/pr111935.c: Ditto.
* gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c: Ditto.
* gcc.target/riscv/rvv/base/simplify-vdiv.c: Ditto.
* gcc.target/riscv/rvv/base/simplify-vrsub.c: Ditto.
* gcc.target/riscv/rvv/base/tuple-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/tuple_vundefined.c: Ditto.
* gcc.target/riscv/rvv/base/vcreate.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-2.c: Ditto.
* gcc.target/riscv/rvv/base/vslide1down-1.c: Ditto.
* gcc.target/riscv/rvv/base/vslide1down-2.c: Ditto.
* gcc.target/riscv/rvv/base/vslide1down-3.c: Ditto.
* gcc.target/riscv/rvv/base/vslide1up-1.c: Ditto.
* gcc.target/riscv/rvv/base/vslide1up-2.c: Ditto.
* gcc.target/riscv/rvv/base/vslide1up-3.c: Ditto.
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: Ditto.
* gcc.target/riscv/rvv/base/zvbc-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c: Ditto.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: Ditto.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvkg-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvkned-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvknha-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvknhb-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvksed-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvksh-intrinsic.c: Ditto.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c | 2 +-
.../gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c | 2 +-
.../gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c | 2 +-
.../gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c | 2 +-
.../gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c | 2 +-
.../gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c | 2 +-
.../gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c | 2 +-
.../gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-1.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-10.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-11.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-14.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-15.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-16.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-17.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-18.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-19.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-2.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-20.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-21.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-22.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-23.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-24.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-25.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-26.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-27.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-28.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-29.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-3.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-31.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-32.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-4.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-5.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-6.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-63.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-7.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-72.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-73.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-76.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-8.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-9.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-1.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-10.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-2.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-3.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-4.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-5.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-7.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-8.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-frm-insert-9.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-single-div.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-single-mul.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-single-rdiv.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-single-rsub.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-single-sub.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-widening-add.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-widening-mul.c | 2 +-
.../gcc.target/riscv/rvv/base/float-point-widening-sub.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c | 2 +-
.../gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c | 2 +-
.../gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c | 2 +-
.../gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c | 2 +-
.../gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c | 2 +-
.../gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c | 2 +-
.../gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c | 2 +-
.../gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c | 2 +-
.../gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c | 2 +-
215 files changed, 215 insertions(+), 215 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
index 6355ecbf1aa..85f004422eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-additional-sources abi-call-args-1.c } */
#include <stdbool.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
index 067e61303b1..c4858a38a16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
index fe036efaa2b..06d77035183 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-additional-sources abi-call-args-2.c } */
#include <stdlib.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
index 3aed245454f..269fbeb104c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */
#include <stdarg.h>
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
index 8c5a09441ea..9056d7539e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-additional-sources abi-call-args-3.c } */
#include <stdbool.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
index 17d8dace95e..8c774716fc9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
index aa28bb7e477..21618b573cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-additional-sources abi-call-args-4.c } */
#include <stdbool.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c
index 9693b0c325f..2872ffc6d8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c
index 8070ca34781..664b5145997 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-vector-abi -Wno-psabi -Wno-implicit-function-declaration" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-vector-abi -Wno-implicit-function-declaration" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c
index 054b6fa3e21..b5b3c5d9c2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-O1 --param=riscv-vector-abi" } */
/* { dg-additional-sources abi-call-return.c } */
#include <stdbool.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c
index a6287e6e9bb..ac19cc6bd18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O1 --param=riscv-vector-abi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c
index 6459f8ef1fb..16c7687f03d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O1 --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O1 --param=riscv-vector-abi" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
index 1e6292e84ed..06b3647e9d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-vector-abi --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-vector-abi --param=riscv-autovec-preference=fixed-vlmax" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
index 9fdbcd8deb3..5a6ab81bbf9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-vector-abi --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-vector-abi --param=riscv-autovec-preference=fixed-vlmax" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c
index 007c27498b8..c6aa5e13593 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -Wno-psabi -msave-restore" } */
+/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -msave-restore" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c
index 5f697e7c372..386916a23ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d --param=riscv-vector-abi -Wno-psabi -fno-shrink-wrap-separate" } */
+/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d --param=riscv-vector-abi -fno-shrink-wrap-separate" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
index 42d099d39fd..bc1f9ff60bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c
index ce2f68e07d9..96a3e717636 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -Wno-psabi -msave-restore" } */
+/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -msave-restore" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c
index 08ca1a102a7..b3a8141a81c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d --param=riscv-vector-abi -Wno-psabi -fno-shrink-wrap-separate" } */
+/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d --param=riscv-vector-abi -fno-shrink-wrap-separate" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c
index 0ea3e247368..8b6537ba9de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -Wno-psabi" } */
+/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c b/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c
index 2b824458cf5..b66ecefd8a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm-error.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c b/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c
index 41e34cd3844..582aa03289c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/fixed-point-vxrm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
index 424a38ede13..48930cde7fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
index e090f0f97e9..fcbfb874c00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
index bb164b2b001..dc8aff8c568 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-1.c
index 75af8eed123..0c78cac36cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-10.c
index 71428d6394c..c578be54269 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-11.c
index 94f8ea171b8..f3b3068b48f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c
index 66c74958f2e..320332974ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c
index 0fb84987d89..1216793425a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-14.c
index ab5fc06493c..d84e4704f47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-15.c
index 97daccad7af..3a75398a4d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-15.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-16.c
index da710b17f7f..5caa29219b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-17.c
index 43f25179aba..b0a89352483 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-17.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-18.c
index e7258254529..6f02296797c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-18.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-19.c
index c0161a1ba36..09020d59330 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-19.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-2.c
index 9f8ac99f294..4b35e99a28e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-20.c
index 9e75b79722e..849ba16855b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-20.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-21.c
index aec56427371..052f8ea7e14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-21.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-22.c
index 83bc26a8d78..c6b0722c4a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-22.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-23.c
index e7c51ea874e..09f4bee4bf6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-23.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-24.c
index 46ac8e02215..14ac2fb2858 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-24.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-25.c
index b70f531a24c..ae2853da913 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-25.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-26.c
index 78b2946b9fb..d67e6d6d5bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-26.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-27.c
index 4dba68040e2..87507a2e47e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-27.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-28.c
index 35a37b83239..7fd63db802f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-28.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-29.c
index e24c2045f43..9e7b471edf6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-29.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-3.c
index 600ac45bb03..baa3461d45d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
index bf5772073f7..7e738783974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-31.c
index 64a0c8cd2b0..d7ff69bc6f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-31.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-32.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-32.c
index a24ffd799fd..179f8d0d4ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c
index 4bd520ea2af..ce929e83545 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c
index 6c7cf7ef69c..de0ba5d759e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c
index b7f5a6919f4..a69a6619896 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c
index 4485cea24d9..f81341fd465 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c
index a1fca1a2a3f..2457254ee60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c
index 8d59cae9a87..c402fad758b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
index 04c54877393..fe497c757db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-4.c
index aaf912e0923..c26dcfcd985 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c
index 49cf52f739b..7c75f12eb51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
index 79ef55b2c9f..4f86fcb938a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c
index 1123a93997e..4a09a11feb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c
index 2ea60ca47c0..f6c8a0018c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c
index 7486ed465c6..4e73ee9c592 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
index 3ceea105f6a..69ccd4fe04d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
index b990fb434f8..a11a1b45f50 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c
index 994c86e93eb..6212305bdf3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
index 4cde923abc1..2855d5f4562 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
index 0b0a017cfd5..af89f628657 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-5.c
index 9149388bea1..6aa3f5b0764 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
index 23f72664426..5b759355547 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c
index 8b564ca5f43..caf6792417a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
index b63f717b239..cd23141e72e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c
index 647de39d66e..949f1d344cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c
index f33f303c0cb..be569b9cc34 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c
index 61365103b40..efbc59b45f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
index e5a1c356a98..aa9c06f625c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c
index cc0fb556da3..d4b5ed0bae7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c
index c5c3408be30..d6568321dfc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
index 87d436ac146..8a752697cd8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-6.c
index 1541de88979..15ebb69ab97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
index ad3a7f81a69..96f009185cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
index 8748ca66b1b..5028b789192 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
index 8fd97b50124..44bf9ffd059 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-63.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-63.c
index 58718c39279..12ebef1a9e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-63.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-63.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
index ad2d54510bf..45c8b8408de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
index c15629d2134..329f98c5c1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
index ea99831f31f..b9240f24ec7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-66.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
index b8500303a21..2008cc60b46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-67.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
index 1dbf6dba208..cad2f1d5f9c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-68.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
index b08ab1ef605..5f07b893fb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-7.c
index 6f24317c51a..e5e53b7e45d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
index 5a2b8a16952..44f985b767e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
index 185a04cc2bd..694f3aa2d96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-72.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-72.c
index 6a07cfa6df9..6b1d31b868c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-72.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-72.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-73.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-73.c
index 91b015c51e8..0d3b3ef0de6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-73.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-73.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c
index b52400e5123..fb57803640c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c
index 4d3fd859637..09067d3dce7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-76.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-76.c
index 7ff106a8847..915483d0e6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-76.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-76.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c
index c3d12cfe04e..9920a241007 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zbb --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zbb --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-8.c
index a4846b05ab6..4a9eddc008c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-9.c
index cfb8fca08a7..58f7ad9eb32 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
index f4f17a306d5..ccdd6d4a663 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
index 77d0f5ef773..89e43cd19d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c
index abedfc1b8fb..cb0ea58a05f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
index 2cc4e0ae38e..c043761477e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c
index 01d82d4e661..bbd8592b5c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
index d6c5e1bddd6..9a7e917d7fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
index 3252f67d078..f38042a70c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
index 96e10c720b8..2ca5714132f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
index 519537c07cb..8e72a8ff2a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
index f9e6bc36a90..17e47eb0f41 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
index c3f6302384a..32c938db123 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
index 6de9d06b875..e74f9fa6795 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
index cc83dae4e95..9eb67367ef1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
index 3b650ec2948..db707fc6956 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 34b8c488467..efa55f5a921 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 -Wno-psabi" } */
+/* { dg-options "-O3" } */
#include "riscv_vector.h"
#include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c
index 4c43983e537..fa7630a5711 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 -Wno-psabi" } */
+/* { dg-options "-O3" } */
#include "riscv_vector.h"
#include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c
index ff43422ad78..4f21fe34d28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 -Wno-psabi" } */
+/* { dg-options "-O3" } */
#include "riscv_vector.h"
#include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c
index f2b1b1bc5cd..0194df995c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-4.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 -Wno-psabi" } */
+/* { dg-options "-O3" } */
#include "riscv_vector.h"
#include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c
index 4cb913ab2b2..510f9ab39cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-5.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 -Wno-psabi" } */
+/* { dg-options "-O3" } */
#include "riscv_vector.h"
#include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c
index 1f142605cc3..538d6128ce3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c
index 45bb628fa7b..b286a2e4e44 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c
index df29f4d240f..a0d89e188e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c
index 00c9d002998..c6df691bc4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
index 8fee552dd30..dde0d161a6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c
index e58519d0742..4b7feb06263 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
index d6d4be5e98e..c5a390a619d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c
index 1630b7e7ccf..47a907482c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
index 82c3e1364bf..51af172ad50 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
index fca378b7a8f..245a93d83f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c
index 9332617641b..f22767f55b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
index c3089234272..6e5113b87c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c
index 1b3e939b1e1..e8661494922 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c
index a8e10d0853a..643e18f7037 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
index 2e6a3c28a89..6eaf459bd96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c
index 36da6dd46f7..e2bb60e7904 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c
index cef6ab007b1..06430d535ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
index e6410ea3a37..ebefce1d3c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c
index 385cddf5070..a3181977427 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
index 86c56b7c6cb..147a6d1009e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
index 8075dced0b9..6f0bd5a9a24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c
index afd1fb2b8f6..553d017547b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
index 8f67ec00966..378f7d42ab6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
index 29449e79b69..6ba6ae1d68d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c
index 19ce1e1829d..b7d4c7508e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
index 893fa866a31..0c3f98372c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
index 4325cc510a7..1dc3c3a2846 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c
index 886a0b13695..d86f72fa5c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c
index 2602289ec88..d1d729573df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c
index 13eb306313c..c32e2a94d19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
index acf79569a22..83357698996 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c
index 6c888c10c0d..42add7e3d90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c
index 59c6d7c887d..6d965704493 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
index b2e0f217bfa..a8350c65c16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
void foo (void) {
for (unsigned i = 0; i < sizeof(foo); i++)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c
index 5f10aa9bf35..05e6e43b1e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3" } */
#include "overloaded_vadd.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c
index bea35a13a7b..dd183597a42 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3" } */
#include "overloaded_vfadd.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c
index 6b0ba142b90..1bd091b7a5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3" } */
#include "overloaded_vget_vset.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c
index a20e4a3bb4f..3bec715a955 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3" } */
#include "overloaded_vloxseg2ei16.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c
index 237b34dbe91..8a87b91312e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vmv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3" } */
#include "overloaded_vmv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c
index 42d50589246..d5d80c005a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv_zvfh -mabi=ilp32 -O3" } */
#include "overloaded_vreinterpret.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c
index c4555e3f477..390e2e525c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "overloaded_vadd.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c
index ca98136ce9b..bf540c68f17 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "overloaded_vfadd.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c
index 1cb4225084c..a6a05c1688b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "overloaded_vget_vset.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c
index ea73170444d..d0b8be018b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "overloaded_vloxseg2ei16.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c
index c5da6bbfca8..50db15aa05b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vmv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "overloaded_vmv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c
index 3b8399c126d..57ec538c78a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "overloaded_vreinterpret.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
index c5d9b1538cd..ca974daf2a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
index 3dadc9920e6..561b62c0188 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
#include <stdint-gcc.h>
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c
index 2e4aeb5b90b..a2531b82a1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32f -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32f -O3" } */
#include "pr110265-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c
index 7454c1cc918..6611d1abb8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -O3" } */
#include "pr110265-1.h"
#include "pr110265-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c
index 0ed1fbae35a..99593af239d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32f -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32f -O3" } */
#include "pr110265-1.h"
#include "pr110265-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c
index 24a4ba3b45f..fa0fa92a64b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvfh -mabi=ilp32f -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve32f_zvfh -mabi=ilp32f -O3" } */
#include "pr110277-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c
index 23d7361488a..0d564b87180 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
#include "pr110277-1.h"
#include "pr110277-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
index a903dde34d1..c987d271c56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvfh -mabi=ilp32f -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve32f_zvfh -mabi=ilp32f -O3" } */
#include "pr110299-1.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
index 1254ace58eb..b675e86a40d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
#include "pr110299-1.h"
#include "pr110299-2.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c
index 0f84c17d6f1..5d4833b1223 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32f -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32f -O3" } */
#include "pr110299-3.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c
index 8297cd62f65..1754704511a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -O3" } */
#include "pr110299-3.h"
#include "pr110299-4.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c
index a61e94a6d98..251486910f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c
index 46efd7379ac..7bb5a6f1e2b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c
index 8bebac219a6..a4c8bc67442 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c
index 47e4243e02e..71f56967a68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c
index 5331e547ed3..e932d46e4b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c
index 0c728f93514..8b12f9da5eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c
index ccfc40cd382..529052797fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c
index ce7ddbb99b2..f69fcbd086f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c
index ac0100a1211..fb09ffca324 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c
index b7ebef80954..2d99c6f2ac7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c
index 21fed06d201..7216631d167 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
index 0b936d849a1..a210d6b3e21 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
index 72070108ff6..38d0afae8ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 -Wno-psabi" } */
+/* { dg-options "-O3" } */
#define TEST_VAL 2
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
index 08300061832..b9fcfe70451 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c
index df87ed94ea4..f669c685ecb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c
index 494e40bbcc5..5316b4ef44b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
index 174860de559..893e5a3c6db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
index 158eec04e22..79509903326 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
index 3749d972a6d..2b088b53546 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
index 541745be2a1..78cd6388bc5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
index 9b5a240a9e6..4e26a573067 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
index 7b05c85a243..dec2512dc0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1down-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
index 74e8e5e63f7..5b9afa43deb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
index e7e2ee950c7..e989a06eb8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
index b0b3af24e64..f91a02c0f1d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vslide1up-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -Wno-psabi -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
index b7e25bfe819..993f4d0cc8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d" } */
#include "riscv_vector.h"
vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
index b3e879e6995..0d626095544 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zvbb_zve64x -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zvbb_zve64x -mabi=ilp32 -O3" } */
#include "riscv_vector.h"
vuint64m1_t test_vandn_vx_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c
index ae2a5b652d5..6975ae4c0e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvbc -mabi=lp64d -O2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvbc -mabi=lp64d -O2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c
index 8c1716373e8..1bf11e4c231 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zvbc -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zvbc -mabi=ilp32 -O3" } */
#include "riscv_vector.h"
vuint64m1_t test_vclmul_vx_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
index 9ee70d7eb72..3fb14660af8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvbc -mabi=lp64d -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvbc -mabi=lp64d -O3" } */
#include "riscv_vector.h"
vuint64m1_t test_vclmul_vx_u64m1_extend(vuint64m1_t vs2, uint32_t rs1, size_t vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 500748b8e79..193902d0e5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c
index fa68310bb1c..e60785ab1ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvkg_zve64x -mabi=lp64d -O2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvkg_zve64x -mabi=lp64d -O2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c
index 414157379da..c29a0f62bfb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvkned_zve64x -mabi=lp64d -O2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvkned_zve64x -mabi=lp64d -O2" } */
#include "riscv_vector.h"
vuint32mf2_t test_vaesdf_vv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c
index 40009adf6bb..f50828eb8dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvknha_zve64x -mabi=lp64d -O2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvknha_zve64x -mabi=lp64d -O2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c
index 78aebebb5ce..1d23903fa6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvknhb -mabi=lp64d -O2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvknhb -mabi=lp64d -O2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c
index b655fe83eb5..ad23239bd07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvksed_zve64x -mabi=lp64d -O2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvksed_zve64x -mabi=lp64d -O2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c
index 353e4e71775..77d82c0f70f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvksh_zve64x -mabi=lp64d -O2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gc_zvksh_zve64x -mabi=lp64d -O2" } */
#include "riscv_vector.h"
--
2.42.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
2024-01-15 6:00 [PATCH 1/2] RISC-V: delete all the vector psabi checking yanzhang.wang
2024-01-15 6:00 ` [PATCH 2/2] RISC-V: delete vector abi checking in all relevant tests yanzhang.wang
@ 2024-01-15 6:19 ` juzhe.zhong
2024-01-19 18:59 ` Andreas Schwab
2024-01-15 9:55 ` juzhe.zhong
2 siblings, 1 reply; 7+ messages in thread
From: juzhe.zhong @ 2024-01-15 6:19 UTC (permalink / raw)
To: yanzhang.wang, gcc-patches
Cc: Kito.cheng, pan2.li, 丁乐华, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 21059 bytes --]
I think you should also remove riscv_vector_abi
since vector ABI is ratified and we should by default enable vector calling convention by default.
juzhe.zhong@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding; yanzhang.wang
Subject: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
From: Yanzhang Wang <yanzhang.wang@intel.com>
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete.
(riscv_init_cumulative_args): Delete the checking.
(riscv_get_arg_info): Delete the checking.
(riscv_function_value): Delete the checking.
* config/riscv/riscv.h: Delete the member for checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the -Wno-psabi.
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
---
Have tested the two patches on my local and there's no regression.
---
gcc/config/riscv/riscv.cc | 80 +------------------
gcc/config/riscv/riscv.h | 2 -
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vector-abi-1.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-2.c | 15 ----
.../gcc.target/riscv/rvv/base/vector-abi-3.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-4.c | 16 ----
.../gcc.target/riscv/rvv/base/vector-abi-5.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-6.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-7.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-8.c | 14 ----
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../base/zero_base_load_store_optimization.c | 2 +-
.../riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +-
24 files changed, 15 insertions(+), 222 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e7f7ce605db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4844,59 +4844,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}
-/* Return true if a vector type is included in the type TYPE. */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
- if (riscv_v_ext_mode_p (TYPE_MODE (type)))
- return true;
-
- if (!COMPLETE_TYPE_P (type))
- return false;
-
- switch (TREE_CODE (type))
- {
- case RECORD_TYPE:
- /* If it is a record, it is further determined whether its fields have
- vector type. */
- for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
- if (TREE_CODE (f) == FIELD_DECL)
- {
- tree field_type = TREE_TYPE (f);
- if (!TYPE_P (field_type))
- break;
-
- if (riscv_arg_has_vector (field_type))
- return true;
- }
- break;
- case ARRAY_TYPE:
- return riscv_arg_has_vector (TREE_TYPE (type));
- default:
- break;
- }
-
- return false;
-}
-
-/* Pass the type to check whether it's a vector type or contains vector type.
- Only check the value type and no checking for vector pointer type. */
-
-static void
-riscv_pass_in_vector_p (const_tree type)
-{
- static int warned = 0;
-
- if (type && riscv_vector::lookup_vector_type_attribute (type) && !warned)
- {
- warning (OPT_Wpsabi,
- "ABI for the vector type is currently in experimental stage and "
- "may changes in the upcoming version of GCC.");
- warned = 1;
- }
-}
-
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0. */
@@ -4914,15 +4861,6 @@ riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
cum->variant_cc = (riscv_cc) fntype_abi (fntype).id ();
else
cum->variant_cc = RISCV_CC_BASE;
-
- if (fndecl)
- {
- const tree_function_decl &fn
- = FUNCTION_DECL_CHECK (fndecl)->function_decl;
-
- if (fn.built_in_class == NOT_BUILT_IN)
- cum->rvv_psabi_warning = 1;
- }
}
/* Return true if TYPE is a vector type that can be passed in vector registers.
@@ -5039,12 +4977,6 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
- if (cum->rvv_psabi_warning)
- {
- /* Only check existing of vector type. */
- riscv_pass_in_vector_p (type);
- }
-
/* When disable vector_abi or scalable vector argument is anonymous, this
argument is passed by reference. */
if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named))
@@ -5222,17 +5154,7 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
memset (&args, 0, sizeof args);
- const_tree arg_type = type;
- if (func && DECL_RESULT (func))
- {
- const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
- if (fn.built_in_class == NOT_BUILT_IN)
- args.rvv_psabi_warning = 1;
-
- arg_type = TREE_TYPE (DECL_RESULT (func));
- }
-
- return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
+ return riscv_get_arg_info (&info, &args, mode, type, true, true);
}
/* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index b13ccc5aba9..d97bed5c029 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -733,8 +733,6 @@ typedef struct {
/* Number of floating-point registers used so far, likewise. */
unsigned int num_fprs;
- int rvv_psabi_warning;
-
/* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */
unsigned int num_mrs;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index cc373465957..809b185dd65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include "riscv_vector.h"
vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 2942e0b2e53..1bca8467a16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index a6df1215c60..57d0241675a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 276173d02db..9563c8d27fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index c1df69ace57..e8b5bf8c714 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 9c310bbf590..80ee1b5f0c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index 89c96c8ef5e..d37857e24ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index 484a2510885..d9362ecd41b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index 5464a297670..ec673575b4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
deleted file mode 100644
index 114ee6de483..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
deleted file mode 100644
index 0b24ccb8312..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
-
-#include "riscv_vector.h"
-
-vint32m1_t
-fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
deleted file mode 100644
index 844a5db4027..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1_t*
-fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
deleted file mode 100644
index a5dc2dffaac..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-typedef int v4si __attribute__ ((vector_size (16)));
-
-v4si
-fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- v4si a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
deleted file mode 100644
index 9dc69518b5d..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; int b; };
-
-void foo (int b);
-
-void
-fun (struct A a) {
-
- foo (a.b);
-} /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- struct A a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
deleted file mode 100644
index 3a65f2c60ab..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-#include "riscv_vector.h"
-
-void
-foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
- size_t n, int cond) {
- size_t vl;
- if (cond)
- vl = __riscv_vsetvlmax_e32m1();
- else
- vl = __riscv_vsetvlmax_e16mf2();
- for (size_t i = 0; i < n; i += 1)
- {
- vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
- vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
- vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
- __riscv_vse32_v_i32m1(out, c, vl);
- }
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
deleted file mode 100644
index 2795fd4f9fb..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
deleted file mode 100644
index 9cf68d4da9c..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1x3_t*
-fun (vint32m1x3_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 51f4fac0a8b..501d98c5897 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index b27e5ccad09..fbcfb7b8501 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index 0e7c7cdbdd5..c951644de4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 9ae79663adf..1d82cc8de2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index c3519cedba7..be31df1d84b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
--
2.42.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
2024-01-15 6:00 [PATCH 1/2] RISC-V: delete all the vector psabi checking yanzhang.wang
2024-01-15 6:00 ` [PATCH 2/2] RISC-V: delete vector abi checking in all relevant tests yanzhang.wang
2024-01-15 6:19 ` [PATCH 1/2] RISC-V: delete all the vector psabi checking juzhe.zhong
@ 2024-01-15 9:55 ` juzhe.zhong
2024-01-16 2:16 ` Wang, Yanzhang
2 siblings, 1 reply; 7+ messages in thread
From: juzhe.zhong @ 2024-01-15 9:55 UTC (permalink / raw)
To: yanzhang.wang, gcc-patches
Cc: Kito.cheng, pan2.li, 丁乐华, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 21072 bytes --]
LGTM. I think removing riscv_vector_abi can be another separate followup patch.
But plz make sure you have passed the regression before committed.
Thanks.
juzhe.zhong@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding; yanzhang.wang
Subject: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
From: Yanzhang Wang <yanzhang.wang@intel.com>
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete.
(riscv_init_cumulative_args): Delete the checking.
(riscv_get_arg_info): Delete the checking.
(riscv_function_value): Delete the checking.
* config/riscv/riscv.h: Delete the member for checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the -Wno-psabi.
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
---
Have tested the two patches on my local and there's no regression.
---
gcc/config/riscv/riscv.cc | 80 +------------------
gcc/config/riscv/riscv.h | 2 -
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vector-abi-1.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-2.c | 15 ----
.../gcc.target/riscv/rvv/base/vector-abi-3.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-4.c | 16 ----
.../gcc.target/riscv/rvv/base/vector-abi-5.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-6.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-7.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-8.c | 14 ----
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../base/zero_base_load_store_optimization.c | 2 +-
.../riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +-
24 files changed, 15 insertions(+), 222 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e7f7ce605db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4844,59 +4844,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}
-/* Return true if a vector type is included in the type TYPE. */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
- if (riscv_v_ext_mode_p (TYPE_MODE (type)))
- return true;
-
- if (!COMPLETE_TYPE_P (type))
- return false;
-
- switch (TREE_CODE (type))
- {
- case RECORD_TYPE:
- /* If it is a record, it is further determined whether its fields have
- vector type. */
- for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
- if (TREE_CODE (f) == FIELD_DECL)
- {
- tree field_type = TREE_TYPE (f);
- if (!TYPE_P (field_type))
- break;
-
- if (riscv_arg_has_vector (field_type))
- return true;
- }
- break;
- case ARRAY_TYPE:
- return riscv_arg_has_vector (TREE_TYPE (type));
- default:
- break;
- }
-
- return false;
-}
-
-/* Pass the type to check whether it's a vector type or contains vector type.
- Only check the value type and no checking for vector pointer type. */
-
-static void
-riscv_pass_in_vector_p (const_tree type)
-{
- static int warned = 0;
-
- if (type && riscv_vector::lookup_vector_type_attribute (type) && !warned)
- {
- warning (OPT_Wpsabi,
- "ABI for the vector type is currently in experimental stage and "
- "may changes in the upcoming version of GCC.");
- warned = 1;
- }
-}
-
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0. */
@@ -4914,15 +4861,6 @@ riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
cum->variant_cc = (riscv_cc) fntype_abi (fntype).id ();
else
cum->variant_cc = RISCV_CC_BASE;
-
- if (fndecl)
- {
- const tree_function_decl &fn
- = FUNCTION_DECL_CHECK (fndecl)->function_decl;
-
- if (fn.built_in_class == NOT_BUILT_IN)
- cum->rvv_psabi_warning = 1;
- }
}
/* Return true if TYPE is a vector type that can be passed in vector registers.
@@ -5039,12 +4977,6 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
- if (cum->rvv_psabi_warning)
- {
- /* Only check existing of vector type. */
- riscv_pass_in_vector_p (type);
- }
-
/* When disable vector_abi or scalable vector argument is anonymous, this
argument is passed by reference. */
if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named))
@@ -5222,17 +5154,7 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
memset (&args, 0, sizeof args);
- const_tree arg_type = type;
- if (func && DECL_RESULT (func))
- {
- const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
- if (fn.built_in_class == NOT_BUILT_IN)
- args.rvv_psabi_warning = 1;
-
- arg_type = TREE_TYPE (DECL_RESULT (func));
- }
-
- return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
+ return riscv_get_arg_info (&info, &args, mode, type, true, true);
}
/* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index b13ccc5aba9..d97bed5c029 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -733,8 +733,6 @@ typedef struct {
/* Number of floating-point registers used so far, likewise. */
unsigned int num_fprs;
- int rvv_psabi_warning;
-
/* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */
unsigned int num_mrs;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index cc373465957..809b185dd65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include "riscv_vector.h"
vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 2942e0b2e53..1bca8467a16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index a6df1215c60..57d0241675a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 276173d02db..9563c8d27fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index c1df69ace57..e8b5bf8c714 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 9c310bbf590..80ee1b5f0c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index 89c96c8ef5e..d37857e24ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index 484a2510885..d9362ecd41b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index 5464a297670..ec673575b4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
deleted file mode 100644
index 114ee6de483..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
deleted file mode 100644
index 0b24ccb8312..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
-
-#include "riscv_vector.h"
-
-vint32m1_t
-fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
deleted file mode 100644
index 844a5db4027..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1_t*
-fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
deleted file mode 100644
index a5dc2dffaac..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-typedef int v4si __attribute__ ((vector_size (16)));
-
-v4si
-fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- v4si a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
deleted file mode 100644
index 9dc69518b5d..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; int b; };
-
-void foo (int b);
-
-void
-fun (struct A a) {
-
- foo (a.b);
-} /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- struct A a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
deleted file mode 100644
index 3a65f2c60ab..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-#include "riscv_vector.h"
-
-void
-foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
- size_t n, int cond) {
- size_t vl;
- if (cond)
- vl = __riscv_vsetvlmax_e32m1();
- else
- vl = __riscv_vsetvlmax_e16mf2();
- for (size_t i = 0; i < n; i += 1)
- {
- vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
- vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
- vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
- __riscv_vse32_v_i32m1(out, c, vl);
- }
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
deleted file mode 100644
index 2795fd4f9fb..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
deleted file mode 100644
index 9cf68d4da9c..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1x3_t*
-fun (vint32m1x3_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 51f4fac0a8b..501d98c5897 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index b27e5ccad09..fbcfb7b8501 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index 0e7c7cdbdd5..c951644de4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 9ae79663adf..1d82cc8de2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index c3519cedba7..be31df1d84b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
--
2.42.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
2024-01-15 9:55 ` juzhe.zhong
@ 2024-01-16 2:16 ` Wang, Yanzhang
2024-01-16 2:21 ` Li, Pan2
0 siblings, 1 reply; 7+ messages in thread
From: Wang, Yanzhang @ 2024-01-16 2:16 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Kito.cheng, Li, Pan2, 丁乐华
[-- Attachment #1: Type: text/plain, Size: 21939 bytes --]
Thanks Juzhe. Yes I have passed the regression test with the two patches.
I’ll file another patch to remove riscv_vector_abi.
Thanks,
Yanzhang
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Monday, January 15, 2024 5:55 PM
To: Wang, Yanzhang <yanzhang.wang@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Kito.cheng <kito.cheng@sifive.com>; Li, Pan2 <pan2.li@intel.com>; 丁乐华 <lehua.ding@rivai.ai>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
LGTM. I think removing riscv_vector_abi can be another separate followup patch.
But plz make sure you have passed the regression before committed.
Thanks.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: yanzhang.wang<mailto:yanzhang.wang@intel.com>
Date: 2024-01-15 14:00
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; lehua.ding<mailto:lehua.ding@rivai.ai>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
From: Yanzhang Wang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete.
(riscv_init_cumulative_args): Delete the checking.
(riscv_get_arg_info): Delete the checking.
(riscv_function_value): Delete the checking.
* config/riscv/riscv.h: Delete the member for checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the -Wno-psabi.
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
---
Have tested the two patches on my local and there's no regression.
---
gcc/config/riscv/riscv.cc | 80 +------------------
gcc/config/riscv/riscv.h | 2 -
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vector-abi-1.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-2.c | 15 ----
.../gcc.target/riscv/rvv/base/vector-abi-3.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-4.c | 16 ----
.../gcc.target/riscv/rvv/base/vector-abi-5.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-6.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-7.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-8.c | 14 ----
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../base/zero_base_load_store_optimization.c | 2 +-
.../riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +-
24 files changed, 15 insertions(+), 222 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e7f7ce605db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4844,59 +4844,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}
-/* Return true if a vector type is included in the type TYPE. */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
- if (riscv_v_ext_mode_p (TYPE_MODE (type)))
- return true;
-
- if (!COMPLETE_TYPE_P (type))
- return false;
-
- switch (TREE_CODE (type))
- {
- case RECORD_TYPE:
- /* If it is a record, it is further determined whether its fields have
- vector type. */
- for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
- if (TREE_CODE (f) == FIELD_DECL)
- {
- tree field_type = TREE_TYPE (f);
- if (!TYPE_P (field_type))
- break;
-
- if (riscv_arg_has_vector (field_type))
- return true;
- }
- break;
- case ARRAY_TYPE:
- return riscv_arg_has_vector (TREE_TYPE (type));
- default:
- break;
- }
-
- return false;
-}
-
-/* Pass the type to check whether it's a vector type or contains vector type.
- Only check the value type and no checking for vector pointer type. */
-
-static void
-riscv_pass_in_vector_p (const_tree type)
-{
- static int warned = 0;
-
- if (type && riscv_vector::lookup_vector_type_attribute (type) && !warned)
- {
- warning (OPT_Wpsabi,
- "ABI for the vector type is currently in experimental stage and "
- "may changes in the upcoming version of GCC.");
- warned = 1;
- }
-}
-
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0. */
@@ -4914,15 +4861,6 @@ riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
cum->variant_cc = (riscv_cc) fntype_abi (fntype).id ();
else
cum->variant_cc = RISCV_CC_BASE;
-
- if (fndecl)
- {
- const tree_function_decl &fn
- = FUNCTION_DECL_CHECK (fndecl)->function_decl;
-
- if (fn.built_in_class == NOT_BUILT_IN)
- cum->rvv_psabi_warning = 1;
- }
}
/* Return true if TYPE is a vector type that can be passed in vector registers.
@@ -5039,12 +4977,6 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
- if (cum->rvv_psabi_warning)
- {
- /* Only check existing of vector type. */
- riscv_pass_in_vector_p (type);
- }
-
/* When disable vector_abi or scalable vector argument is anonymous, this
argument is passed by reference. */
if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named))
@@ -5222,17 +5154,7 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
memset (&args, 0, sizeof args);
- const_tree arg_type = type;
- if (func && DECL_RESULT (func))
- {
- const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
- if (fn.built_in_class == NOT_BUILT_IN)
- args.rvv_psabi_warning = 1;
-
- arg_type = TREE_TYPE (DECL_RESULT (func));
- }
-
- return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
+ return riscv_get_arg_info (&info, &args, mode, type, true, true);
}
/* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index b13ccc5aba9..d97bed5c029 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -733,8 +733,6 @@ typedef struct {
/* Number of floating-point registers used so far, likewise. */
unsigned int num_fprs;
- int rvv_psabi_warning;
-
/* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */
unsigned int num_mrs;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index cc373465957..809b185dd65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include "riscv_vector.h"
vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 2942e0b2e53..1bca8467a16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index a6df1215c60..57d0241675a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 276173d02db..9563c8d27fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index c1df69ace57..e8b5bf8c714 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 9c310bbf590..80ee1b5f0c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index 89c96c8ef5e..d37857e24ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index 484a2510885..d9362ecd41b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index 5464a297670..ec673575b4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
deleted file mode 100644
index 114ee6de483..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
deleted file mode 100644
index 0b24ccb8312..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
-
-#include "riscv_vector.h"
-
-vint32m1_t
-fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
deleted file mode 100644
index 844a5db4027..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1_t*
-fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
deleted file mode 100644
index a5dc2dffaac..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-typedef int v4si __attribute__ ((vector_size (16)));
-
-v4si
-fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- v4si a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
deleted file mode 100644
index 9dc69518b5d..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; int b; };
-
-void foo (int b);
-
-void
-fun (struct A a) {
-
- foo (a.b);
-} /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- struct A a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
deleted file mode 100644
index 3a65f2c60ab..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-#include "riscv_vector.h"
-
-void
-foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
- size_t n, int cond) {
- size_t vl;
- if (cond)
- vl = __riscv_vsetvlmax_e32m1();
- else
- vl = __riscv_vsetvlmax_e16mf2();
- for (size_t i = 0; i < n; i += 1)
- {
- vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
- vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
- vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
- __riscv_vse32_v_i32m1(out, c, vl);
- }
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
deleted file mode 100644
index 2795fd4f9fb..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
deleted file mode 100644
index 9cf68d4da9c..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1x3_t*
-fun (vint32m1x3_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 51f4fac0a8b..501d98c5897 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index b27e5ccad09..fbcfb7b8501 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index 0e7c7cdbdd5..c951644de4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 9ae79663adf..1d82cc8de2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index c3519cedba7..be31df1d84b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
--
2.42.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
2024-01-16 2:16 ` Wang, Yanzhang
@ 2024-01-16 2:21 ` Li, Pan2
0 siblings, 0 replies; 7+ messages in thread
From: Li, Pan2 @ 2024-01-16 2:21 UTC (permalink / raw)
To: Wang, Yanzhang, juzhe.zhong, gcc-patches
Cc: Kito.cheng, 丁乐华
[-- Attachment #1: Type: text/plain, Size: 22542 bytes --]
Committed, thanks all.
Pan
From: Wang, Yanzhang <yanzhang.wang@intel.com>
Sent: Tuesday, January 16, 2024 10:16 AM
To: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Kito.cheng <kito.cheng@sifive.com>; Li, Pan2 <pan2.li@intel.com>; 丁乐华 <lehua.ding@rivai.ai>
Subject: RE: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
Thanks Juzhe. Yes I have passed the regression test with the two patches.
I’ll file another patch to remove riscv_vector_abi.
Thanks,
Yanzhang
From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Monday, January 15, 2024 5:55 PM
To: Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; 丁乐华 <lehua.ding@rivai.ai<mailto:lehua.ding@rivai.ai>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
LGTM. I think removing riscv_vector_abi can be another separate followup patch.
But plz make sure you have passed the regression before committed.
Thanks.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: yanzhang.wang<mailto:yanzhang.wang@intel.com>
Date: 2024-01-15 14:00
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; lehua.ding<mailto:lehua.ding@rivai.ai>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
From: Yanzhang Wang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
(riscv_pass_in_vector_p): Delete.
(riscv_init_cumulative_args): Delete the checking.
(riscv_get_arg_info): Delete the checking.
(riscv_function_value): Delete the checking.
* config/riscv/riscv.h: Delete the member for checking.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the -Wno-psabi.
* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
---
Have tested the two patches on my local and there's no regression.
---
gcc/config/riscv/riscv.cc | 80 +------------------
gcc/config/riscv/riscv.h | 2 -
.../riscv/rvv/base/binop_vx_constraint-120.c | 2 +-
.../rvv/base/integer_compare_insn_shortcut.c | 2 +-
.../riscv/rvv/base/mask_insn_shortcut.c | 2 +-
.../rvv/base/misc_vreinterpret_vbool_vint.c | 2 +-
.../gcc.target/riscv/rvv/base/pr110109-2.c | 2 +-
.../gcc.target/riscv/rvv/base/scalar_move-9.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-10.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-11.c | 2 +-
.../gcc.target/riscv/rvv/base/spill-9.c | 2 +-
.../gcc.target/riscv/rvv/base/vector-abi-1.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-2.c | 15 ----
.../gcc.target/riscv/rvv/base/vector-abi-3.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-4.c | 16 ----
.../gcc.target/riscv/rvv/base/vector-abi-5.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-6.c | 20 -----
.../gcc.target/riscv/rvv/base/vector-abi-7.c | 14 ----
.../gcc.target/riscv/rvv/base/vector-abi-8.c | 14 ----
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 2 +-
.../base/zero_base_load_store_optimization.c | 2 +-
.../riscv/rvv/base/zvfh-intrinsic.c | 2 +-
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c | 2 +-
24 files changed, 15 insertions(+), 222 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e7f7ce605db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4844,59 +4844,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}
-/* Return true if a vector type is included in the type TYPE. */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
- if (riscv_v_ext_mode_p (TYPE_MODE (type)))
- return true;
-
- if (!COMPLETE_TYPE_P (type))
- return false;
-
- switch (TREE_CODE (type))
- {
- case RECORD_TYPE:
- /* If it is a record, it is further determined whether its fields have
- vector type. */
- for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
- if (TREE_CODE (f) == FIELD_DECL)
- {
- tree field_type = TREE_TYPE (f);
- if (!TYPE_P (field_type))
- break;
-
- if (riscv_arg_has_vector (field_type))
- return true;
- }
- break;
- case ARRAY_TYPE:
- return riscv_arg_has_vector (TREE_TYPE (type));
- default:
- break;
- }
-
- return false;
-}
-
-/* Pass the type to check whether it's a vector type or contains vector type.
- Only check the value type and no checking for vector pointer type. */
-
-static void
-riscv_pass_in_vector_p (const_tree type)
-{
- static int warned = 0;
-
- if (type && riscv_vector::lookup_vector_type_attribute (type) && !warned)
- {
- warning (OPT_Wpsabi,
- "ABI for the vector type is currently in experimental stage and "
- "may changes in the upcoming version of GCC.");
- warned = 1;
- }
-}
-
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0. */
@@ -4914,15 +4861,6 @@ riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
cum->variant_cc = (riscv_cc) fntype_abi (fntype).id ();
else
cum->variant_cc = RISCV_CC_BASE;
-
- if (fndecl)
- {
- const tree_function_decl &fn
- = FUNCTION_DECL_CHECK (fndecl)->function_decl;
-
- if (fn.built_in_class == NOT_BUILT_IN)
- cum->rvv_psabi_warning = 1;
- }
}
/* Return true if TYPE is a vector type that can be passed in vector registers.
@@ -5039,12 +4977,6 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
- if (cum->rvv_psabi_warning)
- {
- /* Only check existing of vector type. */
- riscv_pass_in_vector_p (type);
- }
-
/* When disable vector_abi or scalable vector argument is anonymous, this
argument is passed by reference. */
if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named))
@@ -5222,17 +5154,7 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
memset (&args, 0, sizeof args);
- const_tree arg_type = type;
- if (func && DECL_RESULT (func))
- {
- const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
- if (fn.built_in_class == NOT_BUILT_IN)
- args.rvv_psabi_warning = 1;
-
- arg_type = TREE_TYPE (DECL_RESULT (func));
- }
-
- return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
+ return riscv_get_arg_info (&info, &args, mode, type, true, true);
}
/* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index b13ccc5aba9..d97bed5c029 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -733,8 +733,6 @@ typedef struct {
/* Number of floating-point registers used so far, likewise. */
unsigned int num_fprs;
- int rvv_psabi_warning;
-
/* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS. */
unsigned int num_mrs;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index cc373465957..809b185dd65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include "riscv_vector.h"
vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 2942e0b2e53..1bca8467a16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index a6df1215c60..57d0241675a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 276173d02db..9563c8d27fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index c1df69ace57..e8b5bf8c714 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 9c310bbf590..80ee1b5f0c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index 89c96c8ef5e..d37857e24ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index 484a2510885..d9362ecd41b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index 5464a297670..ec673575b4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
deleted file mode 100644
index 114ee6de483..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
deleted file mode 100644
index 0b24ccb8312..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */
-
-#include "riscv_vector.h"
-
-vint32m1_t
-fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
deleted file mode 100644
index 844a5db4027..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1_t*
-fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
deleted file mode 100644
index a5dc2dffaac..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-typedef int v4si __attribute__ ((vector_size (16)));
-
-v4si
-fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- v4si a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
deleted file mode 100644
index 9dc69518b5d..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; int b; };
-
-void foo (int b);
-
-void
-fun (struct A a) {
-
- foo (a.b);
-} /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- struct A a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
deleted file mode 100644
index 3a65f2c60ab..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-#include "riscv_vector.h"
-
-void
-foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
- size_t n, int cond) {
- size_t vl;
- if (cond)
- vl = __riscv_vsetvlmax_e32m1();
- else
- vl = __riscv_vsetvlmax_e16mf2();
- for (size_t i = 0; i < n; i += 1)
- {
- vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
- vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
- vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
- __riscv_vse32_v_i32m1(out, c, vl);
- }
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
deleted file mode 100644
index 2795fd4f9fb..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
deleted file mode 100644
index 9cf68d4da9c..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1x3_t*
-fun (vint32m1x3_t* a) { return a; } /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
- vint32m1x3_t a;
- fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 51f4fac0a8b..501d98c5897 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index b27e5ccad09..fbcfb7b8501 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index 0e7c7cdbdd5..c951644de4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 9ae79663adf..1d82cc8de2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index c3519cedba7..be31df1d84b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
--
2.42.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.
2024-01-15 6:19 ` [PATCH 1/2] RISC-V: delete all the vector psabi checking juzhe.zhong
@ 2024-01-19 18:59 ` Andreas Schwab
0 siblings, 0 replies; 7+ messages in thread
From: Andreas Schwab @ 2024-01-19 18:59 UTC (permalink / raw)
To: juzhe.zhong
Cc: yanzhang.wang, gcc-patches, Kito.cheng, pan2.li,
丁乐华
../../gcc/config/riscv/riscv.cc: In function 'void riscv_init_cumulative_args(CUMULATIVE_ARGS*, tree, rtx, tree, int)':
../../gcc/config/riscv/riscv.cc:4879:34: error: unused parameter 'fndecl' [-Werror=unused-parameter]
4879 | tree fndecl,
| ~~~~~^~~~~~
../../gcc/config/riscv/riscv.cc: In function 'bool riscv_vector_mode_supported_any_target_p(machine_mode)':
../../gcc/config/riscv/riscv.cc:10537:56: error: unused parameter 'mode' [-Werror=unused-parameter]
10537 | riscv_vector_mode_supported_any_target_p (machine_mode mode)
| ~~~~~~~~~~~~~^~~~
cc1plus: all warnings being treated as errors
make[3]: *** [Makefile:2559: riscv.o] Error 1
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-01-19 18:59 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-15 6:00 [PATCH 1/2] RISC-V: delete all the vector psabi checking yanzhang.wang
2024-01-15 6:00 ` [PATCH 2/2] RISC-V: delete vector abi checking in all relevant tests yanzhang.wang
2024-01-15 6:19 ` [PATCH 1/2] RISC-V: delete all the vector psabi checking juzhe.zhong
2024-01-19 18:59 ` Andreas Schwab
2024-01-15 9:55 ` juzhe.zhong
2024-01-16 2:16 ` Wang, Yanzhang
2024-01-16 2:21 ` Li, Pan2
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).