From: Jeff Law <jeffreyalaw@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org
Cc: Kito Cheng <kito.cheng@gmail.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Vineet Gupta <vineetg@rivosinc.com>,
Jeff Law <jlaw@ventanamicro.com>,
Christoph Muellner <christoph.muellner@vrull.eu>
Subject: Re: [PATCH v2 0/2] Use Zbs with xori/ori/andi and polarity-reversed twobit-tests
Date: Fri, 18 Nov 2022 12:13:45 -0700 [thread overview]
Message-ID: <8ca4581a-cd38-5ba0-2bdc-158d58fdf52a@gmail.com> (raw)
In-Reply-To: <20221118111001.1488517-1-philipp.tomsich@vrull.eu>
On 11/18/22 04:09, Philipp Tomsich wrote:
> We had a few patches on the list that shared predicates (for extending
> the reach of xori and ori -- and for the branches on two
> polarity-reversed bits) and thus depended on each other.
>
> These all had approval with requested changes, so these are now
> collected together for v2.
>
> Note that this adds the (a & ~C) case, so please take a look on that
> part and OK the updated series.
>
>
>
> Changes in v2:
> - Collects already approved changes for v2 for (a | C) and (a ^ C).
> - Pulls in the (already) approved branch on polarity-reversed bits
> for v2, as it shares predicates with the other changes.
> - Newly adds support for the (a & ~C) case.
>
> Philipp Tomsich (2):
> RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori
> RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs
>
> gcc/config/riscv/bitmanip.md | 79 +++++++++++++++++++
> gcc/config/riscv/iterators.md | 8 ++
> gcc/config/riscv/predicates.md | 33 ++++++++
> gcc/config/riscv/riscv.h | 8 ++
> .../riscv/{zbs-bclri.c => zbs-bclri-01.c} | 0
> gcc/testsuite/gcc.target/riscv/zbs-bclri-02.c | 27 +++++++
> gcc/testsuite/gcc.target/riscv/zbs-binvi.c | 22 ++++++
> gcc/testsuite/gcc.target/riscv/zbs-bseti.c | 27 +++++++
> .../gcc.target/riscv/zbs-if_then_else-01.c | 20 +++++
> 9 files changed, 224 insertions(+)
> rename gcc/testsuite/gcc.target/riscv/{zbs-bclri.c => zbs-bclri-01.c} (100%)
> create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bclri-02.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-binvi.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bseti.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c
1/2 and 2/2 are both OK.
jeff
next prev parent reply other threads:[~2022-11-18 19:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-18 11:09 Philipp Tomsich
2022-11-18 11:10 ` [PATCH v2 1/2] RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori Philipp Tomsich
2022-11-18 11:10 ` [PATCH v2 2/2] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs Philipp Tomsich
2022-11-18 19:13 ` Jeff Law [this message]
2022-11-18 20:04 ` [PATCH v2 0/2] Use Zbs with xori/ori/andi and polarity-reversed twobit-tests Philipp Tomsich
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