Re: [PATCH v2] rs6000: Add new pass for replacement of contiguous addresses vector load lxv with lxvp

["Kewen.Lin" <linkw@linux.ibm.com>]

Hi Ajit,

on 2023/12/8 16:01, Ajit Agarwal wrote:
> Hello Kewen:
> 

[snip...]

> With UNSPEC_MMA_EXTRACT I could generate the register pair but functionally here is the
> below code which is incorrect.
> 
>  l	lxvp %vs0,0(%r4)
>         xxlor %vs32,%vs0,%vs0
>         xvf32ger 0,%vs34,%vs32
>         xvf32gerpp 0,%vs34,%vs33
>         xxmfacc 0
>         stxvp %vs2,0(%r3)
>         stxvp %vs0,32(%r3)
>         blr
> 
> 
> Here is the RTL Code:
> 
> (insn 19 4 20 2 (set (reg:OO 124 [ *ptr_4(D) ])
>         (mem:OO (reg/v/f:DI 122 [ ptr ]) [0 *ptr_4(D)+0 S16 A128])) -1
>      (nil))
> (insn 20 19 9 2 (set (reg:V16QI 129 [orig:124 *ptr_4(D) ] [124])
>         (subreg:V16QI (reg:OO 124 [ *ptr_4(D) ]) 0)) -1
>      (nil))
> (insn 9 20 11 2 (set (reg:XO 119 [ _7 ])
>         (unspec:XO [
>                 (reg/v:V16QI 123 [ src ])
>                 (reg:V16QI 129 [orig:124 *ptr_4(D) ] [124])
>             ] UNSPEC_MMA_XVF32GER)) 2195 {mma_xvf32ger}
>      (expr_list:REG_DEAD (reg:OO 124 [ *ptr_4(D) ])
>         (nil)))
> (insn 11 9 12 2 (set (reg:XO 120 [ _9 ])
>         (unspec:XO [
>                 (reg:XO 119 [ _7 ])
>                 (reg/v:V16QI 123 [ src ])
>                 (reg:V16QI 125 [ MEM[(__vector unsigned char *)ptr_4(D) + 16B] ])
>             ] UNSPEC_MMA_XVF32GERPP)) 2209 {mma_xvf32gerpp}
>      (expr_list:REG_DEAD (reg:V16QI 125 [ MEM[(__vector unsigned char *)ptr_4(D) + 16B] ])
>         (expr_list:REG_DEAD (reg/v:V16QI 123 [ src ])
>             (expr_list:REG_DEAD (reg:XO 119 [ _7 ])
>                 (nil)))))
> (insn 12 11 18 2 (set (mem:XO (reg:DI 126) [1 *dst_10(D)+0 S64 A128])
>         (reg:XO 120 [ _9 ])) "../gcc/testsuite/g++.target/powerpc/vecload.C":13:8 2182 {*movxo}
>      (expr_list:REG_DEAD (reg:DI 126)
>         (expr_list:REG_DEAD (reg:XO 120 [ _9 ])
>             (nil))))
> (note 18 12 0 NOTE_INSN_DELETED)
> 
> r124 and r129 conflicts live range amd ira generates different registers which will not
> serve our purpose.
> 
> Making r124 and r129 as same will not allocate register by ira as r124 could have both OOmode
> and V16QImode.
> 
> Doing this pass before ira_pass has such above issues and we could solve them after making
> after reload pass.

Could you also attach your latest WIP patch?  I'm going to look into the extra move issue with it.

Thanks!

BR,
Kewen