[PATCH v2 0/3] [GCC] arm: vst1_types_xN ACLE intrinsics

[PATCH v2 0/3] [GCC] arm: vst1_types_xN ACLE intrinsics

[Ezra.Sitorus]

Add xN variants of vst1_types intrinsic.

[PATCH v2 1/3] [GCC] arm: vst1_types_x2 ACLE intrinsics

[Ezra.Sitorus]

From: Ezra Sitorus <ezra.sitorus@arm.com>

This patch is part of a series of patches implementing the _xN
variants of the vst1 intrinsic for the arm port. This patch adds the
_x2 variants of the vst1 intrinsic.

ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/

ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/

gcc/ChangeLog:
        * config/arm/arm_neon.h
        (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
        (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
        (vst1_f16_x2, vst1_f32_x2): New.
        (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
        (vst1_bf16_x2): New.
        * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
        * config/arm/neon.md (vst1_x2<mode>): New.

gcc/testsuite/ChangeLog:
        * gcc.target/arm/simd/vst1_base_xN_1.c: Add new tests.
        * gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new tests.
        * gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new tests.
        * gcc.target/arm/simd/vst1_p64_xN_1.c: Add new tests.
---
 gcc/config/arm/arm_neon.h                     | 114 ++++++++++++++++++
 gcc/config/arm/arm_neon_builtins.def          |   1 +
 gcc/config/arm/neon.md                        |  10 ++
 .../gcc.target/arm/simd/vst1_base_xN_1.c      |  67 ++++++++++
 .../gcc.target/arm/simd/vst1_bf16_xN_1.c      |  13 ++
 .../gcc.target/arm/simd/vst1_fp16_xN_1.c      |  13 ++
 .../gcc.target/arm/simd/vst1_p64_xN_1.c       |  13 ++
 7 files changed, 231 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index c03be9912f8..60f1077752c 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11242,6 +11242,14 @@ vst1_p64 (poly64_t * __a, poly64x1_t __b)
   __builtin_neon_vst1di ((__builtin_neon_di *) __a, __b);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x2 (poly64_t * __a, poly64x1x2_t __b)
+{
+  union { poly64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 #pragma GCC pop_options
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11271,6 +11279,38 @@ vst1_s64 (int64_t * __a, int64x1_t __b)
   __builtin_neon_vst1di ((__builtin_neon_di *) __a, __b);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x2 (int8_t * __a, int8x8x2_t __b)
+{
+  union { int8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x2 (int16_t * __a, int16x4x2_t __b)
+{
+  union { int16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x2 (int32_t * __a, int32x2x2_t __b)
+{
+  union { int32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x2 (int64_t * __a, int64x1x2_t __b)
+{
+  union { int64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11287,6 +11327,24 @@ vst1_f32 (float32_t * __a, float32x2_t __b)
   __builtin_neon_vst1v2sf ((__builtin_neon_sf *) __a, __b);
 }
 
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x2 (float16_t * __a, float16x4x2_t __b)
+{
+  union { float16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v4hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x2 (float32_t * __a, float32x2x2_t __b)
+{
+  union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1_u8 (uint8_t * __a, uint8x8_t __b)
@@ -11315,6 +11373,38 @@ vst1_u64 (uint64_t * __a, uint64x1_t __b)
   __builtin_neon_vst1di ((__builtin_neon_di *) __a, (int64x1_t) __b);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x2 (uint8_t * __a, uint8x8x2_t __b)
+{
+  union { uint8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x2 (uint16_t * __a, uint16x4x2_t __b)
+{
+  union { uint16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x2 (uint32_t * __a, uint32x2x2_t __b)
+{
+  union { uint32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x2 (uint64_t * __a, uint64x1x2_t __b)
+{
+  union { uint64x1x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1_p8 (poly8_t * __a, poly8x8_t __b)
@@ -11329,6 +11419,22 @@ vst1_p16 (poly16_t * __a, poly16x4_t __b)
   __builtin_neon_vst1v4hi ((__builtin_neon_hi *) __a, (int16x4_t) __b);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x2 (poly8_t * __a, poly8x8x2_t __b)
+{
+  union { poly8x8x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x2 (poly16_t * __a, poly16x4x2_t __b)
+{
+  union { poly16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
 #pragma GCC push_options
 #pragma GCC target ("fpu=crypto-neon-fp-armv8")
 __extension__ extern __inline void
@@ -20070,6 +20176,14 @@ vst1_bf16 (bfloat16_t * __a, bfloat16x4_t __b)
   __builtin_neon_vst1v4bf (__a, __b);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_bf16_x2 (bfloat16_t * __a, bfloat16x4x2_t __b)
+{
+  union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
+  __builtin_neon_vst1_x2v4bf ((__builtin_neon_bf *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 90dad8cf6d1..6f16bf0863c 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -311,6 +311,7 @@ VAR10 (LOAD1, vld1_dup,
 VAR14 (STORE1, vst1,
         v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
         v4bf, v8bf)
+VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
 VAR14 (STORE1LANE, vst1_lane,
        v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
 VAR13 (LOAD1, vld2,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index b8f8fd6b928..2a7286dee52 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5125,6 +5125,16 @@ if (BYTES_BIG_ENDIAN)
 		     UNSPEC_VST1))]
   "TARGET_NEON")
 
+(define_insn "neon_vst1_x2<mode>"
+  [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
+        (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
+                    (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                   UNSPEC_VST1))]
+  "TARGET_NEON"
+  "vst1.<V_sz_elem>\t%h1, %A0"
+  [(set_attr "type" "neon_store1_2reg<q>")]
+)
+
 (define_insn "neon_vst1<mode>"
   [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
 	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
new file mode 100644
index 00000000000..575897fa422
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
@@ -0,0 +1,67 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_u8_x2 (uint8_t * ptr, uint8x8x2_t val)
+{
+    vst1_u8_x2 (ptr, val);
+}
+
+void test_vst1_u16_x2 (uint16_t * ptr, uint16x4x2_t val)
+{
+    vst1_u16_x2 (ptr, val);
+}
+
+void test_vst1_u32_x2 (uint32_t * ptr, uint32x2x2_t val)
+{
+    vst1_u32_x2 (ptr, val);
+}
+
+void test_vst1_u64_x2 (uint64_t * ptr, uint64x1x2_t val)
+{
+    vst1_u64_x2 (ptr, val);
+}
+
+void test_vst1_s8_x2 (int8_t * ptr, int8x8x2_t val)
+{
+    vst1_s8_x2 (ptr, val);
+}
+
+void test_vst1_s16_x2 (int16_t * ptr, int16x4x2_t val)
+{
+    vst1_s16_x2 (ptr, val);
+}
+
+void test_vst1_s32_x2 (int32_t * ptr, int32x2x2_t val)
+{
+    vst1_s32_x2 (ptr, val);
+}
+
+void test_vst1_s64_x2 (int64_t * ptr, int64x1x2_t val)
+{
+    vst1_s64_x2 (ptr, val);
+}
+
+void test_vst1_f32_x2 (float32_t * ptr, float32x2x2_t val)
+{
+    vst1_f32_x2 (ptr, val);
+}
+
+void test_vst1_p8_x2 (poly8_t * ptr, poly8x8x2_t val)
+{
+    vst1_p8_x2 (ptr, val);
+}
+
+void test_vst1_p16_x2 (poly16_t * ptr, poly16x4x2_t val)
+{
+    vst1_p16_x2 (ptr, val);
+}
+
+
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
new file mode 100644
index 00000000000..213fd20ee65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_bf16_x2 (bfloat16_t * ptr, bfloat16x4x2_t val)
+{
+    vst1_bf16_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
new file mode 100644
index 00000000000..523aec92db2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+void test_vst1_f16_x2 (float16_t * ptr, float16x4x2_t val)
+{
+    vst1_f16_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
new file mode 100644
index 00000000000..f590ebd7b94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1_p64_x2 (poly64_t * ptr, poly64x1x2_t val)
+{
+    vst1_p64_x2 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } }  */
\ No newline at end of file
-- 
2.25.1

[PATCH v2 2/3] [GCC] arm: vst1_types_x3 ACLE intrinsics

[Ezra.Sitorus]

From: Ezra Sitorus <ezra.sitorus@arm.com>

This patch is part of a series of patches implementing the _xN
variants of the vst1 intrinsic for the arm port. This patch adds the
_x3 variants of the vst1 intrinsic.

ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/

ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/

gcc/ChangeLog:
        * config/arm/arm_neon.h
        (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
        (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
        (vst1_f16_x3, vst1_f32_x3): New.
        (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
        (vst1_bf16_x3): New.
        * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
        * config/arm/neon.md (vst1_x3<mode>): New.

gcc/testsuite/ChangeLog:
        * gcc.target/arm/simd/vst1_base_xN_1.c: Add new test.
        * gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new test.
        * gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new test.
        * gcc.target/arm/simd/vst1_p64_xN_1.c: Add new test.
---
 gcc/config/arm/arm_neon.h                     | 114 ++++++++++++++++++
 gcc/config/arm/arm_neon_builtins.def          |   1 +
 gcc/config/arm/neon.md                        |  10 ++
 .../gcc.target/arm/simd/vst1_base_xN_1.c      |  63 +++++++++-
 .../gcc.target/arm/simd/vst1_bf16_xN_1.c      |   7 +-
 .../gcc.target/arm/simd/vst1_fp16_xN_1.c      |   7 +-
 .../gcc.target/arm/simd/vst1_p64_xN_1.c       |   7 +-
 7 files changed, 202 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 60f1077752c..e76be3516d9 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11250,6 +11250,14 @@ vst1_p64_x2 (poly64_t * __a, poly64x1x2_t __b)
   __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x3 (poly64_t * __a, poly64x1x3_t __b)
+{
+  union { poly64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 #pragma GCC pop_options
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11311,6 +11319,38 @@ vst1_s64_x2 (int64_t * __a, int64x1x2_t __b)
   __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x3 (int8_t * __a, int8x8x3_t __b)
+{
+  union { int8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x3 (int16_t * __a, int16x4x3_t __b)
+{
+  union { int16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x3 (int32_t * __a, int32x2x3_t __b)
+{
+  union { int32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x3 (int64_t * __a, int64x1x3_t __b)
+{
+  union { int64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11345,6 +11385,24 @@ vst1_f32_x2 (float32_t * __a, float32x2x2_t __b)
   __builtin_neon_vst1_x2v2sf ((__builtin_neon_sf *) __a, __bu.__o);
 }
 
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x3 (float16_t * __a, float16x4x3_t __b)
+{
+  union { float16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v4hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x3 (float32_t * __a, float32x2x3_t __b)
+{
+  union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1_u8 (uint8_t * __a, uint8x8_t __b)
@@ -11405,6 +11463,38 @@ vst1_u64_x2 (uint64_t * __a, uint64x1x2_t __b)
   __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x3 (uint8_t * __a, uint8x8x3_t __b)
+{
+  union { uint8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x3 (uint16_t * __a, uint16x4x3_t __b)
+{
+  union { uint16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x3 (uint32_t * __a, uint32x2x3_t __b)
+{
+  union { uint32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x3 (uint64_t * __a, uint64x1x3_t __b)
+{
+  union { uint64x1x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1_p8 (poly8_t * __a, poly8x8_t __b)
@@ -11435,6 +11525,22 @@ vst1_p16_x2 (poly16_t * __a, poly16x4x2_t __b)
   __builtin_neon_vst1_x2v4hi ((__builtin_neon_hi *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x3 (poly8_t * __a, poly8x8x3_t __b)
+{
+  union { poly8x8x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x3 (poly16_t * __a, poly16x4x3_t __b)
+{
+  union { poly16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
 #pragma GCC push_options
 #pragma GCC target ("fpu=crypto-neon-fp-armv8")
 __extension__ extern __inline void
@@ -20184,6 +20290,14 @@ vst1_bf16_x2 (bfloat16_t * __a, bfloat16x4x2_t __b)
   __builtin_neon_vst1_x2v4bf ((__builtin_neon_bf *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_bf16_x3 (bfloat16_t * __a, bfloat16x4x3_t __b)
+{
+  union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
+  __builtin_neon_vst1_x3v4bf ((__builtin_neon_bf *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 6f16bf0863c..8b104b1a700 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -312,6 +312,7 @@ VAR14 (STORE1, vst1,
         v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
         v4bf, v8bf)
 VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
 VAR14 (STORE1LANE, vst1_lane,
        v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
 VAR13 (LOAD1, vld2,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 2a7286dee52..5185434d6d9 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5135,6 +5135,16 @@ if (BYTES_BIG_ENDIAN)
   [(set_attr "type" "neon_store1_2reg<q>")]
 )
 
+(define_insn "neon_vst1_x3<mode>"
+  [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
+        (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
+                    (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                   UNSPEC_VST1))]
+  "TARGET_NEON"
+  "vst1.<V_sz_elem>\t%h1, %A0"
+  [(set_attr "type" "neon_store1_3reg<q>")]
+)
+
 (define_insn "neon_vst1<mode>"
   [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
 	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
index 575897fa422..5f820a6a496 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
@@ -60,8 +60,63 @@ void test_vst1_p16_x2 (poly16_t * ptr, poly16x4x2_t val)
     vst1_p16_x2 (ptr, val);
 }
 
+void test_vst1_u8_x3 (uint8_t * ptr, uint8x8x3_t val)
+{
+    vst1_u8_x3 (ptr, val);
+}
+
+void test_vst1_u16_x3 (uint16_t * ptr, uint16x4x3_t val)
+{
+    vst1_u16_x3 (ptr, val);
+}
+
+void test_vst1_u32_x3 (uint32_t * ptr, uint32x2x3_t val)
+{
+    vst1_u32_x3 (ptr, val);
+}
+
+void test_vst1_u64_x3 (uint64_t * ptr, uint64x1x3_t val)
+{
+    vst1_u64_x3 (ptr, val);
+}
+
+void test_vst1_s8_x3 (int8_t * ptr, int8x8x3_t val)
+{
+    vst1_s8_x3 (ptr, val);
+}
+
+void test_vst1_s16_x3 (int16_t * ptr, int16x4x3_t val)
+{
+    vst1_s16_x3 (ptr, val);
+}
+
+void test_vst1_s32_x3 (int32_t * ptr, int32x2x3_t val)
+{
+    vst1_s32_x3 (ptr, val);
+}
+
+void test_vst1_s64_x3 (int64_t * ptr, int64x1x3_t val)
+{
+    vst1_s64_x3 (ptr, val);
+}
+
+void test_vst1_f32_x3 (float32_t * ptr, float32x2x3_t val)
+{
+    vst1_f32_x3 (ptr, val);
+}
+
+void test_vst1_p8_x3 (poly8_t * ptr, poly8x8x3_t val)
+{
+    vst1_p8_x3 (ptr, val);
+}
+
+void test_vst1_p16_x3 (poly16_t * ptr, poly16x4x3_t val)
+{
+    vst1_p16_x3 (ptr, val);
+}
+
 
-/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
-/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
index 213fd20ee65..a3a00ead468 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
@@ -10,4 +10,9 @@ void test_vst1_bf16_x2 (bfloat16_t * ptr, bfloat16x4x2_t val)
     vst1_bf16_x2 (ptr, val);
 }
 
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
+void test_vst1_bf16_x3 (bfloat16_t * ptr, bfloat16x4x3_t val)
+{
+    vst1_bf16_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
index 523aec92db2..0a6863e24c6 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
@@ -10,4 +10,9 @@ void test_vst1_f16_x2 (float16_t * ptr, float16x4x2_t val)
     vst1_f16_x2 (ptr, val);
 }
 
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
+void test_vst1_f16_x3 (float16_t * ptr, float16x4x3_t val)
+{
+    vst1_f16_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
index f590ebd7b94..5dbd6049bc9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
@@ -10,4 +10,9 @@ void test_vst1_p64_x2 (poly64_t * ptr, poly64x1x2_t val)
     vst1_p64_x2 (ptr, val);
 }
 
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } }  */
\ No newline at end of file
+void test_vst1_p64_x3 (poly64_t * ptr, poly64x1x3_t val)
+{
+    vst1_p64_x3 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
\ No newline at end of file
-- 
2.25.1

[PATCH v2 3/3] [GCC] arm: vst1_types_x4 ACLE intrinsics

[Ezra.Sitorus]

From: Ezra Sitorus <ezra.sitorus@arm.com>

This patch is part of a series of patches implementing the _xN
variants of the vst1 intrinsic for the arm port. This patch adds the
_x4 variants of the vst1 intrinsic.

ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/

ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/

gcc/ChangeLog:
        * config/arm/arm_neon.h
        (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
        (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
        (vst1_f16_x4, vst1_f32_x4): New.
        (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
        (vst1_bf16_x4): New.
        * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
        * config/arm/neon.md (vst1_x4<mode>): New.

gcc/testsuite/ChangeLog:
        * gcc.target/arm/simd/vst1_base_xN_1.c: Add new test.
        * gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new test.
        * gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new test.
        * gcc.target/arm/simd/vst1_p64_xN_1.c: Add new test.
---
 gcc/config/arm/arm_neon.h                     | 114 ++++++++++++++++++
 gcc/config/arm/arm_neon_builtins.def          |   1 +
 gcc/config/arm/neon.md                        |  10 ++
 .../gcc.target/arm/simd/vst1_base_xN_1.c      |  62 +++++++++-
 .../gcc.target/arm/simd/vst1_bf16_xN_1.c      |   6 +-
 .../gcc.target/arm/simd/vst1_fp16_xN_1.c      |   7 +-
 .../gcc.target/arm/simd/vst1_p64_xN_1.c       |   7 +-
 7 files changed, 200 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index e76be3516d9..c9bdda39663 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11258,6 +11258,14 @@ vst1_p64_x3 (poly64_t * __a, poly64x1x3_t __b)
   __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p64_x4 (poly64_t * __a, poly64x1x4_t __b)
+{
+  union { poly64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 #pragma GCC pop_options
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11351,6 +11359,38 @@ vst1_s64_x3 (int64_t * __a, int64x1x3_t __b)
   __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s8_x4 (int8_t * __a, int8x8x4_t __b)
+{
+  union { int8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s16_x4 (int16_t * __a, int16x4x4_t __b)
+{
+  union { int16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s32_x4 (int32_t * __a, int32x2x4_t __b)
+{
+  union { int32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_s64_x4 (int64_t * __a, int64x1x4_t __b)
+{
+  union { int64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11403,6 +11443,24 @@ vst1_f32_x3 (float32_t * __a, float32x2x3_t __b)
   __builtin_neon_vst1_x3v2sf ((__builtin_neon_sf *) __a, __bu.__o);
 }
 
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f16_x4 (float16_t * __a, float16x4x4_t __b)
+{
+  union { float16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v4hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_f32_x4 (float32_t * __a, float32x2x4_t __b)
+{
+  union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v2sf ((__builtin_neon_sf *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1_u8 (uint8_t * __a, uint8x8_t __b)
@@ -11495,6 +11553,38 @@ vst1_u64_x3 (uint64_t * __a, uint64x1x3_t __b)
   __builtin_neon_vst1_x3di ((__builtin_neon_di *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u8_x4 (uint8_t * __a, uint8x8x4_t __b)
+{
+  union { uint8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u16_x4 (uint16_t * __a, uint16x4x4_t __b)
+{
+  union { uint16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u32_x4 (uint32_t * __a, uint32x2x4_t __b)
+{
+  union { uint32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v2si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_u64_x4 (uint64_t * __a, uint64x1x4_t __b)
+{
+  union { uint64x1x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1_p8 (poly8_t * __a, poly8x8_t __b)
@@ -11541,6 +11631,22 @@ vst1_p16_x3 (poly16_t * __a, poly16x4x3_t __b)
   __builtin_neon_vst1_x3v4hi ((__builtin_neon_hi *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p8_x4 (poly8_t * __a, poly8x8x4_t __b)
+{
+  union { poly8x8x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v8qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_p16_x4 (poly16_t * __a, poly16x4x4_t __b)
+{
+  union { poly16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v4hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
 #pragma GCC push_options
 #pragma GCC target ("fpu=crypto-neon-fp-armv8")
 __extension__ extern __inline void
@@ -20298,6 +20404,14 @@ vst1_bf16_x3 (bfloat16_t * __a, bfloat16x4x3_t __b)
   __builtin_neon_vst1_x3v4bf ((__builtin_neon_bf *) __a, __bu.__o);
 }
 
+__extension__ extern __inline void
+__attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
+vst1_bf16_x4 (bfloat16_t * __a, bfloat16x4x4_t __b)
+{
+  union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
+  __builtin_neon_vst1_x4v4bf ((__builtin_neon_bf *) __a, __bu.__o);
+}
+
 __extension__ extern __inline void
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
 vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index 8b104b1a700..a4056ec24d9 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -313,6 +313,7 @@ VAR14 (STORE1, vst1,
         v4bf, v8bf)
 VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
 VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
 VAR14 (STORE1LANE, vst1_lane,
        v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
 VAR13 (LOAD1, vld2,
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 5185434d6d9..dfbaf5a6dc6 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5145,6 +5145,16 @@ if (BYTES_BIG_ENDIAN)
   [(set_attr "type" "neon_store1_3reg<q>")]
 )
 
+(define_insn "neon_vst1_x4<mode>"
+  [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+        (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+                    (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+                   UNSPEC_VST1))]
+  "TARGET_NEON"
+  "vst1.<V_sz_elem>\t%h1, %A0"
+  [(set_attr "type" "neon_store1_4reg<q>")]
+)
+
 (define_insn "neon_vst1<mode>"
   [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
 	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
index 5f820a6a496..04ca6583552 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
@@ -115,8 +115,62 @@ void test_vst1_p16_x3 (poly16_t * ptr, poly16x4x3_t val)
     vst1_p16_x3 (ptr, val);
 }
 
+void test_vst1_u8_x4 (uint8_t * ptr, uint8x8x4_t val)
+{
+    vst1_u8_x4 (ptr, val);
+}
+
+void test_vst1_u16_x4 (uint16_t * ptr, uint16x4x4_t val)
+{
+    vst1_u16_x4 (ptr, val);
+}
+
+void test_vst1_u32_x4 (uint32_t * ptr, uint32x2x4_t val)
+{
+    vst1_u32_x4 (ptr, val);
+}
+
+void test_vst1_u64_x4 (uint64_t * ptr, uint64x1x4_t val)
+{
+    vst1_u64_x4 (ptr, val);
+}
+
+void test_vst1_s8_x4 (int8_t * ptr, int8x8x4_t val)
+{
+    vst1_s8_x4 (ptr, val);
+}
+
+void test_vst1_s16_x4 (int16_t * ptr, int16x4x4_t val)
+{
+    vst1_s16_x4 (ptr, val);
+}
+
+void test_vst1_s32_x4 (int32_t * ptr, int32x2x4_t val)
+{
+    vst1_s32_x4 (ptr, val);
+}
+
+void test_vst1_s64_x4 (int64_t * ptr, int64x1x4_t val)
+{
+    vst1_s64_x4 (ptr, val);
+}
+
+void test_vst1_f32_x4 (float32_t * ptr, float32x2x4_t val)
+{
+    vst1_f32_x4 (ptr, val);
+}
+
+void test_vst1_p8_x4 (poly8_t * ptr, poly8x8x4_t val)
+{
+    vst1_p8_x4 (ptr, val);
+}
+
+void test_vst1_p16_x4 (poly16_t * ptr, poly16x4x4_t val)
+{
+    vst1_p16_x4 (ptr, val);
+}
 
-/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
-/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } }  */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } }  */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } }  */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } }  */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 6 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
index a3a00ead468..d919c7d060d 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
@@ -15,4 +15,8 @@ void test_vst1_bf16_x3 (bfloat16_t * ptr, bfloat16x4x3_t val)
     vst1_bf16_x3 (ptr, val);
 }
 
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } }  */
+void test_vst1_bf16_x4 (bfloat16_t * ptr, bfloat16x4x4_t val)
+{
+    vst1_bf16_x4 (ptr, val);
+}
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
index 0a6863e24c6..3d1d1eb7ad1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
@@ -15,4 +15,9 @@ void test_vst1_f16_x3 (float16_t * ptr, float16x4x3_t val)
     vst1_f16_x3 (ptr, val);
 }
 
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } }  */
+void test_vst1_f16_x4 (float16_t * ptr, float16x4x4_t val)
+{
+    vst1_f16_x4 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
index 5dbd6049bc9..62912143481 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
@@ -15,4 +15,9 @@ void test_vst1_p64_x3 (poly64_t * ptr, poly64x1x3_t val)
     vst1_p64_x3 (ptr, val);
 }
 
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
\ No newline at end of file
+void test_vst1_p64_x4 (poly64_t * ptr, poly64x1x4_t val)
+{
+    vst1_p64_x4 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 3 } }  */
\ No newline at end of file
-- 
2.25.1

Re: [PATCH v2 0/3] [GCC] arm: vst1_types_xN ACLE intrinsics

[Richard Earnshaw]

Pushed, thanks.

R.


On 07/12/2023 15:28, Ezra.Sitorus@arm.com wrote:
> Add xN variants of vst1_types intrinsic.
> 
> 

Re: [PATCH v2 0/3] [GCC] arm: vst1_types_xN ACLE intrinsics

[Richard Earnshaw]

Sorry, Ezra, but I've taken the decision to back out all 4 of the patch 
series' related to this.  I think the problems that the CI has shown up 
need to be addressed first, and the fixes don't seem to be entirely trivial.

R.

On 07/12/2023 16:44, Richard Earnshaw wrote:
> Pushed, thanks.
> 
> R.
> 
> 
> On 07/12/2023 15:28, Ezra.Sitorus@arm.com wrote:
>> Add xN variants of vst1_types intrinsic.
>>
>>