* [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case
@ 2024-05-08 7:36 Christoph Müllner
2024-05-08 7:36 ` [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 Christoph Müllner
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Christoph Müllner @ 2024-05-08 7:36 UTC (permalink / raw)
To: gcc-patches, Kito Cheng, Jim Wilson, Palmer Dabbelt,
Andrew Waterman, Philipp Tomsich, Jeff Law, Vineet Gupta
Cc: Christoph Müllner
We already optimize a sign-extension of a right-shift by 31 in
<optab>si3_extend. Let's add a test for that (similar to
zero-extend-1.c).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sign-extend-1.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/testsuite/gcc.target/riscv/sign-extend-1.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sign-extend-1.c
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
new file mode 100644
index 00000000000..e9056ec0d42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+signed long
+foo1 (int i)
+{
+ return i >> 31;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],31" } } */
+
+/* { dg-final { scan-assembler-not "srai\t" } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "srliw\t" } } */
--
2.44.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2
2024-05-08 7:36 [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Christoph Müllner
@ 2024-05-08 7:36 ` Christoph Müllner
2024-05-08 13:40 ` Jeff Law
2024-05-08 7:36 ` [PATCH v2 3/4] RISC-V: Add zero_extract support for rv64gc Christoph Müllner
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Christoph Müllner @ 2024-05-08 7:36 UTC (permalink / raw)
To: gcc-patches, Kito Cheng, Jim Wilson, Palmer Dabbelt,
Andrew Waterman, Philipp Tomsich, Jeff Law, Vineet Gupta
Cc: Christoph Müllner
The pattern lshrsi3_zero_extend_2 extracts the MSB bits of the lower
32-bit word and zero-extends it back to DImode.
This is realized using srliw, which operates on 32-bit registers.
The same optimziation can be applied to sign-extensions when emitting
a sraiw instead of the srliw.
Given these two optimizations are so similar, this patch simply
converts the existing one to also cover the sign-extension case as well.
gcc/ChangeLog:
* config/riscv/iterators.md (sraiw): New code iterator 'any_extract'.
New code attribute 'extract_sidi_shift'.
* config/riscv/riscv.md (*lshrsi3_zero_extend_2): Rename to...
(*lshrsi3_extend_2):...this and add support for sign-extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sign-extend-1.c: Test sraiw 24 and sraiw 16.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/iterators.md | 6 ++++++
gcc/config/riscv/riscv.md | 9 +++++----
gcc/testsuite/gcc.target/riscv/sign-extend-1.c | 14 ++++++++++++++
3 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 32e1b140305..c5ca01f382a 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -150,6 +150,12 @@ (define_mode_attr slot12_offset [(SI "-52") (DI "-104")])
;; to use the same template.
(define_code_iterator any_extend [sign_extend zero_extend])
+;; These code iterators allow unsigned and signed extraction to be generated
+;; from the same template.
+(define_code_iterator any_extract [sign_extract zero_extract])
+(define_code_attr extract_sidi_shift [(sign_extract "sraiw")
+ (zero_extract "srliw")])
+
;; This code iterator allows the two right shift instructions to be
;; generated from the same template.
(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 24558682eb8..b7fc13e4e61 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2765,16 +2765,17 @@ (define_insn "*lshrsi3_zero_extend_1"
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
-;; Canonical form for a zero-extend of a logical right shift.
-(define_insn "*lshrsi3_zero_extend_2"
+;; Canonical form for a sign/zero-extend of a logical right shift.
+;; Special case: extract MSB bits of lower 32-bit word
+(define_insn "*lshrsi3_extend_2"
[(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extract:DI (match_operand:DI 1 "register_operand" " r")
+ (any_extract:DI (match_operand:DI 1 "register_operand" " r")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")))]
"(TARGET_64BIT && (INTVAL (operands[3]) > 0)
&& (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))"
{
- return "srliw\t%0,%1,%3";
+ return "<extract_sidi_shift>\t%0,%1,%3";
}
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
index e9056ec0d42..d8c18dd1aaa 100644
--- a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
@@ -9,6 +9,20 @@ foo1 (int i)
}
/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],31" } } */
+signed char
+sub2 (long i)
+{
+ return i >> 24;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],24" } } */
+
+signed short
+sub3 (long i)
+{
+ return i >> 16;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],16" } } */
+
/* { dg-final { scan-assembler-not "srai\t" } } */
/* { dg-final { scan-assembler-not "srli\t" } } */
/* { dg-final { scan-assembler-not "srliw\t" } } */
--
2.44.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/4] RISC-V: Add zero_extract support for rv64gc
2024-05-08 7:36 [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Christoph Müllner
2024-05-08 7:36 ` [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 Christoph Müllner
@ 2024-05-08 7:36 ` Christoph Müllner
2024-05-08 13:46 ` Jeff Law
2024-05-08 7:36 ` [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4 Christoph Müllner
2024-05-08 13:38 ` [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Jeff Law
3 siblings, 1 reply; 9+ messages in thread
From: Christoph Müllner @ 2024-05-08 7:36 UTC (permalink / raw)
To: gcc-patches, Kito Cheng, Jim Wilson, Palmer Dabbelt,
Andrew Waterman, Philipp Tomsich, Jeff Law, Vineet Gupta
Cc: Christoph Müllner
The combiner attempts to optimize a zero-extension of a logical right shift
using zero_extract. We already utilize this optimization for those cases
that result in a single instructions. Let's add a insn_and_split
pattern that also matches the generic case, where we can emit an
optimized sequence of a slli/srli.
Tested with SPEC CPU 2017 (rv64gc).
PR 111501
gcc/ChangeLog:
* config/riscv/riscv.md (*lshr<GPR:mode>3_zero_extend_4): New
pattern for zero-extraction.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/extend-shift-helpers.h: New test.
* gcc.target/riscv/pr111501.c: New test.
* gcc.target/riscv/zero-extend-rshift-32.c: New test.
* gcc.target/riscv/zero-extend-rshift-64.c: New test.
* gcc.target/riscv/zero-extend-rshift.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/riscv.md | 30 +++++
.../gcc.target/riscv/extend-shift-helpers.h | 26 ++++
gcc/testsuite/gcc.target/riscv/pr111501.c | 21 ++++
.../gcc.target/riscv/zero-extend-rshift-32.c | 13 ++
.../gcc.target/riscv/zero-extend-rshift-64.c | 17 +++
.../gcc.target/riscv/zero-extend-rshift.c | 115 ++++++++++++++++++
6 files changed, 222 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
create mode 100644 gcc/testsuite/gcc.target/riscv/pr111501.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b7fc13e4e61..58bf7712277 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2793,6 +2793,36 @@ (define_insn "*lshrsi3_zero_extend_3"
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
+;; Canonical form for a zero-extend of a logical right shift.
+;; Special cases are handled above.
+;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb)
+(define_insn_and_split "*lshr<GPR:mode>3_zero_extend_4"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (zero_extract:GPR
+ (match_operand:GPR 1 "register_operand" " r")
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))
+ (clobber (match_scratch:GPR 4 "=&r"))]
+ "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1))
+ && !TARGET_XTHEADBB"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 4)
+ (ashift:GPR (match_dup 1) (match_dup 2)))
+ (set (match_dup 0)
+ (lshiftrt:GPR (match_dup 4) (match_dup 3)))]
+{
+ int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant ();
+ int sizebits = INTVAL (operands[2]);
+ int startbits = INTVAL (operands[3]);
+ int lshamt = regbits - sizebits - startbits;
+ int rshamt = lshamt + startbits;
+ operands[2] = GEN_INT (lshamt);
+ operands[3] = GEN_INT (rshamt);
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<GPR:MODE>")])
+
;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into
;; two logical shifts. Otherwise it requires 3 instructions: lui,
;; xor/addi/srli, and.
diff --git a/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h b/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
new file mode 100644
index 00000000000..4853fe490d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
@@ -0,0 +1,26 @@
+#ifndef EXTEND_SHIFT_HELPERS_H
+#define EXTEND_SHIFT_HELPERS_H
+
+#define RT_EXT_CT_RSHIFT_N_AT(RTS,RT,CTS,CT,N,ATS,AT) \
+RTS RT \
+RTS##_##RT##_ext_##CTS##_##CT##_rshift_##N##_##ATS##_##AT(ATS AT v) \
+{ \
+ return (CTS CT)(v >> N); \
+}
+
+#define ULONG_EXT_USHORT_RSHIFT_N_ULONG(N) \
+ RT_EXT_CT_RSHIFT_N_AT(unsigned,long,unsigned,short,N,unsigned,long)
+
+#define ULONG_EXT_UINT_RSHIFT_N_ULONG(N) \
+ RT_EXT_CT_RSHIFT_N_AT(unsigned,long,unsigned,int,N,unsigned,long)
+
+#define UINT_EXT_USHORT_RSHIFT_N_UINT(N) \
+ RT_EXT_CT_RSHIFT_N_AT(unsigned,int,unsigned,short,N,unsigned,int)
+
+#define UINT_EXT_USHORT_RSHIFT_N_ULONG(N) \
+ RT_EXT_CT_RSHIFT_N_AT(unsigned,int,unsigned,short,N,unsigned,long)
+
+#define ULONG_EXT_USHORT_RSHIFT_N_UINT(N) \
+ RT_EXT_CT_RSHIFT_N_AT(unsigned,long,unsigned,short,N,unsigned,int)
+
+#endif /* EXTEND_SHIFT_HELPERS_H */
diff --git a/gcc/testsuite/gcc.target/riscv/pr111501.c b/gcc/testsuite/gcc.target/riscv/pr111501.c
new file mode 100644
index 00000000000..db48c34ce9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr111501.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-options "-march=rv64gc" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+unsigned int
+do_shift(unsigned long csum)
+{
+ return (unsigned short)(csum >> 32);
+}
+
+unsigned int
+do_shift2(unsigned long csum)
+{
+ return (csum << 16) >> 48;
+}
+
+/* { dg-final { scan-assembler-times "slli\t" 2 } } */
+/* { dg-final { scan-assembler-times "srli\t" 2 } } */
+/* { dg-final { scan-assembler-times "slli\ta\[0-9\],a\[0-9\],16" 2 } } */
+/* { dg-final { scan-assembler-times "srli\ta\[0-9\],a\[0-9\],48" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c
new file mode 100644
index 00000000000..c995a6e0dfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-32.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv32 } */
+/* { dg-options "-march=rv32gc" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+#include "extend-shift-helpers.h"
+
+/* { dg-final { scan-assembler "slli\ta\[0-9\],a\[0-9\],2" } } */
+/* { dg-final { scan-assembler "srli\ta\[0-9\],a\[0-9\],16" } } */
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(14)
+
+/* { dg-final { scan-assembler "srli\ta\[0-9\],a\[0-9\],23" } } */
+ULONG_EXT_UINT_RSHIFT_N_ULONG(23)
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c
new file mode 100644
index 00000000000..847fadf660f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift-64.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-options "-march=rv64gc" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+#include "extend-shift-helpers.h"
+
+/* { dg-final { scan-assembler "slli\ta\[0-9\],a\[0-9\],34" } } */
+/* { dg-final { scan-assembler "srli\ta\[0-9\],a\[0-9\],48" } } */
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(14)
+
+/* { dg-final { scan-assembler "srli\ta\[0-9\],a\[0-9\],51" } } */
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(51)
+
+/* { dg-final { scan-assembler "slli\ta\[0-9\],a\[0-9\],9" } } */
+/* { dg-final { scan-assembler "srli\ta\[0-9\],a\[0-9\],32" } } */
+ULONG_EXT_UINT_RSHIFT_N_ULONG(23)
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c
new file mode 100644
index 00000000000..8b27b0eb9ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-rshift.c
@@ -0,0 +1,115 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+// Tests for merging rshifts into zero-extensions.
+// u8-casts are skipped as they can be done with one instruction (andi 0xff).
+
+#include "extend-shift-helpers.h"
+
+// Below "slli (16-N); srli 16" for rv32
+// Below "slli ((32+16)-N); srli (32+16)" for rv64
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(1)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(7)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(8)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(9)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(15)
+// Below "srli 16" for rv32
+// Below "srliw 16" for rv64
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(16)
+// Below "srli N" for rv32
+// Below "slli ((32+16)-N); srli (32+16)" for rv64
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(17)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(23)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(24)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(25)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(31)
+// Below compiler warning for rv32
+#if __riscv_xlen == 64
+// Below "slli ((32+16)-N); srli (32+16)" for rv64
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(32)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(33)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(39)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(40)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(41)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(47)
+// Below "srli N" for rv64
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(48)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(49)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(55)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(56)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(57)
+ULONG_EXT_USHORT_RSHIFT_N_ULONG(63)
+#endif /* __riscv_xlen == 64 */
+
+
+
+// Below "srli N" for rv32
+// Below "slli (32-N); srli 32" for rv64
+ULONG_EXT_UINT_RSHIFT_N_ULONG(1)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(7)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(8)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(9)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(15)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(16)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(17)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(23)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(24)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(25)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(31)
+// Below compiler warning for rv32
+#if __riscv_xlen == 64
+// Below "srli N" for rv64
+ULONG_EXT_UINT_RSHIFT_N_ULONG(32)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(33)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(39)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(40)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(41)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(47)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(48)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(49)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(55)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(56)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(57)
+ULONG_EXT_UINT_RSHIFT_N_ULONG(63)
+#endif /* __riscv_xlen == 64 */
+
+
+
+#if __riscv_xlen == 64
+// Below "slli ((32+16)-N); srli (32+16)" for rv64
+UINT_EXT_USHORT_RSHIFT_N_UINT(1)
+UINT_EXT_USHORT_RSHIFT_N_UINT(7)
+UINT_EXT_USHORT_RSHIFT_N_UINT(8)
+UINT_EXT_USHORT_RSHIFT_N_UINT(9)
+UINT_EXT_USHORT_RSHIFT_N_UINT(15)
+// Below "srliw N" for rv64
+UINT_EXT_USHORT_RSHIFT_N_UINT(16)
+UINT_EXT_USHORT_RSHIFT_N_UINT(17)
+UINT_EXT_USHORT_RSHIFT_N_UINT(23)
+UINT_EXT_USHORT_RSHIFT_N_UINT(24)
+UINT_EXT_USHORT_RSHIFT_N_UINT(25)
+UINT_EXT_USHORT_RSHIFT_N_UINT(31)
+#endif /* __riscv_xlen == 64 */
+
+
+
+// Below "slli (16-N); srli 16" for rv32
+// Below "slli ((32+16)-N); srli (32+16)" for rv64
+UINT_EXT_USHORT_RSHIFT_N_ULONG(9)
+UINT_EXT_USHORT_RSHIFT_N_ULONG(15)
+
+
+
+// Below "slli (16-N); srli 16" for rv32
+// Below "slli ((32+16)-N); srli (32+16)" for rv64
+ULONG_EXT_USHORT_RSHIFT_N_UINT(9)
+ULONG_EXT_USHORT_RSHIFT_N_UINT(15)
+
+/* { dg-final { scan-assembler-times "slli\t" 9 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times "srli\t" 26 { target { rv32 } } } } */
+
+/* { dg-final { scan-assembler-times "slli\t" 36 { target { rv64 } } } } */
+/* { dg-final { scan-assembler-times "srli\t" 54 { target { rv64 } } } } */
+/* { dg-final { scan-assembler-times "srliw\t" 7 { target { rv64 } } } } */
--
2.44.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4
2024-05-08 7:36 [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Christoph Müllner
2024-05-08 7:36 ` [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 Christoph Müllner
2024-05-08 7:36 ` [PATCH v2 3/4] RISC-V: Add zero_extract support for rv64gc Christoph Müllner
@ 2024-05-08 7:36 ` Christoph Müllner
2024-05-08 13:48 ` Jeff Law
2024-05-08 13:38 ` [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Jeff Law
3 siblings, 1 reply; 9+ messages in thread
From: Christoph Müllner @ 2024-05-08 7:36 UTC (permalink / raw)
To: gcc-patches, Kito Cheng, Jim Wilson, Palmer Dabbelt,
Andrew Waterman, Philipp Tomsich, Jeff Law, Vineet Gupta
Cc: Christoph Müllner
The lshr<GPR:mode>3_zero_extend_4 pattern targets bit extraction
with zero-extension. This pattern represents the canonical form
of zero-extensions of a logical right shift.
The same optimization can be applied to sign-extensions.
Given the two optimizations are so similar, this patch converts
the existing one to also cover the sign-extension case as well.
gcc/ChangeLog:
* config/riscv/iterators.md (ashiftrt): New code attribute
'extract_shift' and adding extractions to optab.
* config/riscv/riscv.md (*lshr<GPR:mode>3_zero_extend_4): Rename to...
(*<any_extract:optab><GPR:mode>3):...this and add support for
sign-extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/extend-shift-helpers.h: Add helpers for
sign-extension.
* gcc.target/riscv/sign-extend-rshift-32.c: New test.
* gcc.target/riscv/sign-extend-rshift-64.c: New test.
* gcc.target/riscv/sign-extend-rshift.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/iterators.md | 4 +
gcc/config/riscv/riscv.md | 25 ++--
.../gcc.target/riscv/extend-shift-helpers.h | 20 +++
.../gcc.target/riscv/sign-extend-rshift-32.c | 17 +++
.../gcc.target/riscv/sign-extend-rshift-64.c | 17 +++
.../gcc.target/riscv/sign-extend-rshift.c | 123 ++++++++++++++++++
6 files changed, 198 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/sign-extend-rshift-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sign-extend-rshift-64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sign-extend-rshift.c
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index c5ca01f382a..8a9d1986b4a 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -155,6 +155,8 @@ (define_code_iterator any_extend [sign_extend zero_extend])
(define_code_iterator any_extract [sign_extract zero_extract])
(define_code_attr extract_sidi_shift [(sign_extract "sraiw")
(zero_extract "srliw")])
+(define_code_attr extract_shift [(sign_extract "ashiftrt")
+ (zero_extract "lshiftrt")])
;; This code iterator allows the two right shift instructions to be
;; generated from the same template.
@@ -261,6 +263,8 @@ (define_code_attr optab [(ashift "ashl")
(us_minus "ussub")
(sign_extend "extend")
(zero_extend "zero_extend")
+ (sign_extract "extract")
+ (zero_extract "zero_extract")
(fix "fix_trunc")
(unsigned_fix "fixuns_trunc")])
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 58bf7712277..620a1b3bd32 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2793,24 +2793,33 @@ (define_insn "*lshrsi3_zero_extend_3"
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
-;; Canonical form for a zero-extend of a logical right shift.
-;; Special cases are handled above.
-;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb)
-(define_insn_and_split "*lshr<GPR:mode>3_zero_extend_4"
+;; Canonical form for a extend of a logical shift right (sign/zero extraction).
+;; Special cases, that are ignored (handled elsewhere):
+;; * Single-bit extraction (Zbs/XTheadBs)
+;; * Single-bit extraction (Zicondops/XVentanaCondops)
+;; * Single-bit extraction (SFB)
+;; * Extraction instruction th.ext(u) (XTheadBb)
+;; * lshrsi3_extend_2 (see above)
+(define_insn_and_split "*<any_extract:optab><GPR:mode>3"
[(set (match_operand:GPR 0 "register_operand" "=r")
- (zero_extract:GPR
+ (any_extract:GPR
(match_operand:GPR 1 "register_operand" " r")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")))
(clobber (match_scratch:GPR 4 "=&r"))]
- "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1))
- && !TARGET_XTHEADBB"
+ "!((TARGET_ZBS || TARGET_XTHEADBS || TARGET_ZICOND
+ || TARGET_XVENTANACONDOPS || TARGET_SFB_ALU)
+ && (INTVAL (operands[2]) == 1))
+ && !TARGET_XTHEADBB
+ && !(TARGET_64BIT
+ && (INTVAL (operands[3]) > 0)
+ && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))"
"#"
"&& reload_completed"
[(set (match_dup 4)
(ashift:GPR (match_dup 1) (match_dup 2)))
(set (match_dup 0)
- (lshiftrt:GPR (match_dup 4) (match_dup 3)))]
+ (<extract_shift>:GPR (match_dup 4) (match_dup 3)))]
{
int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant ();
int sizebits = INTVAL (operands[2]);
diff --git a/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h b/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
index 4853fe490d8..720672de242 100644
--- a/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
+++ b/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
@@ -8,6 +8,26 @@ RTS##_##RT##_ext_##CTS##_##CT##_rshift_##N##_##ATS##_##AT(ATS AT v) \
return (CTS CT)(v >> N); \
}
+#define SLONG_EXT_SCHAR_RSHIFT_N_SLONG(N) \
+ RT_EXT_CT_RSHIFT_N_AT(signed,long,signed,char,N,signed,long)
+
+#define SLONG_EXT_SSHORT_RSHIFT_N_SLONG(N) \
+ RT_EXT_CT_RSHIFT_N_AT(signed,long,signed,short,N,signed,long)
+
+#define SLONG_EXT_SINT_RSHIFT_N_SLONG(N) \
+ RT_EXT_CT_RSHIFT_N_AT(signed,long,signed,int,N,signed,long)
+
+#define SINT_EXT_SSHORT_RSHIFT_N_SINT(N) \
+ RT_EXT_CT_RSHIFT_N_AT(signed,int,signed,short,N,signed,int)
+
+#define SINT_EXT_SSHORT_RSHIFT_N_SLONG(N) \
+ RT_EXT_CT_RSHIFT_N_AT(signed,int,signed,short,N,signed,long)
+
+#define SLONG_EXT_SSHORT_RSHIFT_N_SINT(N) \
+ RT_EXT_CT_RSHIFT_N_AT(signed,long,signed,short,N,signed,int)
+
+
+
#define ULONG_EXT_USHORT_RSHIFT_N_ULONG(N) \
RT_EXT_CT_RSHIFT_N_AT(unsigned,long,unsigned,short,N,unsigned,long)
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-rshift-32.c b/gcc/testsuite/gcc.target/riscv/sign-extend-rshift-32.c
new file mode 100644
index 00000000000..895dd18c8f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-rshift-32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv32 } */
+/* { dg-options "-march=rv32gc" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+#include "extend-shift-helpers.h"
+
+/* { dg-final { scan-assembler "slli\ta\[0-9\],a\[0-9\],15" } } */
+/* { dg-final { scan-assembler "srai\ta\[0-9\],a\[0-9\],24" } } */
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(9)
+
+/* { dg-final { scan-assembler "slli\ta\[0-9\],a\[0-9\],2" } } */
+/* { dg-final { scan-assembler "srai\ta\[0-9\],a\[0-9\],16" } } */
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(14)
+
+/* { dg-final { scan-assembler "srai\ta\[0-9\],a\[0-9\],23" } } */
+SLONG_EXT_SINT_RSHIFT_N_SLONG(23)
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-rshift-64.c b/gcc/testsuite/gcc.target/riscv/sign-extend-rshift-64.c
new file mode 100644
index 00000000000..13d18f73eab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-rshift-64.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-options "-march=rv64gc" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+#include "extend-shift-helpers.h"
+
+/* { dg-final { scan-assembler "slli\ta\[0-9\],a\[0-9\],47" } } */
+/* { dg-final { scan-assembler "srai\ta\[0-9\],a\[0-9\],56" } } */
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(9)
+
+/* { dg-final { scan-assembler "slli\ta\[0-9\],a\[0-9\],34" } } */
+/* { dg-final { scan-assembler "srai\ta\[0-9\],a\[0-9\],48" } } */
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(14)
+
+/* { dg-final { scan-assembler "srai\ta\[0-9\],a\[0-9\],51" } } */
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(51)
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-rshift.c b/gcc/testsuite/gcc.target/riscv/sign-extend-rshift.c
new file mode 100644
index 00000000000..90a44eadb59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-rshift.c
@@ -0,0 +1,123 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Os" "-Og" "-Oz" "-flto" } } */
+
+// Tests for merging rshifts into sero-extensions.
+// s32-casts are skipped as they can be done with one instruction (sext.w).
+
+#include "extend-shift-helpers.h"
+
+// Below "slli (24-N); srai 24" for rv32
+// Below "slli ((32+24)-N); srai (32+24)" for rv64
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(1)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(7)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(8)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(9)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(15)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(16)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(17)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(23)
+// Below "srai N" for rv32
+// Below "sraiw N" for rv64
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(24)
+// Below "srai N" for rv32
+// Below "slli ((32+24)-N); srai (32+24)" for rv64
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(25)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(31)
+// Below compiler warning for rv32
+#if __riscv_xlen == 64
+// Below "slli ((32+24)-N); srai (32+24)" for rv64
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(32)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(33)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(39)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(40)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(41)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(47)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(48)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(49)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(55)
+// Below "srai N" for rv64
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(56)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(57)
+SLONG_EXT_SCHAR_RSHIFT_N_SLONG(63)
+#endif /* __riscv_xlen == 64 */
+
+
+
+// Below "slli (16-N); srai 16" for rv32
+// Below "slli ((32+16)-N); srai (32+16)" for rv64
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(1)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(7)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(8)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(9)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(15)
+// Below "srai 16" for rv32
+// Below "sraiw 16" for rv64
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(16)
+// Below "srai N" for rv32
+// Below "slli ((32+16)-N); srai (32+16)" for rv64
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(17)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(23)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(24)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(25)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(31)
+// Below compiler warning for rv32
+#if __riscv_xlen == 64
+// Below "slli ((32+16)-N); srai (32+16)" for rv64
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(32)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(33)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(39)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(40)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(41)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(47)
+// Below "srai N" for rv64
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(48)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(49)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(55)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(56)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(57)
+SLONG_EXT_SSHORT_RSHIFT_N_SLONG(63)
+#endif /* __riscv_xlen == 64 */
+
+
+
+#if __riscv_xlen == 64
+// Below "slli ((32+16)-N); srai (32+16)" for rv64
+// or "slli (16-N); sraiw 16" for rv64
+SINT_EXT_SSHORT_RSHIFT_N_SINT(1)
+SINT_EXT_SSHORT_RSHIFT_N_SINT(7)
+SINT_EXT_SSHORT_RSHIFT_N_SINT(8)
+SINT_EXT_SSHORT_RSHIFT_N_SINT(9)
+SINT_EXT_SSHORT_RSHIFT_N_SINT(15)
+// Below "srai N" for rv64
+SINT_EXT_SSHORT_RSHIFT_N_SINT(16)
+SINT_EXT_SSHORT_RSHIFT_N_SINT(17)
+SINT_EXT_SSHORT_RSHIFT_N_SINT(23)
+SINT_EXT_SSHORT_RSHIFT_N_SINT(24)
+SINT_EXT_SSHORT_RSHIFT_N_SINT(25)
+// Below "sraiw N" for rv64
+SINT_EXT_SSHORT_RSHIFT_N_SINT(31)
+#endif /* __riscv_xlen == 64 */
+
+
+
+// Below "slli (16-N); srai 16" for rv32
+// Below "slli ((32+16)-N); srai (32+16)" for rv64
+// or "slli (16-N); sraiw 16" for rv64
+SINT_EXT_SSHORT_RSHIFT_N_SLONG(9)
+SINT_EXT_SSHORT_RSHIFT_N_SLONG(15)
+
+
+
+// Below "slli (16-N); srai 16" for rv32
+// Below "slli ((32+16)-N); srai (32+16)" for rv64
+SLONG_EXT_SSHORT_RSHIFT_N_SINT(9)
+SLONG_EXT_SSHORT_RSHIFT_N_SINT(15)
+
+/* { dg-final { scan-assembler-times "slli\t" 17 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times "srai\t" 26 { target { rv32 } } } } */
+
+/* { dg-final { scan-assembler-times "slli\t" 44 { target { rv64 } } } } */
+/* { dg-final { scan-assembler-times "srai\t" 51 { target { rv64 } } } } */
+/* { dg-final { scan-assembler-times "sraiw\t" 10 { target { rv64 } } } } */
--
2.44.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case
2024-05-08 7:36 [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Christoph Müllner
` (2 preceding siblings ...)
2024-05-08 7:36 ` [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4 Christoph Müllner
@ 2024-05-08 13:38 ` Jeff Law
3 siblings, 0 replies; 9+ messages in thread
From: Jeff Law @ 2024-05-08 13:38 UTC (permalink / raw)
To: Christoph Müllner, gcc-patches, Kito Cheng, Jim Wilson,
Palmer Dabbelt, Andrew Waterman, Philipp Tomsich, Vineet Gupta
On 5/8/24 1:36 AM, Christoph Müllner wrote:
> We already optimize a sign-extension of a right-shift by 31 in
> <optab>si3_extend. Let's add a test for that (similar to
> zero-extend-1.c).
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sign-extend-1.c: New test.
OK
jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2
2024-05-08 7:36 ` [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 Christoph Müllner
@ 2024-05-08 13:40 ` Jeff Law
0 siblings, 0 replies; 9+ messages in thread
From: Jeff Law @ 2024-05-08 13:40 UTC (permalink / raw)
To: Christoph Müllner, gcc-patches, Kito Cheng, Jim Wilson,
Palmer Dabbelt, Andrew Waterman, Philipp Tomsich, Vineet Gupta
On 5/8/24 1:36 AM, Christoph Müllner wrote:
> The pattern lshrsi3_zero_extend_2 extracts the MSB bits of the lower
> 32-bit word and zero-extends it back to DImode.
> This is realized using srliw, which operates on 32-bit registers.
>
> The same optimziation can be applied to sign-extensions when emitting
> a sraiw instead of the srliw.
>
> Given these two optimizations are so similar, this patch simply
> converts the existing one to also cover the sign-extension case as well.
>
> gcc/ChangeLog:
>
> * config/riscv/iterators.md (sraiw): New code iterator 'any_extract'.
> New code attribute 'extract_sidi_shift'.
> * config/riscv/riscv.md (*lshrsi3_zero_extend_2): Rename to...
> (*lshrsi3_extend_2):...this and add support for sign-extensions.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sign-extend-1.c: Test sraiw 24 and sraiw 16.
OK
jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 3/4] RISC-V: Add zero_extract support for rv64gc
2024-05-08 7:36 ` [PATCH v2 3/4] RISC-V: Add zero_extract support for rv64gc Christoph Müllner
@ 2024-05-08 13:46 ` Jeff Law
0 siblings, 0 replies; 9+ messages in thread
From: Jeff Law @ 2024-05-08 13:46 UTC (permalink / raw)
To: Christoph Müllner, gcc-patches, Kito Cheng, Jim Wilson,
Palmer Dabbelt, Andrew Waterman, Philipp Tomsich, Vineet Gupta
On 5/8/24 1:36 AM, Christoph Müllner wrote:
> The combiner attempts to optimize a zero-extension of a logical right shift
> using zero_extract. We already utilize this optimization for those cases
> that result in a single instructions. Let's add a insn_and_split
> pattern that also matches the generic case, where we can emit an
> optimized sequence of a slli/srli.
>
> Tested with SPEC CPU 2017 (rv64gc).
>
> PR 111501
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md (*lshr<GPR:mode>3_zero_extend_4): New
> pattern for zero-extraction.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/extend-shift-helpers.h: New test.
> * gcc.target/riscv/pr111501.c: New test.
> * gcc.target/riscv/zero-extend-rshift-32.c: New test.
> * gcc.target/riscv/zero-extend-rshift-64.c: New test.
> * gcc.target/riscv/zero-extend-rshift.c: New test.
Doesn't your new pattern still match this one:
> ;; Canonical form for a zero-extend of a logical right shift.
> (define_insn "*lshrsi3_zero_extend_2" [(set (match_operand:DI 0 "register_operand" "=r")
> (zero_extract:DI (match_operand:DI 1 "register_operand" " r")
> (match_operand 2 "const_int_operand")
> (match_operand 3 "const_int_operand")))]
> "(TARGET_64BIT && (INTVAL (operands[3]) > 0)
> && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))"
> {
> return "srliw\t%0,%1,%3";
> }
> [(set_attr "type" "shift")
> (set_attr "mode" "SI")])
Meaning that we'll start generating shift-pairs for this special case
rather than using srliw directly. I'm pretty sure Lyut and I stumbled
over this exact problem when evaluating his effort in this space.
?
Jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4
2024-05-08 7:36 ` [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4 Christoph Müllner
@ 2024-05-08 13:48 ` Jeff Law
2024-05-08 14:05 ` Christoph Müllner
0 siblings, 1 reply; 9+ messages in thread
From: Jeff Law @ 2024-05-08 13:48 UTC (permalink / raw)
To: Christoph Müllner, gcc-patches, Kito Cheng, Jim Wilson,
Palmer Dabbelt, Andrew Waterman, Philipp Tomsich, Vineet Gupta
On 5/8/24 1:36 AM, Christoph Müllner wrote:
> The lshr<GPR:mode>3_zero_extend_4 pattern targets bit extraction
> with zero-extension. This pattern represents the canonical form
> of zero-extensions of a logical right shift.
>
> The same optimization can be applied to sign-extensions.
> Given the two optimizations are so similar, this patch converts
> the existing one to also cover the sign-extension case as well.
>
> gcc/ChangeLog:
>
> * config/riscv/iterators.md (ashiftrt): New code attribute
> 'extract_shift' and adding extractions to optab.
> * config/riscv/riscv.md (*lshr<GPR:mode>3_zero_extend_4): Rename to...
> (*<any_extract:optab><GPR:mode>3):...this and add support for
> sign-extensions.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/extend-shift-helpers.h: Add helpers for
> sign-extension.
> * gcc.target/riscv/sign-extend-rshift-32.c: New test.
> * gcc.target/riscv/sign-extend-rshift-64.c: New test.
> * gcc.target/riscv/sign-extend-rshift.c: New test.
Oh, I see, you handled the special case with this patch. Ignore my
comment on 3/4. 3/4 is fine, as is this patch.
Thanks!
jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4
2024-05-08 13:48 ` Jeff Law
@ 2024-05-08 14:05 ` Christoph Müllner
0 siblings, 0 replies; 9+ messages in thread
From: Christoph Müllner @ 2024-05-08 14:05 UTC (permalink / raw)
To: Jeff Law
Cc: gcc-patches, Kito Cheng, Jim Wilson, Palmer Dabbelt,
Andrew Waterman, Philipp Tomsich, Vineet Gupta
On Wed, May 8, 2024 at 3:48 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 5/8/24 1:36 AM, Christoph Müllner wrote:
> > The lshr<GPR:mode>3_zero_extend_4 pattern targets bit extraction
> > with zero-extension. This pattern represents the canonical form
> > of zero-extensions of a logical right shift.
> >
> > The same optimization can be applied to sign-extensions.
> > Given the two optimizations are so similar, this patch converts
> > the existing one to also cover the sign-extension case as well.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/iterators.md (ashiftrt): New code attribute
> > 'extract_shift' and adding extractions to optab.
> > * config/riscv/riscv.md (*lshr<GPR:mode>3_zero_extend_4): Rename to...
> > (*<any_extract:optab><GPR:mode>3):...this and add support for
> > sign-extensions.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/extend-shift-helpers.h: Add helpers for
> > sign-extension.
> > * gcc.target/riscv/sign-extend-rshift-32.c: New test.
> > * gcc.target/riscv/sign-extend-rshift-64.c: New test.
> > * gcc.target/riscv/sign-extend-rshift.c: New test.
> Oh, I see, you handled the special case with this patch. Ignore my
> comment on 3/4. 3/4 is fine, as is this patch.
Oh, yes, I forgot to add this to 3/4.
Thanks!
>
> Thanks!
>
> jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-05-08 14:05 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-08 7:36 [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Christoph Müllner
2024-05-08 7:36 ` [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 Christoph Müllner
2024-05-08 13:40 ` Jeff Law
2024-05-08 7:36 ` [PATCH v2 3/4] RISC-V: Add zero_extract support for rv64gc Christoph Müllner
2024-05-08 13:46 ` Jeff Law
2024-05-08 7:36 ` [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4 Christoph Müllner
2024-05-08 13:48 ` Jeff Law
2024-05-08 14:05 ` Christoph Müllner
2024-05-08 13:38 ` [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Jeff Law
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).