[PATCH] RISC-V: Add vec_init expander for masks [PR112854].

[PATCH] RISC-V: Add vec_init expander for masks [PR112854].

[Robin Dapp]

Hi,

PR112854 shows a problem on rv32 with zvl1024b.  During the course of
expand_constructor we try to overlay/subreg a 64-element mask by a
scalar (Pmode) register.  This works for zvle512b and its maximum of
32 elements but fails for rv32 and 64 elements.

To circumvent this this patch adds a vec_init expander for vector masks
by initializing a QImode vector and comparing that against 0.  This
also ensures we don't do element initialization of masks.

Regards
 Robin

gcc/ChangeLog:

	PR target/112854

	* config/riscv/autovec.md (vec_init<mode>qi): New expander.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr112854.c: New test.
---
 gcc/config/riscv/autovec.md                      | 16 ++++++++++++++++
 .../gcc.target/riscv/rvv/autovec/pr112854.c      | 12 ++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3c4d68367f0..65ab76b3e0c 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -394,6 +394,22 @@ (define_expand "vec_init<mode><vel>"
   }
 )
 
+;; Provide a vec_init for mask registers by initializing
+;; a QImode vector and comparing it against 0.
+(define_expand "vec_init<mode>qi"
+  [(match_operand:VB 0 "register_operand")
+   (match_operand 1 "")]
+  "TARGET_VECTOR"
+  {
+    machine_mode qimode = riscv_vector::get_vector_mode
+	(QImode, GET_MODE_NUNITS (<MODE>mode)).require ();
+    rtx tmp = gen_reg_rtx (qimode);
+    riscv_vector::expand_vec_init (tmp, operands[1]);
+    riscv_vector::expand_vec_cmp (operands[0], NE, tmp, CONST0_RTX (qimode));
+    DONE;
+  }
+)
+
 ;; Slide an RVV vector left and insert a scalar into element 0.
 (define_expand "vec_shl_insert_<mode>"
   [(match_operand:VI 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
new file mode 100644
index 00000000000..8f7f13f9dc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+short a, b;
+void c(int d) {
+  for (; a; a--) {
+    b = 0;
+    for (; b <= 8; b++)
+      if (d)
+        break;
+  }
+}
-- 
2.43.0

Re: [PATCH] RISC-V: Add vec_init expander for masks [PR112854].

[juzhe.zhong]

[-- Attachment #1: Type: text/plain, Size: 2686 bytes --]

LGTM.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-12-05 23:13
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zhong@rivai.ai
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add vec_init expander for masks [PR112854].
Hi,
 
PR112854 shows a problem on rv32 with zvl1024b.  During the course of
expand_constructor we try to overlay/subreg a 64-element mask by a
scalar (Pmode) register.  This works for zvle512b and its maximum of
32 elements but fails for rv32 and 64 elements.
 
To circumvent this this patch adds a vec_init expander for vector masks
by initializing a QImode vector and comparing that against 0.  This
also ensures we don't do element initialization of masks.
 
Regards
Robin
 
gcc/ChangeLog:
 
PR target/112854
 
* config/riscv/autovec.md (vec_init<mode>qi): New expander.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/pr112854.c: New test.
---
gcc/config/riscv/autovec.md                      | 16 ++++++++++++++++
.../gcc.target/riscv/rvv/autovec/pr112854.c      | 12 ++++++++++++
2 files changed, 28 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
 
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3c4d68367f0..65ab76b3e0c 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -394,6 +394,22 @@ (define_expand "vec_init<mode><vel>"
   }
)
+;; Provide a vec_init for mask registers by initializing
+;; a QImode vector and comparing it against 0.
+(define_expand "vec_init<mode>qi"
+  [(match_operand:VB 0 "register_operand")
+   (match_operand 1 "")]
+  "TARGET_VECTOR"
+  {
+    machine_mode qimode = riscv_vector::get_vector_mode
+ (QImode, GET_MODE_NUNITS (<MODE>mode)).require ();
+    rtx tmp = gen_reg_rtx (qimode);
+    riscv_vector::expand_vec_init (tmp, operands[1]);
+    riscv_vector::expand_vec_cmp (operands[0], NE, tmp, CONST0_RTX (qimode));
+    DONE;
+  }
+)
+
;; Slide an RVV vector left and insert a scalar into element 0.
(define_expand "vec_shl_insert_<mode>"
   [(match_operand:VI 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
new file mode 100644
index 00000000000..8f7f13f9dc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+short a, b;
+void c(int d) {
+  for (; a; a--) {
+    b = 0;
+    for (; b <= 8; b++)
+      if (d)
+        break;
+  }
+}
-- 
2.43.0