From: Jeff Law <jeffreyalaw@gmail.com>
To: Fei Gao <gaofei@eswincomputing.com>, gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com, zengxiao@eswincomputing.com
Subject: Re: [PATCH 4/5] [ifcvt] optimize x=c ? (y op const_int) : y by RISC-V Zicond like insns
Date: Sun, 10 Dec 2023 22:38:39 -0700 [thread overview]
Message-ID: <9c06d609-34aa-4476-8835-aff581c1ead5@gmail.com> (raw)
In-Reply-To: <20231205081248.2106-4-gaofei@eswincomputing.com>
On 12/5/23 01:12, Fei Gao wrote:
> op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT, AND]
>
> Co-authored-by: Xiao Zeng<zengxiao@eswincomputing.com>
>
> gcc/ChangeLog:
>
> * ifcvt.cc (noce_cond_zero_shift_op_supported): check if OP is shift like operation
> (noce_cond_zero_binary_op_supported): restructure & call noce_cond_zero_shift_op_supported
> (noce_bbs_ok_for_cond_zero_arith): add support for const_int
> (noce_try_cond_zero_arith): add support for x=c ? (y op const_int)
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zicond_ifcvt_opt.c: add TCs for x=c ? (y op const_int) : y
> ---
> gcc/ifcvt.cc | 45 +-
> .../gcc.target/riscv/zicond_ifcvt_opt.c | 774 +++++++++++++++++-
> 2 files changed, 811 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
> index 29f33f956eb..b84be53ec5c 100644
> --- a/gcc/ifcvt.cc
> +++ b/gcc/ifcvt.cc
> @@ -2910,6 +2910,20 @@ noce_try_sign_mask (struct noce_if_info *if_info)
> return true;
> }
>
> +/* Check if OP is shift-like operation supported by conditional zero
> + based if conversion, returning TRUE if satisfied otherwise FALSE.
> +
> + OP is the operation to check. */
> +static bool
> +noce_cond_zero_shift_op_supported (enum rtx_code op)
> +{
> + if (op == ASHIFT || op == ASHIFTRT || op == LSHIFTRT || op == ROTATE
> + || op == ROTATERT)
> + return true;
Formatting nit. Go ahead and bring down the || op = ROTATE test as
well. That leaves the two lines better balanced with all the shifts on
one line and all the rotates on another. It's minor, but we might as
well keep it easy to read.
> @@ -3089,7 +3111,18 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info)
> return false;
> }
>
> - *to_replace = target;
> + if (CONST_INT_P (*to_replace))
> + {
> + if (noce_cond_zero_shift_op_supported (bin_code))
> + *to_replace = gen_rtx_SUBREG (E_QImode, target, 0);
> + else if (SUBREG_P (bin_op0))
> + *to_replace = gen_rtx_SUBREG (GET_MODE (bin_op0), target, 0);
> + else
> + *to_replace = target;
Not all targets use QImode for their shift counts, so you can't just
force that argument to QImode.
The way this works in our internal tree is that we re-expand the binary
operation rather than replacing bits of existing RTL. That allows the
expanders to do the right thing automatically for the target WRT
handling of things like the mode of the shift count. In fact, I don't
see how you can ever do replacement of a constant with a register with
the current scheme since the original constant will be modeless, so you
never know what mode to use.
Jeff
next prev parent reply other threads:[~2023-12-11 5:38 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-05 8:12 [PATCH 1/5][V3][ifcvt] optimize x=c ? (y op z) " Fei Gao
2023-12-05 8:12 ` [PATCH 2/5] [ifcvt] optimize x=c ? (y shift_op z):y " Fei Gao
2023-12-10 20:43 ` Jeff Law
2023-12-11 4:01 ` Fei Gao
2023-12-11 6:15 ` Jeff Law
2023-12-05 8:12 ` [PATCH 3/5] [ifcvt] optimize x=c ? (y AND z) : y " Fei Gao
2023-12-11 5:16 ` Jeff Law
2023-12-05 8:12 ` [PATCH 4/5] [ifcvt] optimize x=c ? (y op const_int) " Fei Gao
2023-12-11 5:38 ` Jeff Law [this message]
2023-12-14 8:42 ` Fei Gao
2023-12-05 8:12 ` [PATCH 5/5] [ifcvt] optimize extension for x=c ? (y op z) " Fei Gao
2023-12-11 5:46 ` Jeff Law
2023-12-14 9:32 ` Fei Gao
2023-12-08 0:49 ` [PATCH 1/5][V3][ifcvt] optimize " Jeff Law
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