[PATCH 2/2] arm: move the switch tables for Arm to the RO data section
2023-10-19 10:58 UTC (2+ messages)
[PATCH 1/2] arm: Use deltas for Arm switch tables
2023-10-19 10:57 UTC (2+ messages)
Enable top-level recursive 'autoreconf' (was: Hints on reconfiguring GCC)
2023-10-19 10:42 UTC (3+ messages)
` Enable top-level recursive 'autoreconf'
[PATCH] wwwdocs: gcc-14: mark amdgcn fiji deprecated
2023-10-19 10:07 UTC (2+ messages)
[PATCH] return edge in make_eh_edges
2023-10-19 9:09 UTC (2+ messages)
[committed] amdgcn: deprecate Fiji device and multilib
2023-10-19 8:58 UTC
[PATCH] x86: Correct ISA enabled for clients since Arrow Lake
2023-10-19 8:56 UTC (3+ messages)
` [PATCH v2] "
[PATCH V2] RISC-V: Fix failed hoist in LICM of vmv.v.x instruction
2023-10-19 8:53 UTC (4+ messages)
` "
[PATCH V3 00/11] Refactor and cleanup vsetvl pass
2023-10-19 8:50 UTC (15+ messages)
` [PATCH V3 01/11] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info/vector_block_info
` [PATCH V3 02/11] RISC-V: P2: Refactor and cleanup demand system
` [PATCH V3 03/11] RISC-V: P3: Refactor vector_infos_manager
` [PATCH V3 04/11] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
` [PATCH V3 05/11] RISC-V: P5: Combine phase 1 and 2
` [PATCH V3 06/11] RISC-V: P6: Add computing reaching definition data flow
` [PATCH V3 07/11] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
` [PATCH V3 08/11] RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization
` [PATCH V3 09/11] RISC-V: P9: Cleanup and reorganize helper functions
` [PATCH V3 10/11] RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
` [PATCH V3 11/11] RISC-V: P11: Adjust and add testcases
[PATCH] c-family: Enable -fpermissive for C and ObjC
2023-10-19 8:43 UTC
[PATCH V2 00/14] Refactor and cleanup vsetvl pass
2023-10-19 8:41 UTC (35+ messages)
` [PATCH V2 01/14] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info
` [PATCH V2 02/14] RISC-V: P2: Refactor and cleanup demand system
` [PATCH V2 03/14] RISC-V: P3: Refactor vector_infos_manager
` [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
` [PATCH V2 05/14] RISC-V: P5: combine phase 1 and 2
` [PATCH V2 06/14] RISC-V: P6: Add computing reaching definition data flow
` [PATCH V2 07/14] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
` [PATCH V2 08/14] RISC-V: P8: Unified insert and delete of vsetvl insn into Phase 4
` [PATCH V2 09/14] RISC-V: P9: Cleanup post optimize phase
` [PATCH V2 10/14] RISC-V: P10: Cleanup helper functions
` [PATCH V2 11/14] RISC-V: P11: Adjust vector_block_info to vsetvl_block_info class
` [PATCH V2 12/14] RISC-V: P12: Delete riscv-vsetvl.h
` [PATCH V2 13/14] RISC-V: P13: Reorganize functions used to modify RTL
` [PATCH V2 14/14] RISC-V: P14: Adjust and add testcases
[PATCH-2, rs6000] Enable vector mode for memory equality compare [PR111449]
2023-10-19 8:39 UTC (5+ messages)
[PATCH][_Hashtable] Fix merge
2023-10-19 8:05 UTC (2+ messages)
[PATCH v4 0/6] Add Loongson SX/ASX instruction support to LoongArch target
2023-10-19 8:00 UTC (5+ messages)
[PATCH] Avoid compile time hog on vect_peel_nonlinear_iv_init for nonlinear induction vec_step_op_mul when iteration count is too big. 65;6800;1c There's loop in vect_peel_nonlinear_iv_init to get init_expr * pow (step_expr, skip_niters). When skipn_iters is too big, compile time hogs. To avoid that, optimize init_expr * pow (step_expr, skip_niters) to init_expr << (exact_log2 (step_expr) * skip_niters) when step_expr is pow of 2, otherwise give up vectorization when skip_niters >= TYPE_PRECISION (TREE_TYPE (init_expr))
2023-10-19 7:14 UTC (5+ messages)
` [PATCH] Avoid compile time hog on vect_peel_nonlinear_iv_init for nonlinear induction vec_step_op_mul when iteration count is too big. 65; 6800; 1c "
` [PATCH] Avoid compile time hog on vect_peel_nonlinear_iv_init for nonlinear induction vec_step_op_mul when iteration count is too big
aarch64, vect, omp: Add SVE support for simd clones [PR 96342]
2023-10-19 7:10 UTC (26+ messages)
` [PATCH 1/8] parloops: Copy target and optimizations when creating a function clone
` [Patch 2/8] parloops: Allow poly nit and bound
` [Patch 3/8] vect: Fix vect_get_smallest_scalar_type for simd clones
` [PATCH 4/8] vect: don't allow fully masked loops with non-masked simd clones [PR 110485]
` [PATCH 5/8] vect: Use inbranch simdclones in masked loops
` [PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM
` [PATCH6/8] omp: Reorder call for TARGET_SIMD_CLONE_ADJUST (was Re: [PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM)
` [PATCH 8/8] aarch64: Add SVE support for simd clones [PR 96342]
` [PATCH 0/8] omp: Replace simd_clone_subparts with TYPE_VECTOR_SUBPARTS
[0/3] target_version and aarch64 function multiversioning
2023-10-19 7:04 UTC (5+ messages)
` [1/3] Add support for target_version attribute
` [2/3] [aarch64] Add function multiversioning support
` [3/3] WIP/RFC: Fix name mangling for target_clones
[PATCH v3 0/4] ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets
2023-10-19 6:53 UTC (3+ messages)
[PATCH 0/3] Optimize loongarch vector implementation
2023-10-19 6:16 UTC (2+ messages)
` "
[PATCH] aarch64: [PR110986] Emit csinv again for `a ? ~b : b`
2023-10-19 4:05 UTC
[PATCH 0/6] PowerPC Future patches
2023-10-19 0:06 UTC (7+ messages)
` [PATCH 1/6] PowerPC: Add -mcpu=future option
` [PATCH 2/6] PowerPC: Make -mcpu=future enable -mblock-ops-vector-pair
` [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers
` [PATCH 4/6] PowerPC: Make MMA insns support "
` [PATCH 5/6] PowerPC: Switch to dense math names for all MMA operations
` [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers
[COMMITTED] Fix expansion of `(a & 2) != 1`
2023-10-18 22:34 UTC
[PATCH V2 0/7] aarch64: Add support for __arm_rsr and __arm_wsr ACLE function family
2023-10-18 21:30 UTC (14+ messages)
` [PATCH V2 1/7] aarch64: Sync system register information with Binutils
` [PATCH V2 2/7] aarch64: Add support for aarch64-sys-regs.def
` [PATCH V2 3/7] aarch64: Implement system register validation tools
` [PATCH V2 4/7] aarch64: Add basic target_print_operand support for CONST_STRING
` [PATCH V2 5/7] aarch64: Implement system register r/w arm ACLE intrinsic functions
` [PATCH V2 6/7] aarch64: Add front-end argument type checking for target builtins
` [PATCH V2 7/7] aarch64: Add system register duplication check selftest
[PATCH] c++: Make -Wunknown-pragmas controllable by #pragma GCC diagnostic [PR89038]
2023-10-18 21:15 UTC
[V3][PATCH 0/3] New attribute "counted_by" to annotate bounds for C99 FAM(PR108896)
2023-10-18 21:11 UTC (19+ messages)
` [V3][PATCH 1/3] Provide counted_by attribute to flexible array member field (PR108896)
` [V3][PATCH 2/3] Use the counted_by atribute info in builtin object size [PR108896]
[PATCH] libcpp: testsuite: Add test for fixed _Pragma bug [PR82335]
2023-10-18 21:03 UTC (2+ messages)
[PATCH] RISC-V: Add popcount fallback expander
2023-10-18 20:25 UTC (10+ messages)
` "
[PATCH] gcc: Introduce -fhardened
2023-10-18 20:12 UTC (5+ messages)
` [PATCH v2] "
PR111648: Fix wrong code-gen due to incorrect VEC_PERM_EXPR folding
2023-10-18 19:04 UTC (9+ messages)
[PATCH 10/11] aarch64: Generalise TFmode load/store pair patterns
2023-10-18 18:16 UTC (2+ messages)
[PATCH 09/11] aarch64, testsuite: Fix up pr71727.c
2023-10-18 18:13 UTC (2+ messages)
[PATCH 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]
2023-10-18 18:12 UTC (14+ messages)
` [PATCH v2 "
` [PATCH v3 "
[PATCH 08/11] aarch64, testsuite: Tweak sve/pcs/args_9.c to allow stps
2023-10-18 18:12 UTC (2+ messages)
[PATCH 07/11] aarch64, testsuite: Prevent stp in lr_free_1.c
2023-10-18 18:10 UTC (2+ messages)
[PATCH 04/11] rtl-ssa: Support inferring uses of mem in change_insns
2023-10-18 18:00 UTC (2+ messages)
[PATCH 03/11] rtl-ssa: Add entry point to allow re-parenting uses
2023-10-18 17:57 UTC (2+ messages)
[PATCH 02/11] rtl-ssa: Add drop_memory_access helper
2023-10-18 17:55 UTC (2+ messages)
[PATCH 01/11] rtl-ssa: Fix bug in function_info::add_insn_after
2023-10-18 17:54 UTC (2+ messages)
[x86 PATCH] PR 106245: Split (x<<31)>>31 as -(x&1) in i386.md
2023-10-18 17:43 UTC (4+ messages)
[committed] pru: Implement TARGET_INSN_COST
2023-10-18 17:18 UTC
[avr,committed] LibF7: Implement a function that was missing for devices without MUL
2023-10-18 17:03 UTC
[PATCH] c++/modules: ICE with lambda initializing local var [PR105322]
2023-10-18 16:34 UTC (2+ messages)
[Patch] nvptx: Use fatal_error when -march= is missing not an assert [PR111093]
2023-10-18 16:01 UTC (3+ messages)
aarch64: Replace duplicated selftests
2023-10-18 15:24 UTC
[PATCH] vect: Allow same precision for bit-precision conversions
2023-10-18 15:14 UTC (2+ messages)
[PATCH v2] swap: Fix incorrect lane extraction by vec_extract() [PR106770]
2023-10-18 14:44 UTC
[PATCH v2] swap: Fix incorrect lane extraction by vec_extract() [PR106770]
2023-10-18 14:42 UTC
[x86 PATCH] PR target/110551: Fix reg allocation for widening multiplications
2023-10-18 14:29 UTC
[PATCH] lra: Avoid unfolded plus-0
2023-10-18 13:59 UTC (3+ messages)
` [Backport RFA] "
[PATCH V5] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721]
2023-10-18 12:42 UTC (2+ messages)
[PATCH] RISC-V: Add popcount fallback expander
2023-10-18 12:17 UTC
[PATCH] Support g++ 4.8 as a host compiler
2023-10-18 11:51 UTC (9+ messages)
[PATCH v1] RISC-V: Remove the type size restriction of vectorizer
2023-10-18 11:50 UTC (3+ messages)
[Patch] Fortran: Support OpenMP's 'allocate' directive for stack vars
2023-10-18 11:01 UTC (7+ messages)
` [Patch] OpenMP: Avoid ICE with LTO and 'omp allocate (was: [Patch] Fortran: Support OpenMP's 'allocate' directive for stack vars)
[PATCH] libstdc++: testsuite: Enhance codecvt_unicode with tests for length()
2023-10-18 10:52 UTC (4+ messages)
` [PATCH v2] "
[PATCH] tree-ssa-math-opts: Fix up match_uaddc_usubc [PR111845]
2023-10-18 10:36 UTC (2+ messages)
[PATCH] RISC-V: Fix failed hoist in LICM of vmv.v.x instruction
2023-10-18 10:26 UTC (2+ messages)
[Patch] OpenMP: Add ME support for 'omp allocate' stack variables
2023-10-18 10:01 UTC (4+ messages)
[pushed] Darwin: Check as for .build_version support and use it if available
2023-10-18 9:40 UTC
[PATCH] Harmonize headers between both dg-extract-results scripts
2023-10-18 9:35 UTC (7+ messages)
` [PING] "
[PATCH] LoongArch: Use fcmp.caf.s instead of movgr2cf for zeroing a fcc
2023-10-18 8:41 UTC (4+ messages)
` Pushed: "
[PATCH] Re-instantiate integer mask to traditional vector mask support
2023-10-18 8:17 UTC
GCC 14.0.0 Status Report (2023-10-18), Stage 1 ends Nov. 19th
2023-10-18 8:04 UTC
[r14-4629 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18f.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64
2023-10-18 8:01 UTC (4+ messages)
[PATCH] RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx
2023-10-18 8:00 UTC (3+ messages)
[PATCH 0/3] Add Intel new cpu archs
2023-10-18 6:30 UTC (3+ messages)
[PATCH RFC] diagnostic: add permerror variants with opt
2023-10-18 6:23 UTC (4+ messages)
` [PATCH v2 RFA] "
` PING "
[PATCH] vect: Cost adjacent vector loads/stores together [PR111784]
2023-10-18 5:09 UTC
[PATCH] RISC-V: Enable more tests for dynamic LMUL and bug fix[PR111832]
2023-10-18 1:05 UTC (2+ messages)
[PATCH 2/2] aarch64: Put LR save slot first in more cases
2023-10-17 22:48 UTC
[PATCH 1/2] aarch64: Use vecs to store register save order
2023-10-17 22:48 UTC
[PATCH] c++: accepts-invalid with =delete("") [PR111840]
2023-10-17 21:42 UTC (2+ messages)
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