[PATCH][committed] aarch64: PR target/PR99195 Annotate more simple integer binary patterns with vcz subst rules

[PATCH][committed] aarch64: PR target/PR99195 Annotate more simple integer binary patterns with vcz subst rules

[Kyrylo Tkachov]

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Hi all,

This patch adds more straightforward annotations to some more integer binary ops to
eliminate redundant fmovs around 64-bit SIMD results.

Bootstrapped and tested on aarch64-none-linux.
Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

	PR target/PR99195
	* config/aarch64/aarch64-simd.md (orn<mode>3): Rename to...
	(orn<mode>3<vczle><vczbe>): ... This.
	(bic<mode>3): Rename to...
	(bic<mode>3<vczle><vczbe>): ... This.
	(<su><maxmin><mode>3): Rename to...
	(<su><maxmin><mode>3<vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	PR target/PR99195
	* gcc.target/aarch64/simd/pr99195_1.c: Add tests for orn, bic, max and min.

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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 0bf4346227ead8c8568c1221cb4f1ed546079efc..d2321113671053ec4c4ec3f7379d3287f9d922ee 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -398,7 +398,7 @@ (define_insn "aarch64_simd_mov_from_<mode>high"
    (set_attr "length" "4")]
 )
 
-(define_insn "orn<mode>3"
+(define_insn "orn<mode>3<vczle><vczbe>"
  [(set (match_operand:VDQ_I 0 "register_operand" "=w")
        (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w"))
 		(match_operand:VDQ_I 2 "register_operand" "w")))]
@@ -407,7 +407,7 @@ (define_insn "orn<mode>3"
   [(set_attr "type" "neon_logic<q>")]
 )
 
-(define_insn "bic<mode>3"
+(define_insn "bic<mode>3<vczle><vczbe>"
  [(set (match_operand:VDQ_I 0 "register_operand" "=w")
        (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w"))
 		(match_operand:VDQ_I 2 "register_operand" "w")))]
@@ -1697,7 +1697,7 @@ (define_insn "aarch64_mls_n<mode>"
 )
 
 ;; Max/Min operations.
-(define_insn "<su><maxmin><mode>3"
+(define_insn "<su><maxmin><mode>3<vczle><vczbe>"
  [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
        (MAXMIN:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w")
 		    (match_operand:VDQ_BHSI 2 "register_operand" "w")))]
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c
index 3fe0e53bcd086a202ec1580a0b118121ef9334cc..5304e14b573aa7dea6b4eb2a3103882bb482a00d 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c
@@ -37,18 +37,17 @@ OPFOUR (T, IS, OS, S, OP2, OP3, OP4, OP5)
 FUNC (T, IS, OS, OP1, S)                \
 OPFIVE (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6)
 
-#define OPSEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7)        \
-FUNC (T, IS, OS, OP1, S)                \
-OPSIX (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6, OP7)
-
+#define OPELEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7,OP8,OP9,OP10,OP11)        \
+OPFIVE (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5)                \
+OPSIX (T, IS, OS, S, OP6, OP7, OP8, OP9, OP10, OP11)
 
-OPSEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor)
-OPSEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor)
-OPSEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor)
+OPELEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min)
+OPELEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min)
+OPELEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min)
 
-OPSEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor)
-OPSEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor)
-OPSEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor)
+OPELEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min)
+OPELEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min)
+OPELEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min)
 
 /* { dg-final { scan-assembler-not {\tfmov\t} } }  */
 /* { dg-final { scan-assembler-not {\tmov\t} } }  */