From: Kito Cheng <kito.cheng@gmail.com>
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com
Subject: Re: [PATCH] RISC-V: Add the rest testcases of AVL=REG support
Date: Fri, 27 Jan 2023 03:17:48 +0800 [thread overview]
Message-ID: <CA+yXCZA-M0g4GF+KQQ3FXc6hFgRtMMKa=gsq6XciCL59UhvHcg@mail.gmail.com> (raw)
In-Reply-To: <20230109234026.161632-1-juzhe.zhong@rivai.ai>
[-- Attachment #1: Type: text/plain, Size: 30716 bytes --]
committed, thanks.
On Tue, Jan 10, 2023 at 7:41 AM <juzhe.zhong@rivai.ai> wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: New test.
> * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: New test.
>
> ---
> .../riscv/rvv/vsetvl/avl_single-1.c | 17 ++++++
> .../riscv/rvv/vsetvl/avl_single-10.c | 21 +++++++
> .../riscv/rvv/vsetvl/avl_single-11.c | 21 +++++++
> .../riscv/rvv/vsetvl/avl_single-12.c | 19 +++++++
> .../riscv/rvv/vsetvl/avl_single-13.c | 28 ++++++++++
> .../riscv/rvv/vsetvl/avl_single-14.c | 27 +++++++++
> .../riscv/rvv/vsetvl/avl_single-15.c | 27 +++++++++
> .../riscv/rvv/vsetvl/avl_single-16.c | 32 +++++++++++
> .../riscv/rvv/vsetvl/avl_single-17.c | 29 ++++++++++
> .../riscv/rvv/vsetvl/avl_single-18.c | 29 ++++++++++
> .../riscv/rvv/vsetvl/avl_single-19.c | 40 +++++++++++++
> .../riscv/rvv/vsetvl/avl_single-7.c | 17 ++++++
> .../riscv/rvv/vsetvl/avl_single-70.c | 41 ++++++++++++++
> .../riscv/rvv/vsetvl/avl_single-71.c | 54 ++++++++++++++++++
> .../riscv/rvv/vsetvl/avl_single-72.c | 46 +++++++++++++++
> .../riscv/rvv/vsetvl/avl_single-8.c | 18 ++++++
> .../riscv/rvv/vsetvl/avl_single-9.c | 56 +++++++++++++++++++
> 17 files changed, 522 insertions(+)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
> new file mode 100644
> index 00000000000..84225dbe7d2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int n, int vl)
> +{
> + for (int i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts
> "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
> new file mode 100644
> index 00000000000..f64d1c3680f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
> @@ -0,0 +1,21 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int n)
> +{
> + size_t vl = 39;
> + for (int i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +
> + vint8mf2_t v2 = __riscv_vle8_v_i8mf2 (in + i + 100, vl);
> + __riscv_vse8_v_i8mf2 (out + i + 100, v2, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
> no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
> new file mode 100644
> index 00000000000..e1a8383e0db
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
> @@ -0,0 +1,21 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int n)
> +{
> + size_t vl = 39;
> + for (int i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts
> "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
> new file mode 100644
> index 00000000000..027bc387a5e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
> @@ -0,0 +1,19 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
> +{
> + if (cond == 2) {
> + size_t vl = 101;
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 900, vl);
> + __riscv_vse8_v_i8mf8 (out + 900, v, vl);
> + vl = 102;
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 1000, vl);
> + __riscv_vse8_v_i8mf8 (out + 1000, v2, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
> new file mode 100644
> index 00000000000..faf68950ad7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
> +{
> + size_t vl = 101;
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
> + }
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 200, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 200, v2, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
> new file mode 100644
> index 00000000000..501d14c6e2d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
> +{
> + size_t vl = 101;
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
> + }
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
> new file mode 100644
> index 00000000000..501e0766c22
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
> +{
> + size_t vl = 101;
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
> + }
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
> new file mode 100644
> index 00000000000..75bed40562d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
> @@ -0,0 +1,32 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int
> cond)
> +{
> + size_t vl = 101;
> + vbool64_t mask = *(vbool64_t*) (in + 1000000);
> + for (size_t j = 0; j < m; j++){
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in + i + j +
> 100, vl);
> + __riscv_vse8_v_i8mf8_m (mask, out + i + j + 100, v2, vl);
> + }
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j +
> 200), vl);
> + __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
> +
> + vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float
> *)(in + i + j + 300), vl);
> + __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2,
> vl);
> + }
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts
> "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
> new file mode 100644
> index 00000000000..ad2b34095eb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int
> cond)
> +{
> + size_t vl = 101;
> + vbool64_t mask = *(vbool64_t*) (in + 1000000);
> + for (size_t j = 0; j < m; j++){
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> + }
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j +
> 200), vl);
> + __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
> +
> + vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float
> *)(in + i + j + 300), vl);
> + __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2,
> vl);
> + }
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
> new file mode 100644
> index 00000000000..3860c6d54ff
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int
> cond)
> +{
> + size_t vl = 101;
> + vbool64_t mask = *(vbool64_t*) (in + 1000000);
> + for (size_t j = 0; j < m; j++){
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> +
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in + i + j +
> 100, vl);
> + __riscv_vse8_v_i8mf8_m (mask, out + i + j + 100, v2, vl);
> + }
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j +
> 200), vl);
> + __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
> + }
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
> new file mode 100644
> index 00000000000..350e1d08180
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
> @@ -0,0 +1,40 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2 -fno-tree-vectorize" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int
> cond)
> +{
> + size_t vl = 101;
> + vbool64_t mask = *(vbool64_t*) (in + 1000000);
> + for (size_t j = 0; j < m; j++){
> + for (size_t i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> + }
> +
> + for (size_t i = 0; i < n * n; i++)
> + out[i] = out[i] * out[i];
> + for (size_t i = 0; i < n * n * n; i++)
> + out[i] = out[i] + out[i];
> + for (size_t i = 0; i < n * n * n * n; i++)
> + out[i] = out[i] + 2;
> + for (size_t i = 0; i < n * n * n * n * n; i++)
> + out[i] = out[i] * 100;
> + for (size_t i = 0; i < n * n * n * n * n * n; i++)
> + out[i] = out[i] - 77;
> +
> + for (size_t i = 0; i < n; i++)
> + {
> + vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + j +
> 200), vl);
> + __riscv_vse32_v_f32mf2 ((float *)(out + i + j + 200), v, vl);
> +
> + vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float
> *)(in + i + j + 300), vl);
> + __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + j + 300), v2,
> vl);
> + }
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
> new file mode 100644
> index 00000000000..bd407b25d54
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int n)
> +{
> + register size_t vl asm ("a5");
> + for (int i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*a5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts
> "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
> new file mode 100644
> index 00000000000..89036abc9d8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
> @@ -0,0 +1,41 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize
> -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m,
> size_t cond)
> +{
> + size_t vl = 555;
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl);
> + __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl);
> + }
> + }
> + }
> +
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + out[i+j+k+10000000] = out[i+j+k+10000000] + in[i+j+k+10000000];
> + }
> + }
> + }
> +
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000,
> vl);
> + v = __riscv_vle8_v_i8mf8_tu (v, in + i + j + k + 20000, vl);
> + __riscv_vse8_v_i8mf8 (out + i + j + k + 10000, v, vl);
> + }
> + }
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
> new file mode 100644
> index 00000000000..0f780a7cb55
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
> @@ -0,0 +1,54 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize
> -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m,
> size_t cond)
> +{
> + size_t vl = 555;
> +
> + if (cond) {
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl);
> + __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl);
> + }
> + }
> + }
> + } else {
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + vint32mf2_t v = __riscv_vle32_v_i32mf2 ((int32_t *)(in + i +
> j + k), vl);
> + __riscv_vse32_v_i32mf2 ((int32_t *)(out + i + j + k), v, vl);
> + }
> + }
> + }
> + }
> +
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + out[i+j+k+10000000] = out[i+j+k+10000000] + in[i+j+k+10000000];
> + }
> + }
> + }
> +
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000,
> vl);
> + v = __riscv_vle8_v_i8mf8_tu (v, in + i + j + k + 20000, vl);
> + __riscv_vse8_v_i8mf8 (out + i + j + k + 10000, v, vl);
> + }
> + }
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts
> "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
> new file mode 100644
> index 00000000000..866370f0618
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
> @@ -0,0 +1,46 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize
> -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m,
> size_t cond)
> +{
> + size_t vl = 555;
> +
> + if (cond) {
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl);
> + __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl);
> + }
> + }
> + }
> + } else {
> + out[999] = out[999] * in[999];
> + }
> +
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + out[i+j+k+10000000] = out[i+j+k+10000000] + in[i+j+k+10000000];
> + }
> + }
> + }
> +
> + for (int i = 0; i < l; i++){
> + for (int j = 0; j < m; j++){
> + for (int k = 0; k < n; k++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k + 10000,
> vl);
> + v = __riscv_vle8_v_i8mf8_tu (v, in + i + j + k + 20000, vl);
> + __riscv_vse8_v_i8mf8 (out + i + j + k + 10000, v, vl);
> + }
> + }
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts
> "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
> no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
> new file mode 100644
> index 00000000000..0785af7f020
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int n)
> +{
> + size_t vl = 32;
> + for (int i = 0; i < n; i++)
> + {
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
> + __riscv_vse8_v_i8mf8 (out + i, v, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts
> "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
> new file mode 100644
> index 00000000000..0ecfb969685
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
> @@ -0,0 +1,56 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
> -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +void f (void * restrict in, void * restrict out, int l, int n, int m)
> +{
> + int vl = 32;
> + for (int i = 0; i < n; i++)
> + {
> + vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + i + 1, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 1, v1, vl);
> +
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8 (in + i + 2, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 2, v2, vl);
> +
> + vint8mf8_t v3 = __riscv_vle8_v_i8mf8 (in + i + 3, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 3, v3, vl);
> +
> + vint8mf8_t v4 = __riscv_vle8_v_i8mf8 (in + i + 4, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 4, v4, vl);
> +
> + vint8mf8_t v5 = __riscv_vle8_v_i8mf8 (in + i + 5, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 5, v5, vl);
> +
> + vint8mf8_t v6 = __riscv_vle8_v_i8mf8 (in + i + 6, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 6, v6, vl);
> +
> + vint8mf8_t v7 = __riscv_vle8_v_i8mf8 (in + i + 7, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 7, v7, vl);
> +
> + vint8mf8_t v8 = __riscv_vle8_v_i8mf8 (in + i + 8, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 8, v8, vl);
> +
> + vint8mf8_t v9 = __riscv_vle8_v_i8mf8 (in + i + 9, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 9, v9, vl);
> +
> + vint8mf8_t v10 = __riscv_vle8_v_i8mf8 (in + i + 10, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 10, v10, vl);
> +
> + vint8mf8_t v11 = __riscv_vle8_v_i8mf8 (in + i + 11, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 11, v11, vl);
> +
> + vint8mf8_t v12 = __riscv_vle8_v_i8mf8 (in + i + 12, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 12, v12, vl);
> +
> + vint8mf8_t v13 = __riscv_vle8_v_i8mf8 (in + i + 13, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 13, v13, vl);
> +
> + vint8mf8_t v14 = __riscv_vle8_v_i8mf8 (in + i + 14, vl);
> + __riscv_vse8_v_i8mf8 (out + i + 14, v14, vl);
> + }
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
> no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
> +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> --
> 2.36.1
>
>
prev parent reply other threads:[~2023-01-26 19:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-09 23:40 juzhe.zhong
2023-01-26 19:17 ` Kito Cheng [this message]
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