* [PATCH] RISC-V: Add vm* mask C api tests
@ 2023-02-16 3:36 juzhe.zhong
2023-02-16 9:38 ` Jakub Jelinek
0 siblings, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2023-02-16 3:36 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmand_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmand_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmand_mm-3.c: New test.
* gcc.target/riscv/rvv/base/vmandn_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmandn_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmandn_mm-3.c: New test.
* gcc.target/riscv/rvv/base/vmclr_m_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmclr_m_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmclr_m_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmmv_m_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmmv_m_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmmv_m_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmnand_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmnand_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmnand_mm-3.c: New test.
* gcc.target/riscv/rvv/base/vmnor_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmnor_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmnor_mm-3.c: New test.
* gcc.target/riscv/rvv/base/vmnot_m_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmnot_m_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmnot_m_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmor_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmor_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmor_mm-3.c: New test.
* gcc.target/riscv/rvv/base/vmorn_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmorn_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmorn_mm-3.c: New test.
* gcc.target/riscv/rvv/base/vmsbf_m_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbf_m_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbf_m_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vmset_m_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmset_m_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmset_m_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmsif_m_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmsif_m_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmsif_m_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmsif_m_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vmsif_m_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vmsif_m_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vmsof_m_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmsof_m_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmsof_m_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmsof_m_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vmsof_m_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vmsof_m_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vmxnor_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmxnor_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmxnor_mm-3.c: New test.
* gcc.target/riscv/rvv/base/vmxor_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmxor_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmxor_mm-3.c: New test.
---
.../gcc.target/riscv/rvv/base/vmand_mm-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmand_mm-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmand_mm-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmandn_mm-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmandn_mm-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmandn_mm-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmclr_m_m-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmclr_m_m-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmclr_m_m-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmmv_m_m-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmmv_m_m-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmmv_m_m-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnand_mm-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnand_mm-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnand_mm-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnor_mm-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnor_mm-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnor_mm-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnot_m_m-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnot_m_m-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmnot_m_m-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmor_mm-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmor_mm-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmor_mm-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmorn_mm-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmorn_mm-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmorn_mm-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsbf_m_m-1.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsbf_m_m-2.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsbf_m_m-3.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmset_m_m-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmset_m_m-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmset_m_m-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsif_m_m-1.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsif_m_m-2.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsif_m_m-3.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsif_m_mu-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsif_m_mu-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsif_m_mu-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsof_m_m-1.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsof_m_m-2.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsof_m_m-3.c | 104 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vmsof_m_mu-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsof_m_mu-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmsof_m_mu-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmxnor_mm-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmxnor_mm-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmxnor_mm-3.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmxor_mm-1.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmxor_mm-2.c | 55 +++++++++
.../gcc.target/riscv/rvv/base/vmxor_mm-3.c | 55 +++++++++
54 files changed, 3411 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c
new file mode 100644
index 00000000000..9f11c8420dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c
new file mode 100644
index 00000000000..81d96b85f0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c
new file mode 100644
index 00000000000..4b5dd50cf80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmand_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c
new file mode 100644
index 00000000000..f0ccd9f54f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c
new file mode 100644
index 00000000000..a6605c4597d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c
new file mode 100644
index 00000000000..ad48a8547b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmandn_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c
new file mode 100644
index 00000000000..74f89f1a445
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmclr_m_b1(size_t vl)
+{
+ return __riscv_vmclr_m_b1(vl);
+}
+
+
+vbool2_t test___riscv_vmclr_m_b2(size_t vl)
+{
+ return __riscv_vmclr_m_b2(vl);
+}
+
+
+vbool4_t test___riscv_vmclr_m_b4(size_t vl)
+{
+ return __riscv_vmclr_m_b4(vl);
+}
+
+
+vbool8_t test___riscv_vmclr_m_b8(size_t vl)
+{
+ return __riscv_vmclr_m_b8(vl);
+}
+
+
+vbool16_t test___riscv_vmclr_m_b16(size_t vl)
+{
+ return __riscv_vmclr_m_b16(vl);
+}
+
+
+vbool32_t test___riscv_vmclr_m_b32(size_t vl)
+{
+ return __riscv_vmclr_m_b32(vl);
+}
+
+
+vbool64_t test___riscv_vmclr_m_b64(size_t vl)
+{
+ return __riscv_vmclr_m_b64(vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c
new file mode 100644
index 00000000000..e4c91959dd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmclr_m_b1(size_t vl)
+{
+ return __riscv_vmclr_m_b1(31);
+}
+
+
+vbool2_t test___riscv_vmclr_m_b2(size_t vl)
+{
+ return __riscv_vmclr_m_b2(31);
+}
+
+
+vbool4_t test___riscv_vmclr_m_b4(size_t vl)
+{
+ return __riscv_vmclr_m_b4(31);
+}
+
+
+vbool8_t test___riscv_vmclr_m_b8(size_t vl)
+{
+ return __riscv_vmclr_m_b8(31);
+}
+
+
+vbool16_t test___riscv_vmclr_m_b16(size_t vl)
+{
+ return __riscv_vmclr_m_b16(31);
+}
+
+
+vbool32_t test___riscv_vmclr_m_b32(size_t vl)
+{
+ return __riscv_vmclr_m_b32(31);
+}
+
+
+vbool64_t test___riscv_vmclr_m_b64(size_t vl)
+{
+ return __riscv_vmclr_m_b64(31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c
new file mode 100644
index 00000000000..12cd1a5c0fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmclr_m_b1(size_t vl)
+{
+ return __riscv_vmclr_m_b1(32);
+}
+
+
+vbool2_t test___riscv_vmclr_m_b2(size_t vl)
+{
+ return __riscv_vmclr_m_b2(32);
+}
+
+
+vbool4_t test___riscv_vmclr_m_b4(size_t vl)
+{
+ return __riscv_vmclr_m_b4(32);
+}
+
+
+vbool8_t test___riscv_vmclr_m_b8(size_t vl)
+{
+ return __riscv_vmclr_m_b8(32);
+}
+
+
+vbool16_t test___riscv_vmclr_m_b16(size_t vl)
+{
+ return __riscv_vmclr_m_b16(32);
+}
+
+
+vbool32_t test___riscv_vmclr_m_b32(size_t vl)
+{
+ return __riscv_vmclr_m_b32(32);
+}
+
+
+vbool64_t test___riscv_vmclr_m_b64(size_t vl)
+{
+ return __riscv_vmclr_m_b64(32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c
new file mode 100644
index 00000000000..8ebb69128b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b64(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c
new file mode 100644
index 00000000000..bd97c0daa7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b64(op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c
new file mode 100644
index 00000000000..fa8cb2f6f6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmmv_m_b64(op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c
new file mode 100644
index 00000000000..9c2f38f6194
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c
new file mode 100644
index 00000000000..35eeedb12e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c
new file mode 100644
index 00000000000..69b32ef8111
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmnand_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c
new file mode 100644
index 00000000000..7724fcb2725
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c
new file mode 100644
index 00000000000..91eabb9a800
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c
new file mode 100644
index 00000000000..2eb333b6f46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmnor_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c
new file mode 100644
index 00000000000..bba5506cf11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b64(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c
new file mode 100644
index 00000000000..a7c872372a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b64(op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c
new file mode 100644
index 00000000000..8c68be9f870
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmnot_m_b64(op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c
new file mode 100644
index 00000000000..638c0b3743f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c
new file mode 100644
index 00000000000..eb8ebc25904
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c
new file mode 100644
index 00000000000..3b6a7e81ef9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmor_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c
new file mode 100644
index 00000000000..c8c383dbc78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c
new file mode 100644
index 00000000000..d612293066c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c
new file mode 100644
index 00000000000..d3701ddc453
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmorn_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c
new file mode 100644
index 00000000000..393928d7069
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64(op1,vl);
+}
+
+
+vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1_m(mask,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2_m(mask,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4_m(mask,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8_m(mask,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16_m(mask,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32_m(mask,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c
new file mode 100644
index 00000000000..961282f52a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64(op1,31);
+}
+
+
+vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1_m(mask,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2_m(mask,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4_m(mask,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8_m(mask,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16_m(mask,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32_m(mask,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c
new file mode 100644
index 00000000000..60802fa81d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64(op1,32);
+}
+
+
+vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1_m(mask,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2_m(mask,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4_m(mask,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8_m(mask,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16_m(mask,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32_m(mask,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c
new file mode 100644
index 00000000000..81255e48b63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c
new file mode 100644
index 00000000000..377613d89af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c
new file mode 100644
index 00000000000..16ebb27f67c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c
new file mode 100644
index 00000000000..3be6e704197
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmset_m_b1(size_t vl)
+{
+ return __riscv_vmset_m_b1(vl);
+}
+
+
+vbool2_t test___riscv_vmset_m_b2(size_t vl)
+{
+ return __riscv_vmset_m_b2(vl);
+}
+
+
+vbool4_t test___riscv_vmset_m_b4(size_t vl)
+{
+ return __riscv_vmset_m_b4(vl);
+}
+
+
+vbool8_t test___riscv_vmset_m_b8(size_t vl)
+{
+ return __riscv_vmset_m_b8(vl);
+}
+
+
+vbool16_t test___riscv_vmset_m_b16(size_t vl)
+{
+ return __riscv_vmset_m_b16(vl);
+}
+
+
+vbool32_t test___riscv_vmset_m_b32(size_t vl)
+{
+ return __riscv_vmset_m_b32(vl);
+}
+
+
+vbool64_t test___riscv_vmset_m_b64(size_t vl)
+{
+ return __riscv_vmset_m_b64(vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c
new file mode 100644
index 00000000000..d020c8decaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmset_m_b1(size_t vl)
+{
+ return __riscv_vmset_m_b1(31);
+}
+
+
+vbool2_t test___riscv_vmset_m_b2(size_t vl)
+{
+ return __riscv_vmset_m_b2(31);
+}
+
+
+vbool4_t test___riscv_vmset_m_b4(size_t vl)
+{
+ return __riscv_vmset_m_b4(31);
+}
+
+
+vbool8_t test___riscv_vmset_m_b8(size_t vl)
+{
+ return __riscv_vmset_m_b8(31);
+}
+
+
+vbool16_t test___riscv_vmset_m_b16(size_t vl)
+{
+ return __riscv_vmset_m_b16(31);
+}
+
+
+vbool32_t test___riscv_vmset_m_b32(size_t vl)
+{
+ return __riscv_vmset_m_b32(31);
+}
+
+
+vbool64_t test___riscv_vmset_m_b64(size_t vl)
+{
+ return __riscv_vmset_m_b64(31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c
new file mode 100644
index 00000000000..e1761956b0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmset_m_b1(size_t vl)
+{
+ return __riscv_vmset_m_b1(32);
+}
+
+
+vbool2_t test___riscv_vmset_m_b2(size_t vl)
+{
+ return __riscv_vmset_m_b2(32);
+}
+
+
+vbool4_t test___riscv_vmset_m_b4(size_t vl)
+{
+ return __riscv_vmset_m_b4(32);
+}
+
+
+vbool8_t test___riscv_vmset_m_b8(size_t vl)
+{
+ return __riscv_vmset_m_b8(32);
+}
+
+
+vbool16_t test___riscv_vmset_m_b16(size_t vl)
+{
+ return __riscv_vmset_m_b16(32);
+}
+
+
+vbool32_t test___riscv_vmset_m_b32(size_t vl)
+{
+ return __riscv_vmset_m_b32(32);
+}
+
+
+vbool64_t test___riscv_vmset_m_b64(size_t vl)
+{
+ return __riscv_vmset_m_b64(32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c
new file mode 100644
index 00000000000..e22e1772c92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64(op1,vl);
+}
+
+
+vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1_m(mask,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2_m(mask,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4_m(mask,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8_m(mask,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16_m(mask,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32_m(mask,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c
new file mode 100644
index 00000000000..cb7ad9faece
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64(op1,31);
+}
+
+
+vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1_m(mask,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2_m(mask,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4_m(mask,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8_m(mask,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16_m(mask,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32_m(mask,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c
new file mode 100644
index 00000000000..c92b0e9b89a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64(op1,32);
+}
+
+
+vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1_m(mask,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2_m(mask,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4_m(mask,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8_m(mask,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16_m(mask,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32_m(mask,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c
new file mode 100644
index 00000000000..7a7075e61e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c
new file mode 100644
index 00000000000..8e8222bd3b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c
new file mode 100644
index 00000000000..c305562df82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c
new file mode 100644
index 00000000000..87202ff62ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64(op1,vl);
+}
+
+
+vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1_m(mask,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2_m(mask,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4_m(mask,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8_m(mask,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16_m(mask,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32_m(mask,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c
new file mode 100644
index 00000000000..6e4f3ce1288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64(op1,31);
+}
+
+
+vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1_m(mask,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2_m(mask,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4_m(mask,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8_m(mask,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16_m(mask,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32_m(mask,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c
new file mode 100644
index 00000000000..55cf50d5c9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64(op1,32);
+}
+
+
+vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1_m(mask,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2_m(mask,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4_m(mask,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8_m(mask,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16_m(mask,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32_m(mask,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c
new file mode 100644
index 00000000000..4b9d846631e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c
new file mode 100644
index 00000000000..3f4ea728505
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c
new file mode 100644
index 00000000000..9c143bfc746
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+ return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c
new file mode 100644
index 00000000000..0d63ea7718e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c
new file mode 100644
index 00000000000..ba39230b2b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c
new file mode 100644
index 00000000000..e74c39b5dde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmxnor_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c
new file mode 100644
index 00000000000..b7072e492fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c
new file mode 100644
index 00000000000..3222cd2f7bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c
new file mode 100644
index 00000000000..9938dc94151
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+ return __riscv_vmxor_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
--
2.36.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] RISC-V: Add vm* mask C api tests
2023-02-16 3:36 [PATCH] RISC-V: Add vm* mask C api tests juzhe.zhong
@ 2023-02-16 9:38 ` Jakub Jelinek
2023-02-16 9:53 ` juzhe.zhong
0 siblings, 1 reply; 6+ messages in thread
From: Jakub Jelinek @ 2023-02-16 9:38 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, kito.cheng, Jeff Law
Hi!
I see in the past few weeks you've added huge amounts of these tests
du -shc *.target/riscv/*/
34M gcc.target/riscv/rvv/
28M g++.target/riscv/rvv/
61M total
and new are coming (nothing at all at this year's start).
This is far larger than tests of any other architecture
(i386 has 35M total, aarch64 31M total, arm 17M total, powerpc 12M total,
everything else is even much smaller) but for the other architectures it has
been decades of testsuite coverage for features added over the years.
Rather than looking purely at size, I'm more worried about the content
of the tests. Usually target testsuites include runtime tests whether
particular intrinsics etc. behave correctly at runtime, plus some compile
tests that they can be compiled with occassional scan-assembler* to mention
a particular instruction appears, but in these cases the scan-assembler*
covers the entire (albeit small) functions, which makes it IMHO a
maintainance nightmare whenever one wants to change something important
in the compiler. Take e.g. the recent Andreas Schwab's change to make
-fasynchronous-unwind-tables the default on riscv, even that change required
quite a few changes. My worry is that with these kind of tests changes like
that will become much harder and some people will simply decide not to do
such changes because having to adjust tens of thousands of tests even with
some scripting would be a nightmare. Can't we do better than this?
E.g. what is the difference between gcc.target/riscv/rvv/ and
g++.target/riscv/rvv/ tests? Are the <riscv_vector.h> APIs so different
between C and C++ that it needs to be tested twice? Even if so,
we have the concept of c-c++-common tests, we could add c-c++-common.target
and make riscv.exp handle it similarly to how e.g. C and C++ dg.exp handles
those. How do you create these tests? If you use some generator for them,
wouldn't it be better to include the generator in the testsuite and generate
them on the fly? We already have a precedent for that, e.g. the
gcc/testsuite/g*.dg/compat/struct-layout-1.exp testsuite has a generator
program written in C that creates tests on the fly. Now, using something
like that would have 2 advantages, it would be much easier for maintainance,
if you do some global change in the compiler that affects those tests, just
adjust a few spots in the generator instead of tweaking currently 6000 tests
and counting. Even if you aren't using a generator to write these tests
(that would be a lot of work then!), a question is if it couldn't be done by
one, have say some file like gcc has *.def files all around to describe what
you want to test and something that generates those.
Just wanted to chime in before we have 10 times more of such tests and it
will be too late to adjust...
On Thu, Feb 16, 2023 at 11:36:19AM +0800, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vmand_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmand_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmand_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmandn_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmandn_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmandn_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmclr_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmclr_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmclr_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmmv_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmmv_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmmv_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmnand_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmnand_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmnand_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmnor_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmnor_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmnor_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmnot_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmnot_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmnot_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmor_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmor_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmor_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmorn_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmorn_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmorn_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vmset_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmset_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmset_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vmxnor_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmxnor_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmxnor_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmxor_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmxor_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmxor_mm-3.c: New test.
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Re: [PATCH] RISC-V: Add vm* mask C api tests
2023-02-16 9:38 ` Jakub Jelinek
@ 2023-02-16 9:53 ` juzhe.zhong
2023-02-16 10:20 ` Jakub Jelinek
0 siblings, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2023-02-16 9:53 UTC (permalink / raw)
To: jakub; +Cc: gcc-patches, kito.cheng, jeffreyalaw
[-- Attachment #1: Type: text/plain, Size: 7757 bytes --]
Thanks for reporting this. I think may be we can make reduce tests into 1/3.
For example:
We have:
* gcc.target/riscv/rvv/base/vmand_mm-1.c: New test.
* gcc.target/riscv/rvv/base/vmand_mm-2.c: New test.
* gcc.target/riscv/rvv/base/vmand_mm-3.c: New test.
Maybe we can reduce it into one test:
vmand_mm.c only.
I will improve and reduce all intrinsic tests like this soon (I almost done all intrinsic in this week, next week I will do this soon).
RVV intrinsics are really huge, this is the document:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/auto-generated
The testcases are directly come from LLVM (We just add assembler check into the test), they also have this amount of testcases and the just recently change them:
https://reviews.llvm.org/D142697
https://reviews.llvm.org/D142644
Take a look at the changing LLVM patch, I am aggree with you ,the LLVM patch is quite huge and not easy to maintain.
So...... I think I can reduce the tests into 1/3 of them in the next. But it's still very big (you can take a look at LLVM).
Let's see whether kito has more comments about it.
juzhe.zhong@rivai.ai
From: Jakub Jelinek
Date: 2023-02-16 17:38
To: juzhe.zhong
CC: gcc-patches; kito.cheng; Jeff Law
Subject: Re: [PATCH] RISC-V: Add vm* mask C api tests
Hi!
I see in the past few weeks you've added huge amounts of these tests
du -shc *.target/riscv/*/
34M gcc.target/riscv/rvv/
28M g++.target/riscv/rvv/
61M total
and new are coming (nothing at all at this year's start).
This is far larger than tests of any other architecture
(i386 has 35M total, aarch64 31M total, arm 17M total, powerpc 12M total,
everything else is even much smaller) but for the other architectures it has
been decades of testsuite coverage for features added over the years.
Rather than looking purely at size, I'm more worried about the content
of the tests. Usually target testsuites include runtime tests whether
particular intrinsics etc. behave correctly at runtime, plus some compile
tests that they can be compiled with occassional scan-assembler* to mention
a particular instruction appears, but in these cases the scan-assembler*
covers the entire (albeit small) functions, which makes it IMHO a
maintainance nightmare whenever one wants to change something important
in the compiler. Take e.g. the recent Andreas Schwab's change to make
-fasynchronous-unwind-tables the default on riscv, even that change required
quite a few changes. My worry is that with these kind of tests changes like
that will become much harder and some people will simply decide not to do
such changes because having to adjust tens of thousands of tests even with
some scripting would be a nightmare. Can't we do better than this?
E.g. what is the difference between gcc.target/riscv/rvv/ and
g++.target/riscv/rvv/ tests? Are the <riscv_vector.h> APIs so different
between C and C++ that it needs to be tested twice? Even if so,
we have the concept of c-c++-common tests, we could add c-c++-common.target
and make riscv.exp handle it similarly to how e.g. C and C++ dg.exp handles
those. How do you create these tests? If you use some generator for them,
wouldn't it be better to include the generator in the testsuite and generate
them on the fly? We already have a precedent for that, e.g. the
gcc/testsuite/g*.dg/compat/struct-layout-1.exp testsuite has a generator
program written in C that creates tests on the fly. Now, using something
like that would have 2 advantages, it would be much easier for maintainance,
if you do some global change in the compiler that affects those tests, just
adjust a few spots in the generator instead of tweaking currently 6000 tests
and counting. Even if you aren't using a generator to write these tests
(that would be a lot of work then!), a question is if it couldn't be done by
one, have say some file like gcc has *.def files all around to describe what
you want to test and something that generates those.
Just wanted to chime in before we have 10 times more of such tests and it
will be too late to adjust...
On Thu, Feb 16, 2023 at 11:36:19AM +0800, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vmand_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmand_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmand_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmandn_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmandn_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmandn_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmclr_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmclr_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmclr_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmmv_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmmv_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmmv_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmnand_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmnand_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmnand_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmnor_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmnor_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmnor_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmnot_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmnot_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmnot_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmor_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmor_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmor_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmorn_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmorn_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmorn_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vmset_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmset_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmset_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsif_m_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmsof_m_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vmxnor_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmxnor_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmxnor_mm-3.c: New test.
> * gcc.target/riscv/rvv/base/vmxor_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmxor_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmxor_mm-3.c: New test.
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Re: [PATCH] RISC-V: Add vm* mask C api tests
2023-02-16 9:53 ` juzhe.zhong
@ 2023-02-16 10:20 ` Jakub Jelinek
2023-02-16 10:31 ` juzhe.zhong
0 siblings, 1 reply; 6+ messages in thread
From: Jakub Jelinek @ 2023-02-16 10:20 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, kito.cheng, jeffreyalaw
On Thu, Feb 16, 2023 at 05:53:48PM +0800, juzhe.zhong@rivai.ai wrote:
> Thanks for reporting this. I think may be we can make reduce tests into 1/3.
> For example:
> We have:
> * gcc.target/riscv/rvv/base/vmand_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmand_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmand_mm-3.c: New test.
>
> Maybe we can reduce it into one test:
> vmand_mm.c only.
>
> I will improve and reduce all intrinsic tests like this soon (I almost done all intrinsic in this week, next week I will do this soon).
>
> RVV intrinsics are really huge, this is the document:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/auto-generated
>
> The testcases are directly come from LLVM (We just add assembler check into the test), they also have this amount of testcases and the just recently change them:
> https://reviews.llvm.org/D142697
> https://reviews.llvm.org/D142644
>
> Take a look at the changing LLVM patch, I am aggree with you ,the LLVM patch is quite huge and not easy to maintain.
Yeah, LLVM does this all the time, their unit-tests where they embed e.g.
matchers for IL in huge tests.
I just think the way they are doing this is a very bad idea.
If say one writes some C/C++ test, compile it, some helper program
adds the IL into comments in the test then again any time you want to
adjust something in the compiler that affects those tests, you need to
regenerate them. Is the generator included somewhere, or does every
user write his own tooling to do that? Anyway, if the solution is
regenerate the IL, the test lost quite lot of its meaning, because
when changing thousands of tests and regenerating the IL for all of them,
one can hardly expect to carefully examine the changes to all those tests
whether everything was intended.
In GCC we have far fewer such unit-tests and big parts of the testsuite
are testing everything from parsing through assembly through linking through
runtime. In my experience over the years, many such tests can discover even
bugs completely unrelated to the original reason why a test has been added.
If they have some generator in LLVM for these riscv tests, even worse,
there is another step for LLVM generator regenerates them on the LLVM side
and somebody needs to reimport them into GCC and regenerate the
scan-assembler regexps.
riscv already uses what various other GCC backends use for builtins and
intrinsics, various *.def files from which the actual support is created.
So, can't we use the same files + something on top of that to have the
testsuite coverage, or if it should be independent from it, at least
have something similar which would describe intrinsic that should be tested,
iterate over such and such types for which arguments and how to come up with
the expected emitted code.
So, rather than reducing the tests into 1/3, try to reduce them to one
line per intrinsic or something of that scale.
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Re: [PATCH] RISC-V: Add vm* mask C api tests
2023-02-16 10:20 ` Jakub Jelinek
@ 2023-02-16 10:31 ` juzhe.zhong
2023-02-16 13:10 ` Kito Cheng
0 siblings, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2023-02-16 10:31 UTC (permalink / raw)
To: jakub; +Cc: gcc-patches, kito.cheng, jeffreyalaw
[-- Attachment #1: Type: text/plain, Size: 4084 bytes --]
Well, I think the best solution:
1. Remove all intrinsic test that I already commited.
2. Then, embed test-generator for this intrinsic unit-test.
3. Call test-generator during regression and test them.
4. Remove the testcases generated by the test-generator after regression.
Not sure whether you aggree with me.
The test-generator I used is generating the testcase by reading the rvv-intrinsic document directly and generate the testcases.
That means I need to commit test-generator and rvv-intrinsic document both.
I don't think my test-generator is good to commit.
I believe Kito has the mature and better test-generator (much better than mine) to commit since rvv-intrinsic doc is their work.
As long as we can make kito's test-generator embedded into GCC regression, this issue will be fixed. And I believe we can fix it soon.
So...Let's wait for kito.
juzhe.zhong@rivai.ai
From: Jakub Jelinek
Date: 2023-02-16 18:20
To: juzhe.zhong@rivai.ai
CC: gcc-patches; kito.cheng; jeffreyalaw
Subject: Re: Re: [PATCH] RISC-V: Add vm* mask C api tests
On Thu, Feb 16, 2023 at 05:53:48PM +0800, juzhe.zhong@rivai.ai wrote:
> Thanks for reporting this. I think may be we can make reduce tests into 1/3.
> For example:
> We have:
> * gcc.target/riscv/rvv/base/vmand_mm-1.c: New test.
> * gcc.target/riscv/rvv/base/vmand_mm-2.c: New test.
> * gcc.target/riscv/rvv/base/vmand_mm-3.c: New test.
>
> Maybe we can reduce it into one test:
> vmand_mm.c only.
>
> I will improve and reduce all intrinsic tests like this soon (I almost done all intrinsic in this week, next week I will do this soon).
>
> RVV intrinsics are really huge, this is the document:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/auto-generated
>
> The testcases are directly come from LLVM (We just add assembler check into the test), they also have this amount of testcases and the just recently change them:
> https://reviews.llvm.org/D142697
> https://reviews.llvm.org/D142644
>
> Take a look at the changing LLVM patch, I am aggree with you ,the LLVM patch is quite huge and not easy to maintain.
Yeah, LLVM does this all the time, their unit-tests where they embed e.g.
matchers for IL in huge tests.
I just think the way they are doing this is a very bad idea.
If say one writes some C/C++ test, compile it, some helper program
adds the IL into comments in the test then again any time you want to
adjust something in the compiler that affects those tests, you need to
regenerate them. Is the generator included somewhere, or does every
user write his own tooling to do that? Anyway, if the solution is
regenerate the IL, the test lost quite lot of its meaning, because
when changing thousands of tests and regenerating the IL for all of them,
one can hardly expect to carefully examine the changes to all those tests
whether everything was intended.
In GCC we have far fewer such unit-tests and big parts of the testsuite
are testing everything from parsing through assembly through linking through
runtime. In my experience over the years, many such tests can discover even
bugs completely unrelated to the original reason why a test has been added.
If they have some generator in LLVM for these riscv tests, even worse,
there is another step for LLVM generator regenerates them on the LLVM side
and somebody needs to reimport them into GCC and regenerate the
scan-assembler regexps.
riscv already uses what various other GCC backends use for builtins and
intrinsics, various *.def files from which the actual support is created.
So, can't we use the same files + something on top of that to have the
testsuite coverage, or if it should be independent from it, at least
have something similar which would describe intrinsic that should be tested,
iterate over such and such types for which arguments and how to come up with
the expected emitted code.
So, rather than reducing the tests into 1/3, try to reduce them to one
line per intrinsic or something of that scale.
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Re: [PATCH] RISC-V: Add vm* mask C api tests
2023-02-16 10:31 ` juzhe.zhong
@ 2023-02-16 13:10 ` Kito Cheng
0 siblings, 0 replies; 6+ messages in thread
From: Kito Cheng @ 2023-02-16 13:10 UTC (permalink / raw)
To: juzhe.zhong; +Cc: jakub, gcc-patches, jeffreyalaw
TL;DR: I think most parts of the test could be added by generator
instead of adding those test cases directly, we gonna stop putting all
API testing testcase.
RISC-V Vector intrinsic is not implement through the *.def file way,
it's using same approach as SVE's intrinsic,
create and register by C files, the reason is RISC-V vector has a huge
set for the intrinsic function:
about ~80k function for different combinations.
So that result we have so huge testcase set, and let me break down that
There are several kinds for those testcase:
1. vsetvli insertion pass testing, which is a highly customized mode
switching pass
2. Code gen test: testing our move pattern and generated code has
satisfied the RISC-V vector ISA constraint.
3. Intrinsic API testing: test the C intrinsic has right interface and
generated expected instruction
---
FIrst part has 375 testcase in `testsuite/gcc.target/riscv/rvv/vsetvl`
which is important and ~16M
but one potential issue is that is highly code gen sensitive, we've
added many long scan-assembly in the test file,
it's not ideal and we plan to implement a builtin verifier inside GCC
instead of lots of long scan-assembly,
This is planned for this year, but will happen after GCC 13 release.
---
Second part is also important, and only 300~400 files, so I think this
part should just keep as it is.
---
The last part is the most huge part in the testcases (~3000 files so
far), and I think we should consider removing this part from the GCC
testsuite,
since we have a standard one[1] from the RISC-V international.
So my thought is we stop putting further intrinsic API testing now,
and use the external one,
and evaluate the effort and benefit of implementing a test generator
inside GCC in future (after GCC 13 release).
[1] https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/auto-generated/api-testing/
On Thu, Feb 16, 2023 at 6:32 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> Well, I think the best solution:
> 1. Remove all intrinsic test that I already commited.
> 2. Then, embed test-generator for this intrinsic unit-test.
> 3. Call test-generator during regression and test them.
> 4. Remove the testcases generated by the test-generator after regression.
>
> Not sure whether you aggree with me.
>
> The test-generator I used is generating the testcase by reading the rvv-intrinsic document directly and generate the testcases.
> That means I need to commit test-generator and rvv-intrinsic document both.
> I don't think my test-generator is good to commit.
>
> I believe Kito has the mature and better test-generator (much better than mine) to commit since rvv-intrinsic doc is their work.
>
> As long as we can make kito's test-generator embedded into GCC regression, this issue will be fixed. And I believe we can fix it soon.
>
> So...Let's wait for kito.
>
>
> juzhe.zhong@rivai.ai
>
> From: Jakub Jelinek
> Date: 2023-02-16 18:20
> To: juzhe.zhong@rivai.ai
> CC: gcc-patches; kito.cheng; jeffreyalaw
> Subject: Re: Re: [PATCH] RISC-V: Add vm* mask C api tests
> On Thu, Feb 16, 2023 at 05:53:48PM +0800, juzhe.zhong@rivai.ai wrote:
> > Thanks for reporting this. I think may be we can make reduce tests into 1/3.
> > For example:
> > We have:
> > * gcc.target/riscv/rvv/base/vmand_mm-1.c: New test.
> > * gcc.target/riscv/rvv/base/vmand_mm-2.c: New test.
> > * gcc.target/riscv/rvv/base/vmand_mm-3.c: New test.
> >
> > Maybe we can reduce it into one test:
> > vmand_mm.c only.
> >
> > I will improve and reduce all intrinsic tests like this soon (I almost done all intrinsic in this week, next week I will do this soon).
> >
> > RVV intrinsics are really huge, this is the document:
> > https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/auto-generated
> >
> > The testcases are directly come from LLVM (We just add assembler check into the test), they also have this amount of testcases and the just recently change them:
> > https://reviews.llvm.org/D142697
> > https://reviews.llvm.org/D142644
> >
> > Take a look at the changing LLVM patch, I am aggree with you ,the LLVM patch is quite huge and not easy to maintain.
>
> Yeah, LLVM does this all the time, their unit-tests where they embed e.g.
> matchers for IL in huge tests.
>
> I just think the way they are doing this is a very bad idea.
> If say one writes some C/C++ test, compile it, some helper program
> adds the IL into comments in the test then again any time you want to
> adjust something in the compiler that affects those tests, you need to
> regenerate them. Is the generator included somewhere, or does every
> user write his own tooling to do that? Anyway, if the solution is
> regenerate the IL, the test lost quite lot of its meaning, because
> when changing thousands of tests and regenerating the IL for all of them,
> one can hardly expect to carefully examine the changes to all those tests
> whether everything was intended.
>
> In GCC we have far fewer such unit-tests and big parts of the testsuite
> are testing everything from parsing through assembly through linking through
> runtime. In my experience over the years, many such tests can discover even
> bugs completely unrelated to the original reason why a test has been added.
>
> If they have some generator in LLVM for these riscv tests, even worse,
> there is another step for LLVM generator regenerates them on the LLVM side
> and somebody needs to reimport them into GCC and regenerate the
> scan-assembler regexps.
>
> riscv already uses what various other GCC backends use for builtins and
> intrinsics, various *.def files from which the actual support is created.
> So, can't we use the same files + something on top of that to have the
> testsuite coverage, or if it should be independent from it, at least
> have something similar which would describe intrinsic that should be tested,
> iterate over such and such types for which arguments and how to come up with
> the expected emitted code.
> So, rather than reducing the tests into 1/3, try to reduce them to one
> line per intrinsic or something of that scale.
>
> Jakub
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-02-16 13:10 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-02-16 3:36 [PATCH] RISC-V: Add vm* mask C api tests juzhe.zhong
2023-02-16 9:38 ` Jakub Jelinek
2023-02-16 9:53 ` juzhe.zhong
2023-02-16 10:20 ` Jakub Jelinek
2023-02-16 10:31 ` juzhe.zhong
2023-02-16 13:10 ` Kito Cheng
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