* [PATCH] RISC-V: Fix ugly && incorrect codes of RVV auto-vectorization
@ 2023-05-08 3:41 juzhe.zhong
2023-05-08 7:01 ` Kito Cheng
0 siblings, 1 reply; 2+ messages in thread
From: juzhe.zhong @ 2023-05-08 3:41 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, jeffreyalaw, rdapp.gcc, Juzhe-Zhong
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=all, Size: 8475 bytes --]
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
1. Add movmisalign pattern for TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
targethook, current RISC-V has supported this target hook, we can't make
it supported without movmisalign pattern.
2. Remove global extern of get_mask_policy_no_pred && get_tail_policy_no_pred.
These 2 functions are comming from intrinsic builtin frameworks.
We are sure we don't need them in auto-vectorization implementation.
3. Refine mask mode implementation.
4. We should not have "riscv_vector_" in riscv_vector namspace since it
makes the codes inconsistent and ugly.
For example:
Before this patch:
static opt_machine_mode
riscv_get_mask_mode (machine_mode mode)
{
machine_mode mask_mode = VOIDmode;
if (TARGET_VECTOR && riscv_vector::riscv_vector_get_mask_mode (mode).exists (&mask_mode))
return mask_mode;
..
After this patch:
riscv_get_mask_mode (machine_mode mode)
{
machine_mode mask_mode = VOIDmode;
if (TARGET_VECTOR && riscv_vector::get_mask_mode (mode).exists (&mask_mode))
return mask_mode;
..
5. Fix fail testcase fixed-vlmax-1.c.
gcc/ChangeLog:
* config/riscv/autovec.md (movmisalign<mode>): New pattern.
* config/riscv/riscv-protos.h (riscv_vector_mask_mode_p): Delete.
(riscv_vector_get_mask_mode): Ditto.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(get_mask_mode): New function.
* config/riscv/riscv-v.cc (get_mask_policy_no_pred): Delete.
(get_tail_policy_no_pred): Ditto.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
(get_mask_mode): New function.
* config/riscv/riscv-vector-builtins.cc (use_real_merge_p): Remove global extern.
(get_tail_policy_for_pred): Ditto.
* config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred): Ditto.
(get_mask_policy_for_pred): Ditto
* config/riscv/riscv.cc (riscv_get_mask_mode): Refine codes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Fix typo.
---
gcc/config/riscv/autovec.md | 11 ++++++
gcc/config/riscv/riscv-protos.h | 5 +--
gcc/config/riscv/riscv-v.cc | 36 ++-----------------
gcc/config/riscv/riscv-vector-builtins.cc | 4 +--
gcc/config/riscv/riscv-vector-builtins.h | 3 --
gcc/config/riscv/riscv.cc | 3 +-
.../riscv/rvv/autovec/fixed-vlmax-1.c | 4 +--
7 files changed, 19 insertions(+), 47 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b5d46ff57ab..f1c5ff5951b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -47,3 +47,14 @@
operands[1], operands[2], <VM>mode);
DONE;
})
+
+(define_expand "movmisalign<mode>"
+ [(set (match_operand:V 0 "nonimmediate_operand")
+ (match_operand:V 1 "general_operand"))]
+ "TARGET_VECTOR"
+ {
+ /* Equivalent to a normal move for our purpooses. */
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+ }
+)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index d83ea2c77e4..c0293a306f9 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -218,10 +218,7 @@ bool slide1_sew64_helper (int, machine_mode, machine_mode,
rtx gen_avl_for_scalar_move (rtx);
void expand_tuple_move (machine_mode, rtx *);
machine_mode preferred_simd_mode (scalar_mode);
-extern bool riscv_vector_mask_mode_p (machine_mode);
-extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
-extern rtx get_mask_policy_no_pred (void);
-extern rtx get_tail_policy_no_pred (void);
+opt_machine_mode get_mask_mode (machine_mode);
}
/* We classify builtin types into two classes:
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 8c7f3206771..7ca49ca67c1 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -43,7 +43,6 @@
#include "expr.h"
#include "optabs.h"
#include "tm-constrs.h"
-#include "riscv-vector-builtins.h"
#include "rtx-vector-builder.h"
#include "targhooks.h"
@@ -479,43 +478,12 @@ get_avl_type_rtx (enum avl_type type)
return gen_int_mode (type, Pmode);
}
-/* Return the mask policy for no predication. */
-rtx
-get_mask_policy_no_pred (void)
-{
- return get_mask_policy_for_pred (PRED_TYPE_none);
-}
-
-/* Return the tail policy for no predication. */
-rtx
-get_tail_policy_no_pred (void)
-{
- return get_tail_policy_for_pred (PRED_TYPE_none);
-}
-
-/* Return true if it is a RVV mask mode. */
-bool
-riscv_vector_mask_mode_p (machine_mode mode)
-{
- return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode
- || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode
- || mode == VNx64BImode);
-}
-
/* Return the appropriate mask mode for MODE. */
opt_machine_mode
-riscv_vector_get_mask_mode (machine_mode mode)
+get_mask_mode (machine_mode mode)
{
- machine_mode mask_mode;
- int nf = 1;
-
- FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL)
- if (GET_MODE_INNER (mask_mode) == BImode
- && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode))
- && riscv_vector_mask_mode_p (mask_mode))
- return mask_mode;
- return default_get_mask_mode (mode);
+ return get_vector_mode (BImode, GET_MODE_NUNITS (mode));
}
/* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE.
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 01d7958f3b8..4117897c6c9 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2705,7 +2705,7 @@ use_real_merge_p (enum predication_type_index pred)
/* Get TAIL policy for predication. If predication indicates TU, return the TU.
Otherwise, return the prefer default configuration. */
-rtx
+static rtx
get_tail_policy_for_pred (enum predication_type_index pred)
{
if (pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu)
@@ -2715,7 +2715,7 @@ get_tail_policy_for_pred (enum predication_type_index pred)
/* Get MASK policy for predication. If predication indicates MU, return the MU.
Otherwise, return the prefer default configuration. */
-rtx
+static rtx
get_mask_policy_for_pred (enum predication_type_index pred)
{
if (pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu)
diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h
index 2ed727e03b1..b024731e37a 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -486,9 +486,6 @@ extern rvv_builtin_types_t builtin_types[NUM_VECTOR_TYPES + 1];
extern function_instance get_read_vl_instance (void);
extern tree get_read_vl_decl (void);
-extern rtx get_tail_policy_for_pred (enum predication_type_index pred);
-extern rtx get_mask_policy_for_pred (enum predication_type_index pred);
-
inline tree
rvv_arg_type_info::get_scalar_type (vector_type_index type_idx) const
{
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 87ae84e7667..8684271f8ac 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7295,8 +7295,7 @@ static opt_machine_mode
riscv_get_mask_mode (machine_mode mode)
{
machine_mode mask_mode = VOIDmode;
- if (TARGET_VECTOR
- && riscv_vector::riscv_vector_get_mask_mode (mode).exists (&mask_mode))
+ if (TARGET_VECTOR && riscv_vector::get_mask_mode (mode).exists (&mask_mode))
return mask_mode;
return default_get_mask_mode (mode);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
index b15e98c7807..09e8396936e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
@@ -11,11 +11,11 @@ void stack_check_alloca_1 (vuint8m1_t data, uint8_t *base, int y, ...)
asm volatile ("nop"
: "=vr" (v0), "=vr" (v8), "=vr" (v16), "=vr" (v24)
:
- 😄;
+ :);
asm volatile ("nop"
:
: "vr" (v0), "vr" (v8), "vr" (v16), "vr" (v24)
- 😄;
+ :);
*(vuint8m1_t *)base = data;
char* pStr = (char*)__builtin_alloca(y);
f(pStr);
--
2.36.3
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] RISC-V: Fix ugly && incorrect codes of RVV auto-vectorization
2023-05-08 3:41 [PATCH] RISC-V: Fix ugly && incorrect codes of RVV auto-vectorization juzhe.zhong
@ 2023-05-08 7:01 ` Kito Cheng
0 siblings, 0 replies; 2+ messages in thread
From: Kito Cheng @ 2023-05-08 7:01 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, palmer, jeffreyalaw, rdapp.gcc
Committed to trunk, thanks!
On Mon, May 8, 2023 at 11:42 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> 1. Add movmisalign pattern for TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
> targethook, current RISC-V has supported this target hook, we can't make
> it supported without movmisalign pattern.
>
> 2. Remove global extern of get_mask_policy_no_pred && get_tail_policy_no_pred.
> These 2 functions are comming from intrinsic builtin frameworks.
> We are sure we don't need them in auto-vectorization implementation.
>
> 3. Refine mask mode implementation.
>
> 4. We should not have "riscv_vector_" in riscv_vector namspace since it
> makes the codes inconsistent and ugly.
>
> For example:
> Before this patch:
> static opt_machine_mode
> riscv_get_mask_mode (machine_mode mode)
> {
> machine_mode mask_mode = VOIDmode;
> if (TARGET_VECTOR && riscv_vector::riscv_vector_get_mask_mode (mode).exists (&mask_mode))
> return mask_mode;
> ..
>
> After this patch:
> riscv_get_mask_mode (machine_mode mode)
> {
> machine_mode mask_mode = VOIDmode;
> if (TARGET_VECTOR && riscv_vector::get_mask_mode (mode).exists (&mask_mode))
> return mask_mode;
> ..
>
> 5. Fix fail testcase fixed-vlmax-1.c.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (movmisalign<mode>): New pattern.
> * config/riscv/riscv-protos.h (riscv_vector_mask_mode_p): Delete.
> (riscv_vector_get_mask_mode): Ditto.
> (get_mask_policy_no_pred): Ditto.
> (get_tail_policy_no_pred): Ditto.
> (get_mask_mode): New function.
> * config/riscv/riscv-v.cc (get_mask_policy_no_pred): Delete.
> (get_tail_policy_no_pred): Ditto.
> (riscv_vector_mask_mode_p): Ditto.
> (riscv_vector_get_mask_mode): Ditto.
> (get_mask_mode): New function.
> * config/riscv/riscv-vector-builtins.cc (use_real_merge_p): Remove global extern.
> (get_tail_policy_for_pred): Ditto.
> * config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred): Ditto.
> (get_mask_policy_for_pred): Ditto
> * config/riscv/riscv.cc (riscv_get_mask_mode): Refine codes.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Fix typo.
>
> ---
> gcc/config/riscv/autovec.md | 11 ++++++
> gcc/config/riscv/riscv-protos.h | 5 +--
> gcc/config/riscv/riscv-v.cc | 36 ++-----------------
> gcc/config/riscv/riscv-vector-builtins.cc | 4 +--
> gcc/config/riscv/riscv-vector-builtins.h | 3 --
> gcc/config/riscv/riscv.cc | 3 +-
> .../riscv/rvv/autovec/fixed-vlmax-1.c | 4 +--
> 7 files changed, 19 insertions(+), 47 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index b5d46ff57ab..f1c5ff5951b 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -47,3 +47,14 @@
> operands[1], operands[2], <VM>mode);
> DONE;
> })
> +
> +(define_expand "movmisalign<mode>"
> + [(set (match_operand:V 0 "nonimmediate_operand")
> + (match_operand:V 1 "general_operand"))]
> + "TARGET_VECTOR"
> + {
> + /* Equivalent to a normal move for our purpooses. */
> + emit_move_insn (operands[0], operands[1]);
> + DONE;
> + }
> +)
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index d83ea2c77e4..c0293a306f9 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -218,10 +218,7 @@ bool slide1_sew64_helper (int, machine_mode, machine_mode,
> rtx gen_avl_for_scalar_move (rtx);
> void expand_tuple_move (machine_mode, rtx *);
> machine_mode preferred_simd_mode (scalar_mode);
> -extern bool riscv_vector_mask_mode_p (machine_mode);
> -extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
> -extern rtx get_mask_policy_no_pred (void);
> -extern rtx get_tail_policy_no_pred (void);
> +opt_machine_mode get_mask_mode (machine_mode);
> }
>
> /* We classify builtin types into two classes:
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 8c7f3206771..7ca49ca67c1 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -43,7 +43,6 @@
> #include "expr.h"
> #include "optabs.h"
> #include "tm-constrs.h"
> -#include "riscv-vector-builtins.h"
> #include "rtx-vector-builder.h"
> #include "targhooks.h"
>
> @@ -479,43 +478,12 @@ get_avl_type_rtx (enum avl_type type)
> return gen_int_mode (type, Pmode);
> }
>
> -/* Return the mask policy for no predication. */
> -rtx
> -get_mask_policy_no_pred (void)
> -{
> - return get_mask_policy_for_pred (PRED_TYPE_none);
> -}
> -
> -/* Return the tail policy for no predication. */
> -rtx
> -get_tail_policy_no_pred (void)
> -{
> - return get_tail_policy_for_pred (PRED_TYPE_none);
> -}
> -
> -/* Return true if it is a RVV mask mode. */
> -bool
> -riscv_vector_mask_mode_p (machine_mode mode)
> -{
> - return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode
> - || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode
> - || mode == VNx64BImode);
> -}
> -
> /* Return the appropriate mask mode for MODE. */
>
> opt_machine_mode
> -riscv_vector_get_mask_mode (machine_mode mode)
> +get_mask_mode (machine_mode mode)
> {
> - machine_mode mask_mode;
> - int nf = 1;
> -
> - FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL)
> - if (GET_MODE_INNER (mask_mode) == BImode
> - && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode))
> - && riscv_vector_mask_mode_p (mask_mode))
> - return mask_mode;
> - return default_get_mask_mode (mode);
> + return get_vector_mode (BImode, GET_MODE_NUNITS (mode));
> }
>
> /* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE.
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index 01d7958f3b8..4117897c6c9 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -2705,7 +2705,7 @@ use_real_merge_p (enum predication_type_index pred)
>
> /* Get TAIL policy for predication. If predication indicates TU, return the TU.
> Otherwise, return the prefer default configuration. */
> -rtx
> +static rtx
> get_tail_policy_for_pred (enum predication_type_index pred)
> {
> if (pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu)
> @@ -2715,7 +2715,7 @@ get_tail_policy_for_pred (enum predication_type_index pred)
>
> /* Get MASK policy for predication. If predication indicates MU, return the MU.
> Otherwise, return the prefer default configuration. */
> -rtx
> +static rtx
> get_mask_policy_for_pred (enum predication_type_index pred)
> {
> if (pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu)
> diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h
> index 2ed727e03b1..b024731e37a 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.h
> +++ b/gcc/config/riscv/riscv-vector-builtins.h
> @@ -486,9 +486,6 @@ extern rvv_builtin_types_t builtin_types[NUM_VECTOR_TYPES + 1];
> extern function_instance get_read_vl_instance (void);
> extern tree get_read_vl_decl (void);
>
> -extern rtx get_tail_policy_for_pred (enum predication_type_index pred);
> -extern rtx get_mask_policy_for_pred (enum predication_type_index pred);
> -
> inline tree
> rvv_arg_type_info::get_scalar_type (vector_type_index type_idx) const
> {
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 87ae84e7667..8684271f8ac 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7295,8 +7295,7 @@ static opt_machine_mode
> riscv_get_mask_mode (machine_mode mode)
> {
> machine_mode mask_mode = VOIDmode;
> - if (TARGET_VECTOR
> - && riscv_vector::riscv_vector_get_mask_mode (mode).exists (&mask_mode))
> + if (TARGET_VECTOR && riscv_vector::get_mask_mode (mode).exists (&mask_mode))
> return mask_mode;
>
> return default_get_mask_mode (mode);
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
> index b15e98c7807..09e8396936e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
> @@ -11,11 +11,11 @@ void stack_check_alloca_1 (vuint8m1_t data, uint8_t *base, int y, ...)
> asm volatile ("nop"
> : "=vr" (v0), "=vr" (v8), "=vr" (v16), "=vr" (v24)
> :
> - 😄;
> + :);
> asm volatile ("nop"
> :
> : "vr" (v0), "vr" (v8), "vr" (v16), "vr" (v24)
> - 😄;
> + :);
> *(vuint8m1_t *)base = data;
> char* pStr = (char*)__builtin_alloca(y);
> f(pStr);
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-05-08 3:41 [PATCH] RISC-V: Fix ugly && incorrect codes of RVV auto-vectorization juzhe.zhong
2023-05-08 7:01 ` Kito Cheng
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