From: Kito Cheng <kito.cheng@gmail.com>
To: "Maciej W. Rozycki" <macro@embecosm.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Andrew Waterman <andrew@sifive.com>
Subject: Re: [PING][PATCH v2] RISC-V: Split unordered FP comparisons into individual RTL insns
Date: Wed, 27 Jul 2022 18:40:48 +0800 [thread overview]
Message-ID: <CA+yXCZAOA8GaPVOTLDm3RvYcK-VNVgboMk9ZtJwps=HU=4e-XA@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.20.2207181639450.10833@tpp.orcam.me.uk>
Hi Maciej:
I am convinced that is OK for now, I agree modeling fflags would be a
rabbit hole, I tried to build a full GNU toolchain with my quick patch
and saw many ICE during build libraries, that definitely should be a
long-term optimization project.
Although I'm thinking if we should default -fno-trapping-math for
RISC-V, because RISC-V didn't trap for any floating point operations,
however I think that would be another topic.
so you got my LGTM :)
On Mon, Jul 18, 2022 at 11:43 PM Maciej W. Rozycki <macro@embecosm.com> wrote:
>
> On Mon, 4 Jul 2022, Maciej W. Rozycki wrote:
>
> > These instructions are only produced via an expander already, so change
> > the expander to emit individual RTL insns for each machine instruction
> > in the ultimate ultimate sequence produced rather than deferring to a
> > single RTL insn producing the whole sequence at once.
>
> Ping for:
>
> <https://gcc.gnu.org/pipermail/gcc-patches/2022-July/597767.html>
>
> Maciej
next prev parent reply other threads:[~2022-07-27 10:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-09 13:44 [PATCH] " Maciej W. Rozycki
2022-06-23 13:39 ` Maciej W. Rozycki
2022-06-23 16:44 ` Kito Cheng
2022-07-04 14:12 ` [PATCH v2] " Maciej W. Rozycki
2022-07-18 15:42 ` [PING][PATCH " Maciej W. Rozycki
2022-07-27 10:40 ` Kito Cheng [this message]
2022-07-28 13:20 ` Maciej W. Rozycki
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