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From: Kito Cheng <kito.cheng@gmail.com>
To: Mary Bennett <mary.bennett@embecosm.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P
Date: Tue, 5 Dec 2023 23:30:40 +0800	[thread overview]
Message-ID: <CA+yXCZAh6-iJDEXf_GcATAir-YjGE-594eT+xtmnW8UKGO6pRQ@mail.gmail.com> (raw)
In-Reply-To: <20231109105542.4013483-2-mary.bennett@embecosm.com>

> index 7d7b952d817..e7d4ad1760c 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -27,6 +27,25 @@
>
>    ;;CORE-V EVENT LOAD
>    UNSPECV_CV_ELW
> +
> +  ;;CORE-V BITMANIP
> +  UNSPEC_CV_BITMANIP_EXTRACT
> +  UNSPEC_CV_BITMANIP_EXTRACT_INSN
> +  UNSPEC_CV_BITMANIP_EXTRACTR_INSN
> +  UNSPEC_CV_BITMANIP_EXTRACTU
> +  UNSPEC_CV_BITMANIP_EXTRACTU_INSN
> +  UNSPEC_CV_BITMANIP_EXTRACTUR_INSN
> +  UNSPEC_CV_BITMANIP_INSERT
> +  UNSPEC_CV_BITMANIP_INSERT_INSN
> +  UNSPEC_CV_BITMANIP_INSERTR_INSN

You could reference bfe, sbfx and ubfx instructions in aarch64.md
to see how to write the insert and extract bit with RTL code.

> +  UNSPEC_CV_BITMANIP_BCLR
> +  UNSPEC_CV_BITMANIP_BCLR_INSN
> +  UNSPEC_CV_BITMANIP_BCLRR_INSN
> +  UNSPEC_CV_BITMANIP_BSET
> +  UNSPEC_CV_BITMANIP_BSET_INSN
> +  UNSPEC_CV_BITMANIP_BSETR_INSN

Just use generic RTL code for bset and bclr is fine, you could
reference bitmanip.md

> +  UNSPEC_CV_BITMANIP_BITREV
> +  UNSPEC_CV_BITMANIP_FL1
>  ])
>

  reply	other threads:[~2023-12-05 15:30 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-09 10:55 [PATCH 0/1] RISC-V: Support CORE-V XCVBITMAIP extension Mary Bennett
2023-11-09 10:55 ` [PATCH 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P Mary Bennett
2023-12-05 15:30   ` Kito Cheng [this message]
2023-12-06 17:59     ` Jeff Law

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