* [PATCH V1] RISC-V: Add mininal support for zabha extension.
@ 2024-02-06 9:17 shiyulong
2024-02-06 10:02 ` Kito Cheng
0 siblings, 1 reply; 2+ messages in thread
From: shiyulong @ 2024-02-06 9:17 UTC (permalink / raw)
To: gcc-patches
Cc: palmer, kito.cheng, wuwei2016, jiawei, shihua, chenyixuan,
dje.gcc, mirimmad, yulong
From: yulong <shiyulong@iscas.ac.cn>
This patch add the mininal support for zabha extension.
The doc url as follow: https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc
There are have no amocas.[b|h] instructions, because the zacas extension is not merged.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zabha extension name.
* config/riscv/riscv.md (amo_addqi3): New mode.
(amo_addhi3): Ditto.
(amo_minqi3): Ditto.
(amo_minuqi3): Ditto.
(amo_minhi3): Ditto.
(amo_minuhi3): Ditto.
(amo_maxqi3): Ditto.
(amo_maxuqi3): Ditto.
(amo_maxhi3): Ditto.
(amo_maxuhi3): Ditto.
(amo_andqi3): Ditto.
(amo_andhi3): Ditto.
(amo_orqi3): Ditto.
(amo_orhi3): Ditto.
(amo_xorqi3): Ditto.
(amo_xorhi3): Ditto.
(amo_swapqi3): Ditto.
(amo_swaphi3): Ditto.
* config/riscv/riscv.opt: Add zabha extension.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv.md | 167 ++++++++++++++++++++++++
gcc/config/riscv/riscv.opt | 2 +
3 files changed, 171 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 631ce8309a0..9c3be0d7651 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -250,6 +250,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"za64rs", ISA_SPEC_CLASS_NONE, 1, 0},
{"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1504,6 +1505,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
{"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
{"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
+ {"zabha", &gcc_options::x_riscv_za_subext, MASK_ZABHA},
{"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
{"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 39b29795cd6..058b63ac7f0 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -134,6 +134,9 @@
;; XTheadInt unspec
UNSPECV_XTHEADINT_PUSH
UNSPECV_XTHEADINT_POP
+
+ ;; Zabha instructions.
+ UNSPEC_AMO_SWAP
])
(define_constants
@@ -849,6 +852,24 @@
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
+(define_insn "amo_addqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r,r")
+ (plus:QI (match_operand:QI 1 "register_operand" " r,r")
+ (match_operand:QI 2 "arith_operand" " r,r")))]
+ "TARGET_ZABHA"
+ "amoadd.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_addhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r,r")
+ (plus:HI (match_operand:HI 1 "register_operand" " r,r")
+ (match_operand:HI 2 "arith_operand" " r,r")))]
+ "TARGET_ZABHA"
+ "amoadd.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
;;
;; ....................
;;
@@ -1645,6 +1666,78 @@
[(set_attr "type" "fmove")
(set_attr "mode" "<UNITMODE>")])
+(define_insn "amo_minqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (smin:QI (match_operand:QI 1 "register_operand" " r")
+ (match_operand:QI 2 "register_operand" " r")))]
+ "TARGET_ZABHA"
+ "amomin.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_minuqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (umin:QI (match_operand:QI 1 "register_operand" " r")
+ (match_operand:QI 2 "register_operand" " r")))]
+ "TARGET_ZABHA"
+ "amominu.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_minhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (smin:HI (match_operand:HI 1 "register_operand" " r")
+ (match_operand:HI 2 "register_operand" " r")))]
+ "TARGET_ZABHA"
+ "amomin.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
+(define_insn "amo_minuhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (umin:HI (match_operand:HI 1 "register_operand" " r")
+ (match_operand:HI 2 "register_operand" " r")))]
+ "TARGET_ZABHA"
+ "amominu.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
+(define_insn "amo_maxqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (smax:QI (match_operand:QI 1 "register_operand" " r")
+ (match_operand:QI 2 "register_operand" " r")))]
+ "TARGET_ZABHA"
+ "amomax.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_maxuqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (umax:QI (match_operand:QI 1 "register_operand" " r")
+ (match_operand:QI 2 "register_operand" " r")))]
+ "TARGET_ZABHA"
+ "amomaxu.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_maxhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (smax:HI (match_operand:HI 1 "register_operand" " r")
+ (match_operand:HI 2 "register_operand" " r")))]
+ "TARGET_ZABHA"
+ "amomax.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
+(define_insn "amo_maxuhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (umax:HI (match_operand:HI 1 "register_operand" " r")
+ (match_operand:HI 2 "register_operand" " r")))]
+ "TARGET_ZABHA"
+ "amomaxu.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
;;
;; ....................
;;
@@ -1690,6 +1783,24 @@
[(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
+(define_insn "amo_andqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r,r")
+ (and:QI (match_operand:QI 1 "register_operand" "r,r")
+ (match_operand:QI 2 "arith_operand" " r,r")))]
+ "TARGET_ZABHA"
+ "amoand.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_andhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r,r")
+ (and:HI (match_operand:HI 1 "register_operand" "r,r")
+ (match_operand:HI 2 "arith_operand" " r,r")))]
+ "TARGET_ZABHA"
+ "amoand.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
(define_insn "<optab><mode>3"
[(set (match_operand:X 0 "register_operand" "=r,r")
(any_or:X (match_operand:X 1 "register_operand" "%r,r")
@@ -1724,6 +1835,42 @@
[(set_attr "type" "logical")
(set_attr "mode" "SI")])
+(define_insn "amo_orqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r,r")
+ (ior:QI (match_operand:QI 1 "register_operand" " r,r")
+ (match_operand:QI 2 "arith_operand" " r,r")))]
+ "TARGET_ZABHA"
+ "amoor.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_orhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r,r")
+ (ior:HI (match_operand:HI 1 "register_operand" " r,r")
+ (match_operand:HI 2 "arith_operand" " r,r")))]
+ "TARGET_ZABHA"
+ "amoor.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
+(define_insn "amo_xorqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r,r")
+ (xor:QI (match_operand:QI 1 "register_operand" " r,r")
+ (match_operand:QI 2 "arith_operand" " r,r")))]
+ "TARGET_ZABHA"
+ "amoxor.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_xorhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r,r")
+ (xor:HI (match_operand:HI 1 "register_operand" " r,r")
+ (match_operand:HI 2 "arith_operand" " r,r")))]
+ "TARGET_ZABHA"
+ "amoxor.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
;;
;; ....................
;;
@@ -3841,6 +3988,26 @@
[(set_attr "type" "load")
(set (attr "length") (const_int 8))])
+(define_insn "amo_swapqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (unspec:QI [(match_operand:QI 1 "register_operand" "r")
+ (match_operand:QI 2 "register_operand" "r")]
+ UNSPEC_AMO_SWAP))]
+ "TARGET_ZABHA"
+ "amoswap.b\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "QI")])
+
+(define_insn "amo_swaphi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (unspec:HI [(match_operand:HI 1 "register_operand" "r")
+ (match_operand:HI 2 "register_operand" "r")]
+ UNSPEC_AMO_SWAP))]
+ "TARGET_ZABHA"
+ "amoswap.h\t%0,%1,%2"
+ [(set_attr "type" "atomic")
+ (set_attr "mode" "HI")])
+
(include "bitmanip.md")
(include "crypto.md")
(include "sync.md")
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index f6ff70b2b30..1136a5301ea 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -244,6 +244,8 @@ Mask(ZA64RS) Var(riscv_za_subext)
Mask(ZA128RS) Var(riscv_za_subext)
+Mask(ZABHA) Var(riscv_za_subext)
+
TargetVariable
int riscv_zb_subext
--
2.34.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH V1] RISC-V: Add mininal support for zabha extension.
2024-02-06 9:17 [PATCH V1] RISC-V: Add mininal support for zabha extension shiyulong
@ 2024-02-06 10:02 ` Kito Cheng
0 siblings, 0 replies; 2+ messages in thread
From: Kito Cheng @ 2024-02-06 10:02 UTC (permalink / raw)
To: shiyulong
Cc: gcc-patches, palmer, kito.cheng, wuwei2016, jiawei, shihua,
chenyixuan, dje.gcc, mirimmad
I am not sure it's worth adding a dedicated instruction pattern for
those instructions? In theory those instructions should just be used
by those atomic builin when zabha has enabled, but I think that would
be kinda of a bigger work item.
On Tue, Feb 6, 2024 at 5:18 PM <shiyulong@iscas.ac.cn> wrote:
>
> From: yulong <shiyulong@iscas.ac.cn>
>
> This patch add the mininal support for zabha extension.
> The doc url as follow: https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc
> There are have no amocas.[b|h] instructions, because the zacas extension is not merged.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add zabha extension name.
> * config/riscv/riscv.md (amo_addqi3): New mode.
> (amo_addhi3): Ditto.
> (amo_minqi3): Ditto.
> (amo_minuqi3): Ditto.
> (amo_minhi3): Ditto.
> (amo_minuhi3): Ditto.
> (amo_maxqi3): Ditto.
> (amo_maxuqi3): Ditto.
> (amo_maxhi3): Ditto.
> (amo_maxuhi3): Ditto.
> (amo_andqi3): Ditto.
> (amo_andhi3): Ditto.
> (amo_orqi3): Ditto.
> (amo_orhi3): Ditto.
> (amo_xorqi3): Ditto.
> (amo_xorhi3): Ditto.
> (amo_swapqi3): Ditto.
> (amo_swaphi3): Ditto.
> * config/riscv/riscv.opt: Add zabha extension.
>
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 +
> gcc/config/riscv/riscv.md | 167 ++++++++++++++++++++++++
> gcc/config/riscv/riscv.opt | 2 +
> 3 files changed, 171 insertions(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 631ce8309a0..9c3be0d7651 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -250,6 +250,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0},
> {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1504,6 +1505,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
> {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
> {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> + {"zabha", &gcc_options::x_riscv_za_subext, MASK_ZABHA},
>
> {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
> {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 39b29795cd6..058b63ac7f0 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -134,6 +134,9 @@
> ;; XTheadInt unspec
> UNSPECV_XTHEADINT_PUSH
> UNSPECV_XTHEADINT_POP
> +
> + ;; Zabha instructions.
> + UNSPEC_AMO_SWAP
> ])
>
> (define_constants
> @@ -849,6 +852,24 @@
> [(set_attr "type" "arith")
> (set_attr "mode" "SI")])
>
> +(define_insn "amo_addqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r,r")
> + (plus:QI (match_operand:QI 1 "register_operand" " r,r")
> + (match_operand:QI 2 "arith_operand" " r,r")))]
> + "TARGET_ZABHA"
> + "amoadd.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_addhi3"
> + [(set (match_operand:HI 0 "register_operand" "=r,r")
> + (plus:HI (match_operand:HI 1 "register_operand" " r,r")
> + (match_operand:HI 2 "arith_operand" " r,r")))]
> + "TARGET_ZABHA"
> + "amoadd.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> ;;
> ;; ....................
> ;;
> @@ -1645,6 +1666,78 @@
> [(set_attr "type" "fmove")
> (set_attr "mode" "<UNITMODE>")])
>
> +(define_insn "amo_minqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r")
> + (smin:QI (match_operand:QI 1 "register_operand" " r")
> + (match_operand:QI 2 "register_operand" " r")))]
> + "TARGET_ZABHA"
> + "amomin.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_minuqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r")
> + (umin:QI (match_operand:QI 1 "register_operand" " r")
> + (match_operand:QI 2 "register_operand" " r")))]
> + "TARGET_ZABHA"
> + "amominu.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_minhi3"
> + [(set (match_operand:HI 0 "register_operand" "=r")
> + (smin:HI (match_operand:HI 1 "register_operand" " r")
> + (match_operand:HI 2 "register_operand" " r")))]
> + "TARGET_ZABHA"
> + "amomin.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> +(define_insn "amo_minuhi3"
> + [(set (match_operand:HI 0 "register_operand" "=r")
> + (umin:HI (match_operand:HI 1 "register_operand" " r")
> + (match_operand:HI 2 "register_operand" " r")))]
> + "TARGET_ZABHA"
> + "amominu.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> +(define_insn "amo_maxqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r")
> + (smax:QI (match_operand:QI 1 "register_operand" " r")
> + (match_operand:QI 2 "register_operand" " r")))]
> + "TARGET_ZABHA"
> + "amomax.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_maxuqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r")
> + (umax:QI (match_operand:QI 1 "register_operand" " r")
> + (match_operand:QI 2 "register_operand" " r")))]
> + "TARGET_ZABHA"
> + "amomaxu.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_maxhi3"
> + [(set (match_operand:HI 0 "register_operand" "=r")
> + (smax:HI (match_operand:HI 1 "register_operand" " r")
> + (match_operand:HI 2 "register_operand" " r")))]
> + "TARGET_ZABHA"
> + "amomax.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> +(define_insn "amo_maxuhi3"
> + [(set (match_operand:HI 0 "register_operand" "=r")
> + (umax:HI (match_operand:HI 1 "register_operand" " r")
> + (match_operand:HI 2 "register_operand" " r")))]
> + "TARGET_ZABHA"
> + "amomaxu.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> ;;
> ;; ....................
> ;;
> @@ -1690,6 +1783,24 @@
> [(set_attr "type" "logical")
> (set_attr "mode" "<MODE>")])
>
> +(define_insn "amo_andqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r,r")
> + (and:QI (match_operand:QI 1 "register_operand" "r,r")
> + (match_operand:QI 2 "arith_operand" " r,r")))]
> + "TARGET_ZABHA"
> + "amoand.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_andhi3"
> + [(set (match_operand:HI 0 "register_operand" "=r,r")
> + (and:HI (match_operand:HI 1 "register_operand" "r,r")
> + (match_operand:HI 2 "arith_operand" " r,r")))]
> + "TARGET_ZABHA"
> + "amoand.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> (define_insn "<optab><mode>3"
> [(set (match_operand:X 0 "register_operand" "=r,r")
> (any_or:X (match_operand:X 1 "register_operand" "%r,r")
> @@ -1724,6 +1835,42 @@
> [(set_attr "type" "logical")
> (set_attr "mode" "SI")])
>
> +(define_insn "amo_orqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r,r")
> + (ior:QI (match_operand:QI 1 "register_operand" " r,r")
> + (match_operand:QI 2 "arith_operand" " r,r")))]
> + "TARGET_ZABHA"
> + "amoor.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_orhi3"
> + [(set (match_operand:HI 0 "register_operand" "=r,r")
> + (ior:HI (match_operand:HI 1 "register_operand" " r,r")
> + (match_operand:HI 2 "arith_operand" " r,r")))]
> + "TARGET_ZABHA"
> + "amoor.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> +(define_insn "amo_xorqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r,r")
> + (xor:QI (match_operand:QI 1 "register_operand" " r,r")
> + (match_operand:QI 2 "arith_operand" " r,r")))]
> + "TARGET_ZABHA"
> + "amoxor.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_xorhi3"
> + [(set (match_operand:HI 0 "register_operand" "=r,r")
> + (xor:HI (match_operand:HI 1 "register_operand" " r,r")
> + (match_operand:HI 2 "arith_operand" " r,r")))]
> + "TARGET_ZABHA"
> + "amoxor.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> ;;
> ;; ....................
> ;;
> @@ -3841,6 +3988,26 @@
> [(set_attr "type" "load")
> (set (attr "length") (const_int 8))])
>
> +(define_insn "amo_swapqi3"
> + [(set (match_operand:QI 0 "register_operand" "=r")
> + (unspec:QI [(match_operand:QI 1 "register_operand" "r")
> + (match_operand:QI 2 "register_operand" "r")]
> + UNSPEC_AMO_SWAP))]
> + "TARGET_ZABHA"
> + "amoswap.b\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "QI")])
> +
> +(define_insn "amo_swaphi3"
> + [(set (match_operand:HI 0 "register_operand" "=r")
> + (unspec:HI [(match_operand:HI 1 "register_operand" "r")
> + (match_operand:HI 2 "register_operand" "r")]
> + UNSPEC_AMO_SWAP))]
> + "TARGET_ZABHA"
> + "amoswap.h\t%0,%1,%2"
> + [(set_attr "type" "atomic")
> + (set_attr "mode" "HI")])
> +
> (include "bitmanip.md")
> (include "crypto.md")
> (include "sync.md")
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index f6ff70b2b30..1136a5301ea 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -244,6 +244,8 @@ Mask(ZA64RS) Var(riscv_za_subext)
>
> Mask(ZA128RS) Var(riscv_za_subext)
>
> +Mask(ZABHA) Var(riscv_za_subext)
> +
> TargetVariable
> int riscv_zb_subext
>
> --
> 2.34.1
>
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2024-02-06 9:17 [PATCH V1] RISC-V: Add mininal support for zabha extension shiyulong
2024-02-06 10:02 ` Kito Cheng
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