From: Kito Cheng <kito.cheng@gmail.com>
To: Mary Bennett <mary.bennett@embecosm.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension
Date: Thu, 25 Jan 2024 22:52:26 +0800 [thread overview]
Message-ID: <CA+yXCZBJQYbv83OELSSW5EsmwE_84ta-2AdsW5bVqFgRnw914A@mail.gmail.com> (raw)
In-Reply-To: <CA+yXCZDTDGM_eOqp1g9CZ11vj7zYQzU5KVK3d9aEqdeqcY=jcQ@mail.gmail.com>
pushed :)
On Thu, Jan 25, 2024 at 9:53 PM Kito Cheng <kito.cheng@gmail.com> wrote:
>
> It's stage 4, so I think it would be great to not disturb code base
> too much, and adding intrinsic without adding VLS modes should be
> better way to go, and here is not really something serious coding
> style issue, just few minor indentation issue, so I gonna run
> regression to make not break anything else and then commit to trunk :)
prev parent reply other threads:[~2024-01-25 14:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-09 11:57 [PATCH 0/1] " Mary Bennett
2023-11-09 11:57 ` [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett
2023-12-05 16:12 ` Kito Cheng
2024-01-16 16:35 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett
2024-01-16 16:35 ` [PATCH v2 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett
2024-01-16 16:35 ` [PATCH v2 2/2] RISC-V: Fix XCValu test Mary Bennett
2024-01-16 17:13 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett
2024-01-16 17:13 ` [PATCH v3 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett
2024-01-16 17:13 ` [PATCH v3 2/2] RISC-V: Fix XCValu test Mary Bennett
2024-01-21 23:25 ` Jeff Law
2024-01-25 13:53 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Kito Cheng
2024-01-25 14:52 ` Kito Cheng [this message]
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