From: Mary Bennett <mary.bennett@embecosm.com>
To: gcc-patches@gcc.gnu.org
Cc: mary.bennett@embecosm.com
Subject: [PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension
Date: Thu, 9 Nov 2023 11:57:35 +0000 [thread overview]
Message-ID: <20231109115736.541131-1-mary.bennett@embecosm.com> (raw)
This patch series presents the comprehensive implementation of the SIMD
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
[2] github.com/openhwgroup/corev-gcc
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Add support for XCVsimd extension in CV32E40P
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/constraints.md | 30 +
gcc/config/riscv/corev.def | 156 ++
gcc/config/riscv/corev.md | 1908 +++++++++++++++++
gcc/config/riscv/predicates.md | 20 +
gcc/config/riscv/riscv-builtins.cc | 1 +
gcc/config/riscv/riscv-ftypes.def | 9 +
gcc/config/riscv/riscv.cc | 8 +
gcc/config/riscv/riscv.opt | 2 +
gcc/doc/extend.texi | 886 ++++++++
gcc/doc/sourcebuild.texi | 3 +
.../riscv/cv-simd-abs-b-compile-1.c | 11 +
.../riscv/cv-simd-abs-h-compile-1.c | 11 +
.../riscv/cv-simd-add-b-compile-1.c | 11 +
.../riscv/cv-simd-add-div2-compile-1.c | 11 +
.../riscv/cv-simd-add-div4-compile-1.c | 11 +
.../riscv/cv-simd-add-div8-compile-1.c | 11 +
.../riscv/cv-simd-add-h-compile-1.c | 11 +
.../riscv/cv-simd-add-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-add-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-and-b-compile-1.c | 11 +
.../riscv/cv-simd-and-h-compile-1.c | 11 +
.../riscv/cv-simd-and-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-and-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-avg-b-compile-1.c | 11 +
.../riscv/cv-simd-avg-h-compile-1.c | 11 +
.../riscv/cv-simd-avg-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-avg-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-avgu-b-compile-1.c | 11 +
.../riscv/cv-simd-avgu-h-compile-1.c | 11 +
.../riscv/cv-simd-avgu-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-avgu-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-cmpeq-b-compile-1.c | 11 +
.../riscv/cv-simd-cmpeq-h-compile-1.c | 11 +
.../riscv/cv-simd-cmpeq-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-cmpeq-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-cmpge-b-compile-1.c | 11 +
.../riscv/cv-simd-cmpge-h-compile-1.c | 11 +
.../riscv/cv-simd-cmpge-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-cmpge-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-cmpgeu-b-compile-1.c | 11 +
.../riscv/cv-simd-cmpgeu-h-compile-1.c | 11 +
.../riscv/cv-simd-cmpgeu-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-cmpgeu-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-cmpgt-b-compile-1.c | 11 +
.../riscv/cv-simd-cmpgt-h-compile-1.c | 11 +
.../riscv/cv-simd-cmpgt-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-cmpgt-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-cmpgtu-b-compile-1.c | 11 +
.../riscv/cv-simd-cmpgtu-h-compile-1.c | 11 +
.../riscv/cv-simd-cmpgtu-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-cmpgtu-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-cmple-b-compile-1.c | 11 +
.../riscv/cv-simd-cmple-h-compile-1.c | 11 +
.../riscv/cv-simd-cmple-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-cmple-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-cmpleu-b-compile-1.c | 11 +
.../riscv/cv-simd-cmpleu-h-compile-1.c | 11 +
.../riscv/cv-simd-cmpleu-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-cmpleu-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-cmplt-b-compile-1.c | 11 +
.../riscv/cv-simd-cmplt-h-compile-1.c | 11 +
.../riscv/cv-simd-cmplt-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-cmplt-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-cmpltu-b-compile-1.c | 11 +
.../riscv/cv-simd-cmpltu-h-compile-1.c | 11 +
.../riscv/cv-simd-cmpltu-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-cmpltu-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-cmpne-b-compile-1.c | 11 +
.../riscv/cv-simd-cmpne-h-compile-1.c | 11 +
.../riscv/cv-simd-cmpne-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-cmpne-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-cplxconj-compile-1.c | 11 +
.../riscv/cv-simd-cplxmul-i-compile-1.c | 11 +
.../riscv/cv-simd-cplxmul-i-div2-compile-1.c | 11 +
.../riscv/cv-simd-cplxmul-i-div4-compile-1.c | 11 +
.../riscv/cv-simd-cplxmul-i-div8-compile-1.c | 11 +
.../riscv/cv-simd-cplxmul-r-compile-1.c | 11 +
.../riscv/cv-simd-cplxmul-r-div2-compile-1.c | 11 +
.../riscv/cv-simd-cplxmul-r-div4-compile-1.c | 11 +
.../riscv/cv-simd-cplxmul-r-div8-compile-1.c | 11 +
.../riscv/cv-simd-dotsp-b-compile-1.c | 11 +
.../riscv/cv-simd-dotsp-h-compile-1.c | 11 +
.../riscv/cv-simd-dotsp-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-dotsp-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-dotup-b-compile-1.c | 11 +
.../riscv/cv-simd-dotup-h-compile-1.c | 11 +
.../riscv/cv-simd-dotup-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-dotup-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-dotusp-b-compile-1.c | 11 +
.../riscv/cv-simd-dotusp-h-compile-1.c | 11 +
.../riscv/cv-simd-dotusp-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-dotusp-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-extract-b-compile-1.c | 23 +
.../riscv/cv-simd-extract-h-compile-1.c | 23 +
.../riscv/cv-simd-extractu-b-compile-1.c | 23 +
.../riscv/cv-simd-extractu-h-compile-1.c | 23 +
.../riscv/cv-simd-insert-b-compile-1.c | 23 +
.../riscv/cv-simd-insert-h-compile-1.c | 23 +
.../riscv/cv-simd-march-compile-1.c | 1765 +++++++++++++++
.../riscv/cv-simd-max-b-compile-1.c | 11 +
.../riscv/cv-simd-max-h-compile-1.c | 11 +
.../riscv/cv-simd-max-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-max-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-maxu-b-compile-1.c | 11 +
.../riscv/cv-simd-maxu-h-compile-1.c | 11 +
.../riscv/cv-simd-maxu-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-maxu-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-min-b-compile-1.c | 11 +
.../riscv/cv-simd-min-h-compile-1.c | 11 +
.../riscv/cv-simd-min-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-min-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-minu-b-compile-1.c | 11 +
.../riscv/cv-simd-minu-h-compile-1.c | 11 +
.../riscv/cv-simd-minu-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-minu-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-neg-b-compile-1.c | 11 +
.../riscv/cv-simd-neg-h-compile-1.c | 11 +
.../gcc.target/riscv/cv-simd-or-b-compile-1.c | 11 +
.../gcc.target/riscv/cv-simd-or-h-compile-1.c | 11 +
.../riscv/cv-simd-or-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-or-sc-h-compile-1.c | 30 +
.../gcc.target/riscv/cv-simd-pack-compile-1.c | 11 +
.../riscv/cv-simd-pack-h-compile-1.c | 11 +
.../riscv/cv-simd-packhi-b-compile-1.c | 11 +
.../riscv/cv-simd-packlo-b-compile-1.c | 11 +
.../riscv/cv-simd-sdotsp-b-compile-1.c | 11 +
.../riscv/cv-simd-sdotsp-h-compile-1.c | 11 +
.../riscv/cv-simd-sdotsp-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-sdotsp-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-sdotup-b-compile-1.c | 11 +
.../riscv/cv-simd-sdotup-h-compile-1.c | 11 +
.../riscv/cv-simd-sdotup-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-sdotup-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-sdotusp-b-compile-1.c | 11 +
.../riscv/cv-simd-sdotusp-h-compile-1.c | 11 +
.../riscv/cv-simd-sdotusp-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-sdotusp-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-shuffle-sci-h-compile-1.c | 11 +
.../riscv/cv-simd-shuffle2-b-compile-1.c | 11 +
.../riscv/cv-simd-shuffle2-h-compile-1.c | 11 +
.../riscv/cv-simd-shufflei0-sci-b-compile-1.c | 19 +
.../riscv/cv-simd-shufflei1-sci-b-compile-1.c | 19 +
.../riscv/cv-simd-shufflei2-sci-b-compile-1.c | 19 +
.../riscv/cv-simd-shufflei3-sci-b-compile-1.c | 19 +
.../riscv/cv-simd-sll-b-compile-1.c | 11 +
.../riscv/cv-simd-sll-h-compile-1.c | 11 +
.../riscv/cv-simd-sll-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-sll-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-sra-b-compile-1.c | 11 +
.../riscv/cv-simd-sra-h-compile-1.c | 11 +
.../riscv/cv-simd-sra-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-sra-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-srl-b-compile-1.c | 11 +
.../riscv/cv-simd-srl-h-compile-1.c | 11 +
.../riscv/cv-simd-srl-sc-b-compile-1.c | 24 +
.../riscv/cv-simd-srl-sc-h-compile-1.c | 24 +
.../riscv/cv-simd-sub-b-compile-1.c | 11 +
.../riscv/cv-simd-sub-div2-compile-1.c | 11 +
.../riscv/cv-simd-sub-div4-compile-1.c | 11 +
.../riscv/cv-simd-sub-div8-compile-1.c | 11 +
.../riscv/cv-simd-sub-h-compile-1.c | 11 +
.../riscv/cv-simd-sub-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-sub-sc-h-compile-1.c | 30 +
.../riscv/cv-simd-subrotmj-compile-1.c | 11 +
.../riscv/cv-simd-subrotmj-div2-compile-1.c | 11 +
.../riscv/cv-simd-subrotmj-div4-compile-1.c | 11 +
.../riscv/cv-simd-subrotmj-div8-compile-1.c | 11 +
.../riscv/cv-simd-xor-b-compile-1.c | 11 +
.../riscv/cv-simd-xor-h-compile-1.c | 11 +
.../riscv/cv-simd-xor-sc-b-compile-1.c | 30 +
.../riscv/cv-simd-xor-sc-h-compile-1.c | 30 +
gcc/testsuite/lib/target-supports.exp | 13 +
173 files changed, 7663 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c
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--
2.34.1
next reply other threads:[~2023-11-09 11:57 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-09 11:57 Mary Bennett [this message]
2023-11-09 11:57 ` [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett
2023-12-05 16:12 ` Kito Cheng
2024-01-16 16:35 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett
2024-01-16 16:35 ` [PATCH v2 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett
2024-01-16 16:35 ` [PATCH v2 2/2] RISC-V: Fix XCValu test Mary Bennett
2024-01-16 17:13 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett
2024-01-16 17:13 ` [PATCH v3 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett
2024-01-16 17:13 ` [PATCH v3 2/2] RISC-V: Fix XCValu test Mary Bennett
2024-01-21 23:25 ` Jeff Law
2024-01-25 13:53 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Kito Cheng
2024-01-25 14:52 ` Kito Cheng
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