Re: [PATCH v1] RISC-V: Add xfail test case for highpart register overlap of vwcvt

[Kito Cheng <kito.cheng@gmail.com>]

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LGTM

juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> 於 2024年4月25日 週四 09:26 寫道：

> lgtm
>
> ------------------------------
> juzhe.zhong@rivai.ai
>
>
> *From:* pan2.li <pan2.li@intel.com>
> *Date:* 2024-04-25 09:25
> *To:* gcc-patches <gcc-patches@gcc.gnu.org>
> *CC:* juzhe.zhong <juzhe.zhong@rivai.ai>; kito.cheng
> <kito.cheng@gmail.com>; rdapp.gcc <rdapp.gcc@gmail.com>; Pan Li
> <pan2.li@intel.com>
> *Subject:* [PATCH v1] RISC-V: Add xfail test case for highpart register
> overlap of vwcvt
> From: Pan Li <pan2.li@intel.com>
>
> We reverted below patch for register group overlap, add the related
> insn test and mark it as xfail.  And we will remove the xfail
> after we support the register overlap in GCC-15.
>
> bdad036da32 RISC-V: Support highpart register overlap for vwcvt
>
> The below test suites are passed for this patch
> * The rv64gcv fully regression test with isl build.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr112431-1.c: New test.
> * gcc.target/riscv/rvv/base/pr112431-2.c: New test.
> * gcc.target/riscv/rvv/base/pr112431-3.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> .../gcc.target/riscv/rvv/base/pr112431-1.c    | 104 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/pr112431-2.c    |  68 ++++++++++++
> .../gcc.target/riscv/rvv/base/pr112431-3.c    |  51 +++++++++
> 3 files changed, 223 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> new file mode 100644
> index 00000000000..6f9c6f7bd8c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> @@ -0,0 +1,104 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +size_t __attribute__ ((noinline))
> +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
> +   size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,
> +   size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,
> +   size_t sum15)
> +{
> +  return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 +
> sum9
> + + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;
> +}
> +
> +size_t
> +foo (char const *buf, size_t len)
> +{
> +  size_t sum = 0;
> +  size_t vl = __riscv_vsetvlmax_e8m8 ();
> +  size_t step = vl * 4;
> +  const char *it = buf, *end = buf + len;
> +  for (; it + step <= end;)
> +    {
> +      vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +      vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +      it += vl;
> +
> +      asm volatile("nop" ::: "memory");
> +      vint16m2_t vw0 = __riscv_vwcvt_x_x_v_i16m2 (v0, vl);
> +      vint16m2_t vw1 = __riscv_vwcvt_x_x_v_i16m2 (v1, vl);
> +      vint16m2_t vw2 = __riscv_vwcvt_x_x_v_i16m2 (v2, vl);
> +      vint16m2_t vw3 = __riscv_vwcvt_x_x_v_i16m2 (v3, vl);
> +      vint16m2_t vw4 = __riscv_vwcvt_x_x_v_i16m2 (v4, vl);
> +      vint16m2_t vw5 = __riscv_vwcvt_x_x_v_i16m2 (v5, vl);
> +      vint16m2_t vw6 = __riscv_vwcvt_x_x_v_i16m2 (v6, vl);
> +      vint16m2_t vw7 = __riscv_vwcvt_x_x_v_i16m2 (v7, vl);
> +      vint16m2_t vw8 = __riscv_vwcvt_x_x_v_i16m2 (v8, vl);
> +      vint16m2_t vw9 = __riscv_vwcvt_x_x_v_i16m2 (v9, vl);
> +      vint16m2_t vw10 = __riscv_vwcvt_x_x_v_i16m2 (v10, vl);
> +      vint16m2_t vw11 = __riscv_vwcvt_x_x_v_i16m2 (v11, vl);
> +      vint16m2_t vw12 = __riscv_vwcvt_x_x_v_i16m2 (v12, vl);
> +      vint16m2_t vw13 = __riscv_vwcvt_x_x_v_i16m2 (v13, vl);
> +      vint16m2_t vw14 = __riscv_vwcvt_x_x_v_i16m2 (v14, vl);
> +      vint16m2_t vw15 = __riscv_vwcvt_x_x_v_i16m2 (v15, vl);
> +
> +      asm volatile("nop" ::: "memory");
> +      size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);
> +      size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);
> +      size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2);
> +      size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3);
> +      size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4);
> +      size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5);
> +      size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6);
> +      size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7);
> +      size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8);
> +      size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9);
> +      size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10);
> +      size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11);
> +      size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12);
> +      size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13);
> +      size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14);
> +      size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15);
> +
> +      sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7,
> sum8,
> +        sum9, sum10, sum11, sum12, sum13, sum14, sum15);
> +    }
> +  return sum;
> +}
> +
> +/* { dg-final { scan-assembler-not {vmv1r} } } */
> +/* { dg-final { scan-assembler-not {vmv2r} } } */
> +/* { dg-final { scan-assembler-not {vmv4r} } } */
> +/* { dg-final { scan-assembler-not {vmv8r} } } */
> +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c
> new file mode 100644
> index 00000000000..b99dd19e623
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c
> @@ -0,0 +1,68 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +size_t __attribute__ ((noinline))
> +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
> +   size_t sum5, size_t sum6, size_t sum7)
> +{
> +  return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7;
> +}
> +
> +size_t
> +foo (char const *buf, size_t len)
> +{
> +  size_t sum = 0;
> +  size_t vl = __riscv_vsetvlmax_e8m8 ();
> +  size_t step = vl * 4;
> +  const char *it = buf, *end = buf + len;
> +  for (; it + step <= end;)
> +    {
> +      vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl);
> +      it += vl;
> +      vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl);
> +      it += vl;
> +      vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl);
> +      it += vl;
> +      vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl);
> +      it += vl;
> +      vint8m2_t v4 = __riscv_vle8_v_i8m2 ((void *) it, vl);
> +      it += vl;
> +      vint8m2_t v5 = __riscv_vle8_v_i8m2 ((void *) it, vl);
> +      it += vl;
> +      vint8m2_t v6 = __riscv_vle8_v_i8m2 ((void *) it, vl);
> +      it += vl;
> +      vint8m2_t v7 = __riscv_vle8_v_i8m2 ((void *) it, vl);
> +      it += vl;
> +
> +      asm volatile("nop" ::: "memory");
> +      vint16m4_t vw0 = __riscv_vwcvt_x_x_v_i16m4 (v0, vl);
> +      vint16m4_t vw1 = __riscv_vwcvt_x_x_v_i16m4 (v1, vl);
> +      vint16m4_t vw2 = __riscv_vwcvt_x_x_v_i16m4 (v2, vl);
> +      vint16m4_t vw3 = __riscv_vwcvt_x_x_v_i16m4 (v3, vl);
> +      vint16m4_t vw4 = __riscv_vwcvt_x_x_v_i16m4 (v4, vl);
> +      vint16m4_t vw5 = __riscv_vwcvt_x_x_v_i16m4 (v5, vl);
> +      vint16m4_t vw6 = __riscv_vwcvt_x_x_v_i16m4 (v6, vl);
> +      vint16m4_t vw7 = __riscv_vwcvt_x_x_v_i16m4 (v7, vl);
> +
> +      asm volatile("nop" ::: "memory");
> +      size_t sum0 = __riscv_vmv_x_s_i16m4_i16 (vw0);
> +      size_t sum1 = __riscv_vmv_x_s_i16m4_i16 (vw1);
> +      size_t sum2 = __riscv_vmv_x_s_i16m4_i16 (vw2);
> +      size_t sum3 = __riscv_vmv_x_s_i16m4_i16 (vw3);
> +      size_t sum4 = __riscv_vmv_x_s_i16m4_i16 (vw4);
> +      size_t sum5 = __riscv_vmv_x_s_i16m4_i16 (vw5);
> +      size_t sum6 = __riscv_vmv_x_s_i16m4_i16 (vw6);
> +      size_t sum7 = __riscv_vmv_x_s_i16m4_i16 (vw7);
> +
> +      sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7);
> +    }
> +  return sum;
> +}
> +
> +/* { dg-final { scan-assembler-not {vmv1r} } } */
> +/* { dg-final { scan-assembler-not {vmv2r} } } */
> +/* { dg-final { scan-assembler-not {vmv4r} } } */
> +/* { dg-final { scan-assembler-not {vmv8r} } } */
> +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c
> new file mode 100644
> index 00000000000..cac50bd003c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c
> @@ -0,0 +1,51 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +size_t __attribute__ ((noinline))
> +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3)
> +{
> +  return sum0 + sum1 + sum2 + sum3;
> +}
> +
> +size_t
> +foo (char const *buf, size_t len)
> +{
> +  size_t sum = 0;
> +  size_t vl = __riscv_vsetvlmax_e8m8 ();
> +  size_t step = vl * 4;
> +  const char *it = buf, *end = buf + len;
> +  for (; it + step <= end;)
> +    {
> +      vint8m4_t v0 = __riscv_vle8_v_i8m4 ((void *) it, vl);
> +      it += vl;
> +      vint8m4_t v1 = __riscv_vle8_v_i8m4 ((void *) it, vl);
> +      it += vl;
> +      vint8m4_t v2 = __riscv_vle8_v_i8m4 ((void *) it, vl);
> +      it += vl;
> +      vint8m4_t v3 = __riscv_vle8_v_i8m4 ((void *) it, vl);
> +      it += vl;
> +
> +      asm volatile("nop" ::: "memory");
> +      vint16m8_t vw0 = __riscv_vwcvt_x_x_v_i16m8 (v0, vl);
> +      vint16m8_t vw1 = __riscv_vwcvt_x_x_v_i16m8 (v1, vl);
> +      vint16m8_t vw2 = __riscv_vwcvt_x_x_v_i16m8 (v2, vl);
> +      vint16m8_t vw3 = __riscv_vwcvt_x_x_v_i16m8 (v3, vl);
> +
> +      asm volatile("nop" ::: "memory");
> +      size_t sum0 = __riscv_vmv_x_s_i16m8_i16 (vw0);
> +      size_t sum1 = __riscv_vmv_x_s_i16m8_i16 (vw1);
> +      size_t sum2 = __riscv_vmv_x_s_i16m8_i16 (vw2);
> +      size_t sum3 = __riscv_vmv_x_s_i16m8_i16 (vw3);
> +
> +      sum += sumation (sum0, sum1, sum2, sum3);
> +    }
> +  return sum;
> +}
> +
> +/* { dg-final { scan-assembler-not {vmv1r} } } */
> +/* { dg-final { scan-assembler-not {vmv2r} } } */
> +/* { dg-final { scan-assembler-not {vmv4r} } } */
> +/* { dg-final { scan-assembler-not {vmv8r} } } */
> +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
> --
> 2.34.1
>
>
>
>