* [PATCH V2] RISC-V: Fix zero-scratch-regs-3.c fail
@ 2023-05-26 0:45 juzhe.zhong
2023-05-28 12:03 ` Kito Cheng
0 siblings, 1 reply; 2+ messages in thread
From: juzhe.zhong @ 2023-05-26 0:45 UTC (permalink / raw)
To: gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc,
pan2.li, Juzhe-Zhong
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv.cc (vector_zero_call_used_regs): Add explict VL and drop VL in ops.
---
gcc/config/riscv/riscv.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 09fc9e5d95e..b16c60df6a7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7396,9 +7396,9 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
emitted_vlmax_vsetvl = true;
}
- rtx ops[] = {target, CONST0_RTX (mode), vl};
+ rtx ops[] = {target, CONST0_RTX (mode)};
riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode),
- riscv_vector::RVV_UNOP, ops);
+ riscv_vector::RVV_UNOP, ops, vl);
SET_HARD_REG_BIT (zeroed_hardregs, regno);
}
--
2.36.3
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH V2] RISC-V: Fix zero-scratch-regs-3.c fail
2023-05-26 0:45 [PATCH V2] RISC-V: Fix zero-scratch-regs-3.c fail juzhe.zhong
@ 2023-05-28 12:03 ` Kito Cheng
0 siblings, 0 replies; 2+ messages in thread
From: Kito Cheng @ 2023-05-28 12:03 UTC (permalink / raw)
To: 钟居哲
Cc: GCC Patches, Kito Cheng, Palmer Dabbelt, Palmer Dabbelt,
Jeff Law, Robin Dapp, Li, Pan2
[-- Attachment #1: Type: text/plain, Size: 1119 bytes --]
LGTM
<juzhe.zhong@rivai.ai> 於 2023年5月26日 週五 08:46 寫道：
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (vector_zero_call_used_regs): Add explict
> VL and drop VL in ops.
>
> ---
> gcc/config/riscv/riscv.cc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 09fc9e5d95e..b16c60df6a7 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7396,9 +7396,9 @@ vector_zero_call_used_regs (HARD_REG_SET
> need_zeroed_hardregs)
> emitted_vlmax_vsetvl = true;
> }
>
> - rtx ops[] = {target, CONST0_RTX (mode), vl};
> + rtx ops[] = {target, CONST0_RTX (mode)};
> riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode),
> - riscv_vector::RVV_UNOP, ops);
> + riscv_vector::RVV_UNOP, ops, vl);
>
> SET_HARD_REG_BIT (zeroed_hardregs, regno);
> }
> --
> 2.36.3
>
>
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