* [PATCH] RISC-V: Add vxor.vv C API tests
@ 2023-01-31 12:12 juzhe.zhong
2023-01-31 16:46 ` Kito Cheng
0 siblings, 1 reply; 4+ messages in thread
From: juzhe.zhong @ 2023-01-31 12:12 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vxor_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c: New test.
---
.../gcc.target/riscv/rvv/base/vxor_vv-1.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv-2.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv-3.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_m-1.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_m-2.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_m-3.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_mu-1.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_mu-2.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_mu-3.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_tu-1.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_tu-2.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_tu-3.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_tum-1.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_tum-2.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vxor_vv_tum-3.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vxor_vv_tumu-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vxor_vv_tumu-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vxor_vv_tumu-3.c | 292 ++++++++++++++++++
18 files changed, 5256 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c
new file mode 100644
index 00000000000..3f6ff8fa4a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c
new file mode 100644
index 00000000000..9b60835fc07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c
new file mode 100644
index 00000000000..09a877dbca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c
new file mode 100644
index 00000000000..fbe06e204b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_m(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_m(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_m(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_m(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_m(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_m(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_m(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_m(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_m(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_m(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_m(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_m(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_m(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_m(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_m(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c
new file mode 100644
index 00000000000..3797b5d9b0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_m(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_m(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_m(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_m(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_m(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_m(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_m(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_m(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_m(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_m(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_m(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_m(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_m(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_m(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_m(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_m(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_m(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_m(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_m(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_m(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c
new file mode 100644
index 00000000000..4459be0b7cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_m(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_m(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_m(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_m(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_m(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_m(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_m(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_m(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_m(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_m(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_m(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_m(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_m(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_m(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_m(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_m(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_m(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_m(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_m(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_m(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c
new file mode 100644
index 00000000000..93591b37dd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c
new file mode 100644
index 00000000000..f9608597cde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c
new file mode 100644
index 00000000000..96cde136530
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c
new file mode 100644
index 00000000000..195d586c9ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c
new file mode 100644
index 00000000000..c5ee28d1529
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c
new file mode 100644
index 00000000000..cf337a642d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c
new file mode 100644
index 00000000000..08c25d5a408
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c
new file mode 100644
index 00000000000..19151015cf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c
new file mode 100644
index 00000000000..f38eae4f4e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c
new file mode 100644
index 00000000000..bb95ccd9063
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c
new file mode 100644
index 00000000000..819f742ee86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c
new file mode 100644
index 00000000000..7c463fa10fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
--
2.36.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: Add vxor.vv C API tests
2023-01-31 12:12 [PATCH] RISC-V: Add vxor.vv C API tests juzhe.zhong
@ 2023-01-31 16:46 ` Kito Cheng
0 siblings, 0 replies; 4+ messages in thread
From: Kito Cheng @ 2023-01-31 16:46 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, palmer
committed, thanks!
On Tue, Jan 31, 2023 at 8:12 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vxor_vv-1.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv-2.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv-3.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tu-1.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tu-2.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tu-3.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tum-1.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tum-2.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tum-3.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c: New test.
> * gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c: New test.
>
> ---
> .../gcc.target/riscv/rvv/base/vxor_vv-1.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv-2.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv-3.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_m-1.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_m-2.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_m-3.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_mu-1.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_mu-2.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_mu-3.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_tu-1.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_tu-2.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_tu-3.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_tum-1.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_tum-2.c | 292 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vxor_vv_tum-3.c | 292 ++++++++++++++++++
> .../riscv/rvv/base/vxor_vv_tumu-1.c | 292 ++++++++++++++++++
> .../riscv/rvv/base/vxor_vv_tumu-2.c | 292 ++++++++++++++++++
> .../riscv/rvv/base/vxor_vv_tumu-3.c | 292 ++++++++++++++++++
> 18 files changed, 5256 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c
> new file mode 100644
> index 00000000000..3f6ff8fa4a6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8(op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4(op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2(op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1(op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2(op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4(op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8(op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4(op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2(op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1(op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2(op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4(op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8(op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2(op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1(op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2(op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4(op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8(op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1(op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2(op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4(op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8(op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8(op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4(op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2(op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1(op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2(op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4(op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8(op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4(op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2(op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1(op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2(op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4(op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8(op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2(op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1(op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2(op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4(op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8(op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1(op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2(op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4(op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8(op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c
> new file mode 100644
> index 00000000000..9b60835fc07
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8(op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4(op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2(op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1(op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2(op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4(op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8(op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4(op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2(op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1(op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2(op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4(op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8(op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2(op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1(op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2(op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4(op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8(op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1(op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2(op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4(op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8(op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8(op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4(op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2(op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1(op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2(op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4(op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8(op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4(op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2(op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1(op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2(op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4(op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8(op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2(op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1(op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2(op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4(op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8(op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1(op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2(op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4(op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8(op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c
> new file mode 100644
> index 00000000000..09a877dbca3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8(op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4(op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2(op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1(op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2(op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4(op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8(op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4(op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2(op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1(op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2(op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4(op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8(op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2(op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1(op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2(op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4(op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8(op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1(op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2(op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4(op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8(op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8(op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4(op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2(op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1(op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2(op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4(op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8(op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4(op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2(op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1(op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2(op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4(op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8(op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2(op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1(op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2(op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4(op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8(op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1(op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2(op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4(op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8(op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c
> new file mode 100644
> index 00000000000..fbe06e204b7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c
> new file mode 100644
> index 00000000000..3797b5d9b0e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_m(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c
> new file mode 100644
> index 00000000000..4459be0b7cc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_m(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c
> new file mode 100644
> index 00000000000..93591b37dd5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c
> new file mode 100644
> index 00000000000..f9608597cde
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c
> new file mode 100644
> index 00000000000..96cde136530
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c
> new file mode 100644
> index 00000000000..195d586c9ca
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c
> new file mode 100644
> index 00000000000..c5ee28d1529
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c
> new file mode 100644
> index 00000000000..cf337a642d2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c
> new file mode 100644
> index 00000000000..08c25d5a408
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c
> new file mode 100644
> index 00000000000..19151015cf3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c
> new file mode 100644
> index 00000000000..f38eae4f4e9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c
> new file mode 100644
> index 00000000000..bb95ccd9063
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c
> new file mode 100644
> index 00000000000..819f742ee86
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c
> new file mode 100644
> index 00000000000..7c463fa10fe
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: Add vxor.vv C++ API tests
2023-01-31 12:49 [PATCH] RISC-V: Add vxor.vv C++ " juzhe.zhong
@ 2023-01-31 16:48 ` Kito Cheng
0 siblings, 0 replies; 4+ messages in thread
From: Kito Cheng @ 2023-01-31 16:48 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, palmer
committed, thanks!
On Tue, Jan 31, 2023 at 8:50 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/vxor_vv-1.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv-2.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv-3.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_mu-1.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_mu-2.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_mu-3.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tu-1.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tu-2.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tu-3.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tum-1.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tum-2.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tum-3.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tumu-1.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tumu-2.C: New test.
> * g++.target/riscv/rvv/base/vxor_vv_tumu-3.C: New test.
>
> ---
> .../g++.target/riscv/rvv/base/vxor_vv-1.C | 578 ++++++++++++++++++
> .../g++.target/riscv/rvv/base/vxor_vv-2.C | 578 ++++++++++++++++++
> .../g++.target/riscv/rvv/base/vxor_vv-3.C | 578 ++++++++++++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_mu-1.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_mu-2.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_mu-3.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_tu-1.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_tu-2.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_tu-3.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_tum-1.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_tum-2.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vxor_vv_tum-3.C | 292 +++++++++
> .../riscv/rvv/base/vxor_vv_tumu-1.C | 292 +++++++++
> .../riscv/rvv/base/vxor_vv_tumu-2.C | 292 +++++++++
> .../riscv/rvv/base/vxor_vv_tumu-3.C | 292 +++++++++
> 15 files changed, 5238 insertions(+)
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C
>
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C
> new file mode 100644
> index 00000000000..e1128f0af41
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,vl);
> +}
> +
> +
> +vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C
> new file mode 100644
> index 00000000000..41bb26a2adb
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,31);
> +}
> +
> +
> +vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C
> new file mode 100644
> index 00000000000..eb0b7d50939
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(op1,op2,32);
> +}
> +
> +
> +vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C
> new file mode 100644
> index 00000000000..42bb7d88f44
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C
> new file mode 100644
> index 00000000000..97e81c94393
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C
> new file mode 100644
> index 00000000000..04c600e66c6
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C
> new file mode 100644
> index 00000000000..a1221b54f2d
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C
> new file mode 100644
> index 00000000000..4764c248f42
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C
> new file mode 100644
> index 00000000000..ce67e4ea3a0
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C
> new file mode 100644
> index 00000000000..e600967bad7
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C
> new file mode 100644
> index 00000000000..290e0632223
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C
> new file mode 100644
> index 00000000000..6db574a6303
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C
> new file mode 100644
> index 00000000000..dee47dfd762
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C
> new file mode 100644
> index 00000000000..7d2e7b86ec3
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C
> new file mode 100644
> index 00000000000..53f924e49a2
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> + return __riscv_vxor_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] RISC-V: Add vxor.vv C++ API tests
@ 2023-01-31 12:49 juzhe.zhong
2023-01-31 16:48 ` Kito Cheng
0 siblings, 1 reply; 4+ messages in thread
From: juzhe.zhong @ 2023-01-31 12:49 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vxor_vv-1.C: New test.
* g++.target/riscv/rvv/base/vxor_vv-2.C: New test.
* g++.target/riscv/rvv/base/vxor_vv-3.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vxor_vv_tumu-3.C: New test.
---
.../g++.target/riscv/rvv/base/vxor_vv-1.C | 578 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vxor_vv-2.C | 578 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vxor_vv-3.C | 578 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vxor_vv_mu-1.C | 292 +++++++++
.../g++.target/riscv/rvv/base/vxor_vv_mu-2.C | 292 +++++++++
.../g++.target/riscv/rvv/base/vxor_vv_mu-3.C | 292 +++++++++
.../g++.target/riscv/rvv/base/vxor_vv_tu-1.C | 292 +++++++++
.../g++.target/riscv/rvv/base/vxor_vv_tu-2.C | 292 +++++++++
.../g++.target/riscv/rvv/base/vxor_vv_tu-3.C | 292 +++++++++
.../g++.target/riscv/rvv/base/vxor_vv_tum-1.C | 292 +++++++++
.../g++.target/riscv/rvv/base/vxor_vv_tum-2.C | 292 +++++++++
.../g++.target/riscv/rvv/base/vxor_vv_tum-3.C | 292 +++++++++
.../riscv/rvv/base/vxor_vv_tumu-1.C | 292 +++++++++
.../riscv/rvv/base/vxor_vv_tumu-2.C | 292 +++++++++
.../riscv/rvv/base/vxor_vv_tumu-3.C | 292 +++++++++
15 files changed, 5238 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C
new file mode 100644
index 00000000000..e1128f0af41
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C
new file mode 100644
index 00000000000..41bb26a2adb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C
new file mode 100644
index 00000000000..eb0b7d50939
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C
new file mode 100644
index 00000000000..42bb7d88f44
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C
new file mode 100644
index 00000000000..97e81c94393
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C
new file mode 100644
index 00000000000..04c600e66c6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C
new file mode 100644
index 00000000000..a1221b54f2d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C
new file mode 100644
index 00000000000..4764c248f42
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C
new file mode 100644
index 00000000000..ce67e4ea3a0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C
new file mode 100644
index 00000000000..e600967bad7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C
new file mode 100644
index 00000000000..290e0632223
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C
new file mode 100644
index 00000000000..6db574a6303
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C
new file mode 100644
index 00000000000..dee47dfd762
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C
new file mode 100644
index 00000000000..7d2e7b86ec3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C
new file mode 100644
index 00000000000..53f924e49a2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vxor_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
--
2.36.3
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-01-31 12:12 [PATCH] RISC-V: Add vxor.vv C API tests juzhe.zhong
2023-01-31 16:46 ` Kito Cheng
2023-01-31 12:49 [PATCH] RISC-V: Add vxor.vv C++ " juzhe.zhong
2023-01-31 16:48 ` Kito Cheng
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