[RFC] RISC-V: Support -mcmodel=large.

[RFC] RISC-V: Support -mcmodel=large.

[KuanLin Chen]

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This is a RFC patch for large code model implementation.

gcc/ChangeLog:
* gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF
and LABEL_REF type.
(call_insn_operand): Support for CM_Large.
(pcrel_symbol_operand): New.
* gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define
"__riscv_cmodel_large".
* gcc/config/riscv/riscv-opts.h (riscv_code_model): Define CM_LARGE.
* gcc/config/riscv/riscv-protos.h (riscv_symbol_type): Define
SYMBOL_FORCE_TO_MEM.
(riscv_asm_output_pool_epilogue): New.
* gcc/config/riscv/riscv.cc (riscv_classify_symbol) Support CM_LARGE model.
(riscv_symbol_insns) Add SYMBOL_FORCE_TO_MEM.
(riscv_cannot_force_const_mem): Ditto.
(riscv_split_symbol): Ditto.
(riscv_force_address): Check pseudo reg available before force_reg.
(riscv_size_ok_for_small_data_p): Disable in CM_LARGE model.
(riscv_can_use_per_function_literal_pools_p): New.
(riscv_asm_output_pool_epilogue): New. Hook ASM_OUTPUT_POOL_EPILOGUE.
(riscv_output_mi_thunk): Add riscv_in_thunk_func.
(riscv_option_override): Support CM_LARGE model.
(riscv_function_ok_for_sibcall): Disable sibcalls in CM_LARGE model.
* gcc/config/riscv/riscv.h (ASM_OUTPUT_POOL_EPILOGUE): Hookfg
* gcc/config/riscv/riscv.md (unspec): Define UNSPEC_FORCE_FOR_MEM.
(*large_load_address"): New.
* gcc/config/riscv/riscv.opt (code_model): New.

gcc/testsuite/ChangeLog:

  * gcc/testsuite/gcc.target/riscv/large-model.c: New test.

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From b09ba36220db1dbce3b1934685b1783125b5cb66 Mon Sep 17 00:00:00 2001
From: Kuan-Lin Chen <rufus@andestech.com>
Date: Sun, 18 Feb 2018 20:19:49 +0800
Subject: [PATCH] RISC-V: Support -mcmodel=large.

---
 gcc/config/riscv/predicates.md               | 23 +++++-
 gcc/config/riscv/riscv-c.cc                  |  4 +
 gcc/config/riscv/riscv-opts.h                |  1 +
 gcc/config/riscv/riscv-protos.h              |  4 +-
 gcc/config/riscv/riscv.cc                    | 77 +++++++++++++++++++-
 gcc/config/riscv/riscv.h                     |  2 +
 gcc/config/riscv/riscv.md                    |  9 +++
 gcc/config/riscv/riscv.opt                   |  3 +
 gcc/testsuite/gcc.target/riscv/large-model.c | 11 +++
 9 files changed, 127 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/large-model.c

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 53e7c1d03aa..01c68950bc9 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -275,7 +275,8 @@
     case SYMBOL_REF:
     case LABEL_REF:
       return riscv_symbolic_constant_p (op, &symbol_type)
-	      && !riscv_split_symbol_type (symbol_type);
+	     && !riscv_split_symbol_type (symbol_type)
+	     && symbol_type != SYMBOL_FORCE_TO_MEM;
 
     case HIGH:
       op = XEXP (op, 0);
@@ -312,9 +313,15 @@
 })
 
 (define_predicate "call_insn_operand"
-  (ior (match_operand 0 "absolute_symbolic_operand")
-       (match_operand 0 "plt_symbolic_operand")
-       (match_operand 0 "register_operand")))
+  (match_operand 0 "general_operand")
+{
+  if (riscv_cmodel == CM_LARGE)
+    return register_operand (op, mode);
+  else
+    return (absolute_symbolic_operand (op, mode) ||
+	    plt_symbolic_operand (op, mode) ||
+	    register_operand (op, mode));
+})
 
 (define_predicate "modular_operator"
   (match_code "plus,minus,mult,ashift"))
@@ -585,3 +592,11 @@
   (and (match_code "const_int")
        (ior (match_operand 0 "not_uimm_extra_bit_operand")
 	    (match_operand 0 "const_nottwobits_not_arith_operand"))))
+
+(define_predicate "pcrel_symbol_operand"
+  (match_code "symbol_ref")
+{
+  enum riscv_symbol_type type;
+  return (riscv_symbolic_constant_p (op, &type)
+         && type == SYMBOL_PCREL);
+})
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 283052ae313..81edc25feac 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -101,6 +101,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
       builtin_define ("__riscv_cmodel_medlow");
       break;
 
+    case CM_LARGE:
+      builtin_define ("__riscv_cmodel_large");
+      break;
+
     case CM_PIC:
     case CM_MEDANY:
       builtin_define ("__riscv_cmodel_medany");
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index a525f679683..49aefc07af6 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -35,6 +35,7 @@ extern enum riscv_abi_type riscv_abi;
 enum riscv_code_model {
   CM_MEDLOW,
   CM_MEDANY,
+  CM_LARGE,
   CM_PIC
 };
 extern enum riscv_code_model riscv_cmodel;
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index d08d5dfeef4..43c6854e8b7 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -28,6 +28,7 @@ along with GCC; see the file COPYING3.  If not see
    the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST.  */
 enum riscv_symbol_type {
   SYMBOL_ABSOLUTE,
+  SYMBOL_FORCE_TO_MEM,
   SYMBOL_PCREL,
   SYMBOL_GOT_DISP,
   SYMBOL_TLS,
@@ -139,7 +140,8 @@ extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
 extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
 extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
 extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel);
-
+extern void riscv_asm_output_pool_epilogue (FILE *, const char *,
+					    tree, HOST_WIDE_INT);
 /* Routines implemented in riscv-c.cc.  */
 void riscv_cpu_cpp_builtins (cpp_reader *);
 void riscv_register_pragmas (void);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9d04ddd69e0..5f780cd2c20 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -283,6 +283,9 @@ bool riscv_user_wants_strict_align;
 /* Stack alignment to assume/maintain.  */
 unsigned riscv_stack_boundary;
 
+/* Whether in riscv_output_mi_thunk. */
+static bool riscv_in_thunk_func = false;
+
 /* If non-zero, this is an offset to be added to SP to redefine the CFA
    when restoring the FP register from the stack.  Only valid when generating
    the epilogue.  */
@@ -784,7 +787,17 @@ riscv_classify_symbol (const_rtx x)
   if (GET_CODE (x) == SYMBOL_REF && flag_pic && !riscv_symbol_binds_local_p (x))
     return SYMBOL_GOT_DISP;
 
-  return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL;
+  switch (riscv_cmodel)
+    {
+    case CM_MEDLOW:
+      return SYMBOL_ABSOLUTE;
+    case CM_LARGE:
+      if (SYMBOL_REF_P (x))
+	return CONSTANT_POOL_ADDRESS_P (x) ? SYMBOL_PCREL : SYMBOL_FORCE_TO_MEM;
+      return SYMBOL_PCREL;
+    default:
+      return SYMBOL_PCREL;
+    }
 }
 
 /* Classify the base of symbolic expression X.  */
@@ -848,6 +861,7 @@ static int riscv_symbol_insns (enum riscv_symbol_type type)
     case SYMBOL_PCREL: return 2; /* AUIPC + the reference.  */
     case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference.  */
     case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference.  */
+    case SYMBOL_FORCE_TO_MEM: return 3; /* AUIPC + LD + the reference.  */
     default: gcc_unreachable ();
     }
 }
@@ -1017,6 +1031,9 @@ riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
   split_const (x, &base, &offset);
   if (riscv_symbolic_constant_p (base, &type))
     {
+      if (type == SYMBOL_FORCE_TO_MEM)
+	return false;
+
       /* As an optimization, don't spill symbolic constants that are as
 	 cheap to rematerialize as to access in the constant pool.  */
       if (SMALL_OPERAND (INTVAL (offset)) && riscv_symbol_insns (type) > 0)
@@ -1815,6 +1832,9 @@ riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
   if (low_out)
     switch (symbol_type)
       {
+      case SYMBOL_FORCE_TO_MEM:
+	return false;
+
       case SYMBOL_ABSOLUTE:
 	{
 	  rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
@@ -1972,7 +1992,19 @@ static rtx
 riscv_force_address (rtx x, machine_mode mode)
 {
   if (!riscv_legitimate_address_p (mode, x, false))
-    x = force_reg (Pmode, x);
+    {
+      if (can_create_pseudo_p ())
+	return force_reg (Pmode, x);
+      else
+	{
+	  /* It's only safe for the thunk function.*/
+	  gcc_assert (riscv_in_thunk_func);
+	  rtx reg = RISCV_PROLOGUE_TEMP (Pmode);
+	  riscv_emit_move (reg, x);
+	  return reg;
+	}
+    }
+
   return x;
 }
 
@@ -5665,6 +5697,9 @@ riscv_size_ok_for_small_data_p (int size)
 static bool
 riscv_in_small_data_p (const_tree x)
 {
+  if (riscv_cmodel == CM_LARGE)
+    return false;
+
   if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL)
     return false;
 
@@ -5730,6 +5765,23 @@ riscv_unique_section (tree decl, int reloc)
   default_unique_section (decl, reloc);
 }
 
+static inline bool
+riscv_can_use_per_function_literal_pools_p (void)
+{
+  return riscv_cmodel == CM_LARGE;
+}
+
+void
+riscv_asm_output_pool_epilogue (FILE *f, const char *, tree,
+				HOST_WIDE_INT offset)
+{
+  /* When using per-function literal pools, we must ensure that any code
+     section is aligned to the minimal instruction length, lest we get
+     errors from the assembler re "unaligned instructions".  */
+  if ((offset & 3) && riscv_can_use_per_function_literal_pools_p ())
+    ASM_OUTPUT_ALIGN (f, 2);
+}
+
 /* Return a section for X, handling small data. */
 
 static section *
@@ -7826,6 +7878,8 @@ riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
   rtx this_rtx, temp1, temp2, fnaddr;
   rtx_insn *insn;
 
+  riscv_in_thunk_func = true;
+
   /* Pretend to be a post-reload pass while generating rtl.  */
   reload_completed = 1;
 
@@ -7892,6 +7946,7 @@ riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
   /* Clean up the vars set above.  Note that final_end_function resets
      the global pointer for us.  */
   reload_completed = 0;
+  riscv_in_thunk_func = false;
 }
 
 /* Allocate a chunk of memory for per-function machine-dependent data.  */
@@ -8015,6 +8070,18 @@ riscv_option_override (void)
   /* Function to allocate machine-dependent function status.  */
   init_machine_status = &riscv_init_machine_status;
 
+  /* Always prefer medlow than medany for RV32 since medlow can access
+     full address space. */
+  if (riscv_cmodel == CM_LARGE && !TARGET_64BIT)
+    riscv_cmodel = CM_MEDLOW;
+
+  if (riscv_cmodel == CM_LARGE && TARGET_EXPLICIT_RELOCS)
+    sorry ("code model %qs with %qs", "large", "-mexplicit-relocs");
+
+  if (riscv_cmodel == CM_LARGE && flag_pic)
+    sorry ("code model %qs with %qs", "large",
+	   global_options.x_flag_pic > 1 ? "-fPIC" : "-fpic");
+
   if (flag_pic)
     riscv_cmodel = CM_PIC;
 
@@ -8355,6 +8422,12 @@ riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
   if (cfun->machine->interrupt_handler_p)
     return false;
 
+  /* Don't use sibcalls in the large model, because a sibcall instruction
+     expanding and a epilogue expanding both use RISCV_PROLOGUE_TEMP
+     register.  */
+  if (riscv_cmodel == CM_LARGE)
+    return false;
+
   return true;
 }
 
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 7ac78847b3a..5794c3bb0b3 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1191,4 +1191,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
 
+#define ASM_OUTPUT_POOL_EPILOGUE riscv_asm_output_pool_epilogue
+
 #endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index e00b8ee3579..5327f9bb572 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -41,6 +41,7 @@
   ;; Symbolic accesses.  The order of this list must match that of
   ;; enum riscv_symbol_type in riscv-protos.h.
   UNSPEC_ADDRESS_FIRST
+  UNSPEC_FORCE_FOR_MEM
   UNSPEC_PCREL
   UNSPEC_LOAD_GOT
   UNSPEC_TLS
@@ -3577,6 +3578,14 @@
     FAIL;
 })
 
+(define_insn "*large_load_address"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (mem:DI (match_operand 1 "pcrel_symbol_operand" "")))]
+  "TARGET_64BIT && riscv_cmodel == CM_LARGE"
+  "ld\t%0,%1"
+  [(set_attr "type" "load")
+   (set (attr "length") (const_int 8))])
+
 (include "bitmanip.md")
 (include "crypto.md")
 (include "sync.md")
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 21d00606f25..f143f412f6c 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -123,6 +123,9 @@ Enum(code_model) String(medlow) Value(CM_MEDLOW)
 EnumValue
 Enum(code_model) String(medany) Value(CM_MEDANY)
 
+EnumValue
+Enum(code_model) String(large) Value(CM_LARGE)
+
 mexplicit-relocs
 Target Mask(EXPLICIT_RELOCS)
 Use %reloc() operators, rather than assembly macros, to load addresses.
diff --git a/gcc/testsuite/gcc.target/riscv/large-model.c b/gcc/testsuite/gcc.target/riscv/large-model.c
new file mode 100644
index 00000000000..244d14e1878
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/large-model.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -fno-section-anchors -mcmodel=large" } */
+/* { dg-skip-if "" { *-*-* } {"-O0"} } */
+int a, b;
+int foo1()
+{
+  return a*b;
+}
+
+/* { dg-final { scan-assembler-times "ld.*LC0" 1 } } */
+/* { dg-final { scan-assembler-times "ld.*LC1" 1 } } */
-- 
2.30.1

Re: [RFC] RISC-V: Support -mcmodel=large.

[Jeff Law]

On 10/25/23 19:49, KuanLin Chen wrote:
> This is a RFC patch for large code model implementation.
> 
> gcc/ChangeLog:
> * gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF
> and LABEL_REF type.
> (call_insn_operand): Support for CM_Large.
> (pcrel_symbol_operand): New.
> * gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define
> "__riscv_cmodel_large".
> * gcc/config/riscv/riscv-opts.h (riscv_code_model): Define CM_LARGE.
> * gcc/config/riscv/riscv-protos.h (riscv_symbol_type): Define
> SYMBOL_FORCE_TO_MEM.
> (riscv_asm_output_pool_epilogue): New.
> * gcc/config/riscv/riscv.cc (riscv_classify_symbol) Support CM_LARGE model.
> (riscv_symbol_insns) Add SYMBOL_FORCE_TO_MEM.
> (riscv_cannot_force_const_mem): Ditto.
> (riscv_split_symbol): Ditto.
> (riscv_force_address): Check pseudo reg available before force_reg.
> (riscv_size_ok_for_small_data_p): Disable in CM_LARGE model.
> (riscv_can_use_per_function_literal_pools_p): New.
> (riscv_asm_output_pool_epilogue): New. Hook ASM_OUTPUT_POOL_EPILOGUE.
> (riscv_output_mi_thunk): Add riscv_in_thunk_func.
> (riscv_option_override): Support CM_LARGE model.
> (riscv_function_ok_for_sibcall): Disable sibcalls in CM_LARGE model.
> * gcc/config/riscv/riscv.h (ASM_OUTPUT_POOL_EPILOGUE): Hookfg
> * gcc/config/riscv/riscv.md (unspec): Define UNSPEC_FORCE_FOR_MEM.
> (*large_load_address"): New.
> * gcc/config/riscv/riscv.opt (code_model): New.
> 
> gcc/testsuite/ChangeLog:
> 
>    * gcc/testsuite/gcc.target/riscv/large-model.c: New test.
First, thank you so much for tackling this.  It's one of the many 
missing components that we need to round out the implementation.


> 
> 
> 0001-RISC-V-Support-mcmodel-large.patch
> 
>  From b09ba36220db1dbce3b1934685b1783125b5cb66 Mon Sep 17 00:00:00 2001
> From: Kuan-Lin Chen<rufus@andestech.com>
> Date: Sun, 18 Feb 2018 20:19:49 +0800
> Subject: [PATCH] RISC-V: Support -mcmodel=large.
> 
> ---
>   gcc/config/riscv/predicates.md               | 23 +++++-
>   gcc/config/riscv/riscv-c.cc                  |  4 +
>   gcc/config/riscv/riscv-opts.h                |  1 +
>   gcc/config/riscv/riscv-protos.h              |  4 +-
>   gcc/config/riscv/riscv.cc                    | 77 +++++++++++++++++++-
>   gcc/config/riscv/riscv.h                     |  2 +
>   gcc/config/riscv/riscv.md                    |  9 +++
>   gcc/config/riscv/riscv.opt                   |  3 +
>   gcc/testsuite/gcc.target/riscv/large-model.c | 11 +++
>   9 files changed, 127 insertions(+), 7 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/large-model.c
> 
> @@ -312,9 +313,15 @@
>   })
>   
>   (define_predicate "call_insn_operand"
> -  (ior (match_operand 0 "absolute_symbolic_operand")
> -       (match_operand 0 "plt_symbolic_operand")
> -       (match_operand 0 "register_operand")))
> +  (match_operand 0 "general_operand")
> +{
> +  if (riscv_cmodel == CM_LARGE)
> +    return register_operand (op, mode);
> +  else
> +    return (absolute_symbolic_operand (op, mode) ||
> +	    plt_symbolic_operand (op, mode) ||
> +	    register_operand (op, mode));
> +})
Formatting nit.  When wrapping a long line, bring the operator down to 
the next line, indented just beyond the open paren.  Like this:

     return (absolute_symbolic_oeprand (op, mode)
             || plt_symbolic_operand (op, mode)
             || register_operand (op, mode);


Also make sure to use a tab when indenting something 8 spaces.  It's an 
annoyance, but it's the standard way things are formatted in GCC.  THere 
are some scripts in the contrib subdirectory which can help find 
formatting problems, though I'm not sure they work on .md files.

> @@ -1972,7 +1992,19 @@ static rtx
>   riscv_force_address (rtx x, machine_mode mode)
>   {
>     if (!riscv_legitimate_address_p (mode, x, false))
> -    x = force_reg (Pmode, x);
> +    {
> +      if (can_create_pseudo_p ())
> +	return force_reg (Pmode, x);
Note that $ra is fixed now.  So if you need a scratch register, you can 
fall back to $ra.

More importantly, what are the circumstances where you can be asked to 
force an address after the register allocation/reloading phase is 
complete?  Or does it happen within the register allocators (the latter 
would be an indicator we need a secondary reload).


> @@ -5665,6 +5697,9 @@ riscv_size_ok_for_small_data_p (int size)
>   static bool
>   riscv_in_small_data_p (const_tree x)
>   {
> +  if (riscv_cmodel == CM_LARGE)
> +    return false;
> +
>     if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL)
>       return false;
How does large code model impact our ability to access small data 
through $gp?  Aren't they independent?

> +void
> +riscv_asm_output_pool_epilogue (FILE *f, const char *, tree,
> +				HOST_WIDE_INT offset)
> +{
> +  /* When using per-function literal pools, we must ensure that any code
> +     section is aligned to the minimal instruction length, lest we get
> +     errors from the assembler re "unaligned instructions".  */
> +  if ((offset & 3) && riscv_can_use_per_function_literal_pools_p ())
> +    ASM_OUTPUT_ALIGN (f, 2);
> +}
So the comment implies you're aligning the section.  If that were the 
case, then why doesn't the function alignment come from 
FUNCTION_BOUNDARY when we first start emitting the function?

Or is it the case that the comment is incorrect and you've actually got 
mixed code/rodata?




>   
> +(define_insn "*large_load_address"
> +  [(set (match_operand:DI 0 "register_operand" "=r")
> +        (mem:DI (match_operand 1 "pcrel_symbol_operand" "")))]
> +  "TARGET_64BIT && riscv_cmodel == CM_LARGE"
> +  "ld\t%0,%1"
> +  [(set_attr "type" "load")
> +   (set (attr "length") (const_int 8))])
So it would seem like you're relying on the assembler to expand the ld? 
Is there any reasonable way to expose this properly to the compiler? 
I'd start by emitting the right instructions in the template.  Once 
that's working, then we could look to split the components into distinct 
insns.

I also worry that we've got a mem->reg move instruction that is not 
implemented in the standard movXX patterns.  Traditionally that's been a 
recipe for problems.  It was certainly a requirement for reload, but I 
don't know offhand if it's a hard requirement for LRA.

Can you try to merge that in with the standard movdi pattern?

Overall it looks pretty good.   Does Andestech have a copyright 
assignment in place?  Or are you contributing under the DCO rule?

https://gcc.gnu.org/dco.html

JeJeff

Re: [RFC] RISC-V: Support -mcmodel=large.

[Kito Cheng]

> Overall it looks pretty good.   Does Andestech have a copyright
> assignment in place?  Or are you contributing under the DCO rule?

Kuan-Lin Chen is Andestech folk, and Andestech have signed copyright
assignment for most GNU toolchain components I believe :)

> https://gcc.gnu.org/dco.html
>
> JeJeff