* [PATCH] RISC-V: Fix vsetivli instruction asm for IMM AVL
@ 2023-01-03 1:39 juzhe.zhong
2023-01-26 19:12 ` Kito Cheng
0 siblings, 1 reply; 2+ messages in thread
From: juzhe.zhong @ 2023-01-03 1:39 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Notice that we should used vsetivli zero,4 instead of vsetvli zero,4
for IMM AVL (0 ~ 31) according to RVV ISA.
This patch fix vsetivli instruction asm bug.
gcc/ChangeLog:
* config/riscv/vector.md:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vle-constraint-1.c:
---
gcc/config/riscv/vector.md | 2 +-
.../gcc.target/riscv/rvv/base/vle-constraint-1.c | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3d0174f98a2..4e93b7fead5 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -561,7 +561,7 @@
(match_operand 3 "const_int_operand" "i")
(match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
"TARGET_VECTOR"
- "vsetvli\tzero,%0,e%1,%m2,t%p3,m%p4"
+ "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
[(set_attr "type" "vsetvl")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
index b7cf98bfd9f..8d01e2082f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
@@ -6,7 +6,7 @@
/*
** f1:
-** vsetvli\tzero,4,e32,m1,tu,ma
+** vsetivli\tzero,4,e32,m1,tu,ma
** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
** vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -23,7 +23,7 @@ void f1 (float * in, float *out)
** f2:
** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** vsetvli\tzero,4,e32,m1,ta,ma
+** vsetivli\tzero,4,e32,m1,ta,ma
** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
** ret
@@ -41,7 +41,7 @@ void f2 (float * in, float *out)
** f3:
** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** vsetvli\tzero,4,e32,m1,tu,mu
+** vsetivli\tzero,4,e32,m1,tu,mu
** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -58,7 +58,7 @@ void f3 (float * in, float *out)
/*
** f4:
-** vsetvli\tzero,4,e8,mf8,tu,ma
+** vsetivli\tzero,4,e8,mf8,tu,ma
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
** vse8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -75,7 +75,7 @@ void f4 (int8_t * in, int8_t *out)
** f5:
** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** vsetvli\tzero,4,e8,mf8,ta,ma
+** vsetivli\tzero,4,e8,mf8,ta,ma
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
** ret
@@ -93,7 +93,7 @@ void f5 (int8_t * in, int8_t *out)
** f6:
** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** vsetvli\tzero,4,e8,mf8,tu,mu
+** vsetivli\tzero,4,e8,mf8,tu,mu
** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
--
2.36.3
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] RISC-V: Fix vsetivli instruction asm for IMM AVL
2023-01-03 1:39 [PATCH] RISC-V: Fix vsetivli instruction asm for IMM AVL juzhe.zhong
@ 2023-01-26 19:12 ` Kito Cheng
0 siblings, 0 replies; 2+ messages in thread
From: Kito Cheng @ 2023-01-26 19:12 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, palmer
[-- Attachment #1: Type: text/plain, Size: 3402 bytes --]
committed, thanks.
On Tue, Jan 3, 2023 at 9:40 AM <juzhe.zhong@rivai.ai> wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> Notice that we should used vsetivli zero,4 instead of vsetvli zero,4
> for IMM AVL (0 ~ 31) according to RVV ISA.
>
> This patch fix vsetivli instruction asm bug.
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md:
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vle-constraint-1.c:
>
> ---
> gcc/config/riscv/vector.md | 2 +-
> .../gcc.target/riscv/rvv/base/vle-constraint-1.c | 12 ++++++------
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 3d0174f98a2..4e93b7fead5 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -561,7 +561,7 @@
> (match_operand 3 "const_int_operand" "i")
> (match_operand 4 "const_int_operand" "i")]
> UNSPEC_VSETVL))]
> "TARGET_VECTOR"
> - "vsetvli\tzero,%0,e%1,%m2,t%p3,m%p4"
> + "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
> [(set_attr "type" "vsetvl")
> (set_attr "mode" "<MODE>")])
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
> index b7cf98bfd9f..8d01e2082f8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
> @@ -6,7 +6,7 @@
>
> /*
> ** f1:
> -** vsetvli\tzero,4,e32,m1,tu,ma
> +** vsetivli\tzero,4,e32,m1,tu,ma
> ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> ** vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
> @@ -23,7 +23,7 @@ void f1 (float * in, float *out)
> ** f2:
> ** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
> ** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> -** vsetvli\tzero,4,e32,m1,ta,ma
> +** vsetivli\tzero,4,e32,m1,ta,ma
> ** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> ** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
> ** ret
> @@ -41,7 +41,7 @@ void f2 (float * in, float *out)
> ** f3:
> ** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
> ** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> -** vsetvli\tzero,4,e32,m1,tu,mu
> +** vsetivli\tzero,4,e32,m1,tu,mu
> ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> ** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> ** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
> @@ -58,7 +58,7 @@ void f3 (float * in, float *out)
>
> /*
> ** f4:
> -** vsetvli\tzero,4,e8,mf8,tu,ma
> +** vsetivli\tzero,4,e8,mf8,tu,ma
> ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> ** vse8\.v\tv[0-9]+,0\([a-x0-9]+\)
> @@ -75,7 +75,7 @@ void f4 (int8_t * in, int8_t *out)
> ** f5:
> ** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
> ** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> -** vsetvli\tzero,4,e8,mf8,ta,ma
> +** vsetivli\tzero,4,e8,mf8,ta,ma
> ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
> ** ret
> @@ -93,7 +93,7 @@ void f5 (int8_t * in, int8_t *out)
> ** f6:
> ** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
> ** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> -** vsetvli\tzero,4,e8,mf8,tu,mu
> +** vsetivli\tzero,4,e8,mf8,tu,mu
> ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
> --
> 2.36.3
>
>
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2023-01-03 1:39 [PATCH] RISC-V: Fix vsetivli instruction asm for IMM AVL juzhe.zhong
2023-01-26 19:12 ` Kito Cheng
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