[PATCH v2 1/2] riscv-cores.def: Fix description of RISCV_CORE() macro

[PATCH v2 1/2] riscv-cores.def: Fix description of RISCV_CORE() macro

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

The current description of RISCV_CORE() does not match the
implementation. This commit provides a fix for that.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def: Fix comment.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-cores.def | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index ecb5e213d98..60bcadbb034 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -21,15 +21,13 @@
 
    Before using #include to read this file, define a macro:
 
-      RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO)
+      RISCV_CORE(CORE_NAME, ARCH, TUNE_INFO)
 
    The CORE_NAME is the name of the core, represented as a string.
-   The ARCH is the default arch of the core, represented as a string,
-   can be NULL if no default arch.
-   The MICRO_ARCH is the name of the core for which scheduling decisions
-   will be made, represented as an identifier.
-   The TUNE_INFO is the detail cost model for this core, represented as an
-   identifier, reference to riscv-tunes.def.  */
+   The ARCH is a string describing the supported RISC-V ISA (e.g. "rv32i"
+   or "rv64gc_zifencei").
+   The TUNE_INFO is a string that references the detail tuning information
+   for this core (refer to riscv_tune_info_table for possible values).  */
 
 RISCV_CORE("sifive-e20",      "rv32imc",    "rocket")
 RISCV_CORE("sifive-e21",      "rv32imac",   "rocket")
-- 
2.35.3

[PATCH v2 2/2] riscv-cores.def: Add T-Head XuanTie C906

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-thead-c906.c: New test.

Changes since v1:
* Adding test case
* Reword commit message

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-cores.def               |  2 ++
 .../gcc.target/riscv/mcpu-thead-c906.c         | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 60bcadbb034..dd97ece376f 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
+RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
+
 #undef RISCV_CORE
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
new file mode 100644
index 00000000000..f579e7e2215
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */
+/* T-Head XuanTie C906 => rv64imafdc */
+
+#if !((__riscv_xlen == 64)		\
+      && !defined(__riscv_32e)		\
+      && defined(__riscv_mul)		\
+      && defined(__riscv_atomic)	\
+      && (__riscv_flen == 64)		\
+      && defined(__riscv_compressed))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+  return 0;
+}
-- 
2.35.3

Re: [PATCH v2 1/2] riscv-cores.def: Fix description of RISCV_CORE() macro

[Kito Cheng]

LGTM, thanks for correcting the comments !

On Wed, Jun 15, 2022 at 7:47 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The current description of RISCV_CORE() does not match the
> implementation. This commit provides a fix for that.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-cores.def: Fix comment.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv-cores.def | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> index ecb5e213d98..60bcadbb034 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -21,15 +21,13 @@
>
>     Before using #include to read this file, define a macro:
>
> -      RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO)
> +      RISCV_CORE(CORE_NAME, ARCH, TUNE_INFO)
>
>     The CORE_NAME is the name of the core, represented as a string.
> -   The ARCH is the default arch of the core, represented as a string,
> -   can be NULL if no default arch.
> -   The MICRO_ARCH is the name of the core for which scheduling decisions
> -   will be made, represented as an identifier.
> -   The TUNE_INFO is the detail cost model for this core, represented as an
> -   identifier, reference to riscv-tunes.def.  */
> +   The ARCH is a string describing the supported RISC-V ISA (e.g. "rv32i"
> +   or "rv64gc_zifencei").
> +   The TUNE_INFO is a string that references the detail tuning information
> +   for this core (refer to riscv_tune_info_table for possible values).  */
>
>  RISCV_CORE("sifive-e20",      "rv32imc",    "rocket")
>  RISCV_CORE("sifive-e21",      "rv32imac",   "rocket")
> --
> 2.35.3
>

Re: [PATCH v2 2/2] riscv-cores.def: Add T-Head XuanTie C906

[Kito Cheng]

LGTM, thanks!

On Wed, Jun 15, 2022 at 7:48 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
> The C906 is shipped for quite some time (it is the core of the Allwinner D1).
> Note, that the tuning struct for the C906 is already part of GCC (it is
> also name "thead-c906").
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/mcpu-thead-c906.c: New test.
>
> Changes since v1:
> * Adding test case
> * Reword commit message
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv-cores.def               |  2 ++
>  .../gcc.target/riscv/mcpu-thead-c906.c         | 18 ++++++++++++++++++
>  2 files changed, 20 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
>
> diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> index 60bcadbb034..dd97ece376f 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
>  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
>  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
>
> +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
> +
>  #undef RISCV_CORE
> diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
> new file mode 100644
> index 00000000000..f579e7e2215
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
> +/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */
> +/* T-Head XuanTie C906 => rv64imafdc */
> +
> +#if !((__riscv_xlen == 64)             \
> +      && !defined(__riscv_32e)         \
> +      && defined(__riscv_mul)          \
> +      && defined(__riscv_atomic)       \
> +      && (__riscv_flen == 64)          \
> +      && defined(__riscv_compressed))
> +#error "unexpected arch"
> +#endif
> +
> +int main()
> +{
> +  return 0;
> +}
> --
> 2.35.3
>