Re: Re: [PATCH 2/3 V2] RISC-V: Enable basic auto-vectorization for RVV

[Kito Cheng <kito.cheng@gmail.com>]

On Thu, Apr 20, 2023 at 5:07 PM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> >> With --param=riscv-autovec-preference=fixed-vlmax, however, the output is
> >> reasonable.  BTW please use --param instead of -param in the description to
> >> avoid confusion.
> >>Now the patches don't explicitly note that they only work for certain marchs,
> >>configurations or so but they certainly shouldn't introduce ICEs for
> >>unsupported configurations.
>
> Address comments.  And fix that soon. Thank you so much.
>
> >>Are the "fixed-vlmax" vs "scalable" names based on ARM's SVE?  I haven't thought
> >>this through but I think I'd prefer "fixed" vs "varying" or more explicitly
> >>"fixed vector size" vs "dynamic vector size".  Certainly room for discussion here.
> >>What about the -mriscv-vector-bits=... (which would be vlen in v-spec parlance)
> >>from your "rvv-next" branch?  Is this orthogonal to the new parameter here? Are you
> >>thinking of introducing this as well?
>
> The current compile options are suggested by Kito. They are internal GCC compile option.
> I was trying to add -mriscv-vector-bits-...., However, it was objected by LLVM community.
> https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/33


Wait, -mriscv-vector-bits= isn't objected by LLVM, what they objected
to is lmul option.
LLVM community has try to implmenat that:
https://reviews.llvm.org/D145088

But personally I would prefer not to rush to implement that feature on upstream,
we could implement that and have more conversion with LLVM community and then
document that into https://github.com/riscv-non-isa/rvv-intrinsic-doc
or https://github.com/riscv-non-isa/riscv-toolchain-conventions

> I think in case of compile options, Kito may give more comments since he is the RISC-V ABI and convention maintainer.
> I develop this patch following his order.