Re: [PATCH v1 1/3] RISC-V: add consecutive_bits_operand predicate

[Philipp Tomsich <philipp.tomsich@vrull.eu>]

Thanks, applied to master!


On Tue, 7 Jun 2022 at 12:26, Kito Cheng <kito.cheng@gmail.com> wrote:
>
> LGTM
>
>
> On Wed, May 25, 2022 at 5:48 AM Philipp Tomsich
> <philipp.tomsich@vrull.eu> wrote:
> >
> > Provide an easy way to constrain for constants that are a a single,
> > consecutive run of ones.
> >
> > gcc/ChangeLog:
> >
> >         * config/riscv/predicates.md (consecutive_bits_operand):
> >           Implement new predicate.
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > ---
> >
> >  gcc/config/riscv/predicates.md | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> > index c37caa2502b..90db5dfcdd5 100644
> > --- a/gcc/config/riscv/predicates.md
> > +++ b/gcc/config/riscv/predicates.md
> > @@ -243,3 +243,14 @@ (define_predicate "const63_operand"
> >  (define_predicate "imm5_operand"
> >    (and (match_code "const_int")
> >         (match_test "INTVAL (op) < 5")))
> > +
> > +;; A CONST_INT operand that consists of a single run of consecutive set bits.
> > +(define_predicate "consecutive_bits_operand"
> > +  (match_code "const_int")
> > +{
> > +       unsigned HOST_WIDE_INT val = UINTVAL (op);
> > +       if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0)
> > +               return false;
> > +
> > +       return true;
> > +})
> > --
> > 2.34.1
> >