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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org,
	Christoph Muellner <christoph.muellner@vrull.eu>,
	 Palmer Dabbelt <palmer@rivosinc.com>,
	Kito Cheng <kito.cheng@gmail.com>,
	 Vineet Gupta <vineetg@rivosinc.com>,
	Jeff Law <jlaw@ventanamicro.com>
Subject: Re: [PATCH] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w
Date: Fri, 18 Nov 2022 20:57:59 +0100	[thread overview]
Message-ID: <CAAeLtUBRwKKgti677xSBmqGFUd-CepZpM6JmKMW_=H0YzUU9mA@mail.gmail.com> (raw)
In-Reply-To: <0ba55dec-3d59-a63e-5e5d-c99cf89f64ca@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 989 bytes --]

Applied to master. Thanks.
--Philipp.


On Fri, 18 Nov 2022 at 20:52, Jeff Law <jeffreyalaw@gmail.com> wrote:

>
> On 11/8/22 12:57, Philipp Tomsich wrote:
> > gcc/ChangeLog:
> >
> >       * config/riscv/bitmanip.md: Handle corner-cases for combine
> >       when chaining slli(.uw)? + addw
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/zba-shNadd-04.c: New test.
>
> OK.
>
> Something to consider.  We're gaining a lot of
>
> (subreg:SI (reg:DI) 0) kinds of operands.
>
>
> Would it make sense to make an operand predicate that accepted
>
> (reg:SI) or (subreg:SI (reg:DI) 0)?
>
>
> It will reduce my compaints about subregs :-)  But the real reason I'm
> suggesting we consider adding such a predicate is, AFIACT, it it gives
> combine a chance to eliminate the subreg.  I haven't actually tested
> this, but it seems like it might be worth a quick experiment independent
> of these patches (and probably targeted towards gcc-14 rather than gcc-13).
>
>
>
> jeff
>
>

  reply	other threads:[~2022-11-18 19:58 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-08 19:57 Philipp Tomsich
2022-11-18 19:52 ` Jeff Law
2022-11-18 19:57   ` Philipp Tomsich [this message]
2022-11-18 19:59   ` Philipp Tomsich

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