[PATCH V3 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

[PATCH V3 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

[Liao Shihua]

Update v2 -> v3:
  1. Change pattern mode form X to GPR in orcb, clmul, and brev8.
  2. Add emulated testsuite.
  3. Removed duplicate testsuite between built-in and intrinsic. 
  4. Typo fix.

Update v1 -> v2:
  1. Rename *_intrinsic-* to *_intrinsic-XLEN.
  2. Typo fix.
  3. Intrinsics with immediate arguments will use marcos at O0 .

It's a little patch add just provides a mapping from the RV intrinsics to the builtin 
names within GCC.

Liao Shihua (3):
  RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function
    testsuites
  RISC-V: Add C intrinsic for Scalar Crypto Extension
  RISC-V: Add C intrinsic for Scalar Bitmanip Extension

 gcc/config.gcc                                |   2 +-
 gcc/config/riscv/bitmanip.md                  |  10 +-
 gcc/config/riscv/crypto.md                    |   4 +-
 gcc/config/riscv/riscv-builtins.cc            |  22 ++
 gcc/config/riscv/riscv-cmo.def                |  12 +-
 gcc/config/riscv/riscv-ftypes.def             |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def      |  22 +-
 gcc/config/riscv/riscv_bitmanip.h             | 297 +++++++++++++++++
 gcc/config/riscv/riscv_crypto.h               | 309 ++++++++++++++++++
 .../riscv/scalar_bitmanip_intrinsic-32.c      |  96 ++++++
 .../scalar_bitmanip_intrinsic-64-emulated.c   |  32 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c      | 114 +++++++
 .../riscv/scalar_crypto_intrinsic-32.c        | 114 +++++++
 .../riscv/scalar_crypto_intrinsic-64.c        | 122 +++++++
 gcc/testsuite/gcc.target/riscv/zbbw.c         |  26 --
 gcc/testsuite/gcc.target/riscv/zbc32.c        |  23 --
 gcc/testsuite/gcc.target/riscv/zbc64.c        |  23 --
 gcc/testsuite/gcc.target/riscv/zbkb32.c       |  18 -
 gcc/testsuite/gcc.target/riscv/zbkb64.c       |   5 -
 gcc/testsuite/gcc.target/riscv/zbkc32.c       |  17 -
 gcc/testsuite/gcc.target/riscv/zbkc64.c       |  17 -
 gcc/testsuite/gcc.target/riscv/zbkx32.c       |  18 -
 gcc/testsuite/gcc.target/riscv/zbkx64.c       |  18 -
 gcc/testsuite/gcc.target/riscv/zknd32-2.c     |  28 --
 gcc/testsuite/gcc.target/riscv/zknd64-2.c     |  42 ---
 gcc/testsuite/gcc.target/riscv/zkne32-2.c     |  28 --
 gcc/testsuite/gcc.target/riscv/zkne64-2.c     |  34 --
 .../gcc.target/riscv/zknh-sha256-32.c         |  10 -
 .../gcc.target/riscv/zknh-sha256-64.c         |  28 --
 .../gcc.target/riscv/zknh-sha512-32.c         |  42 ---
 .../gcc.target/riscv/zknh-sha512-64.c         |  31 --
 gcc/testsuite/gcc.target/riscv/zksed32-2.c    |  29 --
 gcc/testsuite/gcc.target/riscv/zksed64-2.c    |  29 --
 gcc/testsuite/gcc.target/riscv/zksh32.c       |  19 --
 gcc/testsuite/gcc.target/riscv/zksh64.c       |  19 --
 35 files changed, 1142 insertions(+), 520 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

-- 
2.34.1

[PATCH V3 1/3] RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function testsuites

[Liao Shihua]

The serials patch provides a mapping from the RV intrinsics to the builtin names.
There are some duplicates testsuites between intrinsic and built-in function.
Remove the Scalar Bitmanip and Scalar Crypto Built-In function testsuites 
that will be included in the intrinsic functions.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zbkb32.c: Remove __builtin_riscv_(un)zip,__builtin_riscv_brev8.
        * gcc.target/riscv/zbkb64.c: Remove __builtin_riscv_brev8.
        * gcc.target/riscv/zbbw.c: Removed.
        * gcc.target/riscv/zbc32.c: Removed.
        * gcc.target/riscv/zbc64.c: Removed.
        * gcc.target/riscv/zbkc32.c: Removed.
        * gcc.target/riscv/zbkc64.c: Removed.
        * gcc.target/riscv/zbkx32.c: Removed.
        * gcc.target/riscv/zbkx64.c: Removed.
        * gcc.target/riscv/zknd32-2.c: Removed.
        * gcc.target/riscv/zknd64-2.c: Removed.
        * gcc.target/riscv/zkne32-2.c: Removed.
        * gcc.target/riscv/zkne64-2.c: Removed.
        * gcc.target/riscv/zknh-sha256-32.c: Removed.
        * gcc.target/riscv/zknh-sha256-64.c: Removed.
        * gcc.target/riscv/zknh-sha512-32.c: Removed.
        * gcc.target/riscv/zknh-sha512-64.c: Removed.
        * gcc.target/riscv/zksed32-2.c: Removed.
        * gcc.target/riscv/zksed64-2.c: Removed.
        * gcc.target/riscv/zksh32.c: Removed.
        * gcc.target/riscv/zksh64.c: Removed.

---
 gcc/testsuite/gcc.target/riscv/zbbw.c         | 26 ------------
 gcc/testsuite/gcc.target/riscv/zbc32.c        | 23 ----------
 gcc/testsuite/gcc.target/riscv/zbc64.c        | 23 ----------
 gcc/testsuite/gcc.target/riscv/zbkb32.c       | 18 --------
 gcc/testsuite/gcc.target/riscv/zbkb64.c       |  5 ---
 gcc/testsuite/gcc.target/riscv/zbkc32.c       | 17 --------
 gcc/testsuite/gcc.target/riscv/zbkc64.c       | 17 --------
 gcc/testsuite/gcc.target/riscv/zbkx32.c       | 18 --------
 gcc/testsuite/gcc.target/riscv/zbkx64.c       | 18 --------
 gcc/testsuite/gcc.target/riscv/zknd32-2.c     | 28 -------------
 gcc/testsuite/gcc.target/riscv/zknd64-2.c     | 42 -------------------
 gcc/testsuite/gcc.target/riscv/zkne32-2.c     | 28 -------------
 gcc/testsuite/gcc.target/riscv/zkne64-2.c     | 34 ---------------
 .../gcc.target/riscv/zknh-sha256-32.c         | 10 -----
 .../gcc.target/riscv/zknh-sha256-64.c         | 28 -------------
 .../gcc.target/riscv/zknh-sha512-32.c         | 42 -------------------
 .../gcc.target/riscv/zknh-sha512-64.c         | 31 --------------
 gcc/testsuite/gcc.target/riscv/zksed32-2.c    | 29 -------------
 gcc/testsuite/gcc.target/riscv/zksed64-2.c    | 29 -------------
 gcc/testsuite/gcc.target/riscv/zksh32.c       | 19 ---------
 gcc/testsuite/gcc.target/riscv/zksh64.c       | 19 ---------
 21 files changed, 504 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed32-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed64-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c
deleted file mode 100644
index bdf6b0c4ec5..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zbbw.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
-
-int
-clz (int i)
-{
-  return __builtin_clz (i);
-}
-
-int
-ctz (int i)
-{
-  return __builtin_ctz (i);
-}
-
-int
-popcount (int i)
-{
-  return __builtin_popcount (i);
-}
-
-
-/* { dg-final { scan-assembler-times {\mclzw} 1 } } */
-/* { dg-final { scan-assembler-times {\mctzw} 1 } } */
-/* { dg-final { scan-assembler-times {\mcpopw} 1 } } */
-/* { dg-final { scan-assembler-not "andi\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbc32.c b/gcc/testsuite/gcc.target/riscv/zbc32.c
deleted file mode 100644
index 049ea95c56b..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zbc32.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zbc -mabi=ilp32" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_clmul(rs1, rs2);
-}
-
-uint32_t foo2(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_clmulh(rs1, rs2);
-}
-
-uint32_t foo3(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_clmulr(rs1, rs2);
-}
-
-/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
-/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */
-/* { dg-final { scan-assembler-times {\mclmulr} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbc64.c b/gcc/testsuite/gcc.target/riscv/zbc64.c
deleted file mode 100644
index 69dadd1ca88..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zbc64.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zbc -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-#include <stdint-gcc.h>
-
-uint64_t foo1(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_clmul(rs1, rs2);
-}
-
-uint64_t foo2(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_clmulh(rs1, rs2);
-}
-
-uint64_t foo3(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_clmulr(rs1, rs2);
-}
-
-/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
-/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */
-/* { dg-final { scan-assembler-times {\mclmulr} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c
index 841f5e0d8e3..8f6afd1eabb 100644
--- a/gcc/testsuite/gcc.target/riscv/zbkb32.c
+++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c
@@ -14,23 +14,5 @@ uint32_t foo2(uint8_t rs1, uint8_t rs2)
     return __builtin_riscv_packh(rs1, rs2);
 }
 
-uint32_t foo3(uint32_t rs1)
-{
-    return __builtin_riscv_brev8(rs1);
-}
-
-uint32_t foo4(uint32_t rs1)
-{
-    return __builtin_riscv_zip(rs1);
-}
-
-uint32_t foo5(uint32_t rs1)
-{
-    return __builtin_riscv_unzip(rs1);
-}
-
 /* { dg-final { scan-assembler-times "pack\t" 1 } } */
 /* { dg-final { scan-assembler-times {\mpackh} 1 } } */
-/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */
-/* { dg-final { scan-assembler-times "\tzip\t" 1 } } */
-/* { dg-final { scan-assembler-times {\munzip} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c
index 8b6a0bff1f2..492151ebd7b 100644
--- a/gcc/testsuite/gcc.target/riscv/zbkb64.c
+++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c
@@ -18,11 +18,6 @@ uint64_t foo3(uint16_t rs1, uint16_t rs2)
     return __builtin_riscv_packw(rs1, rs2);
 }
 
-uint64_t foo4(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_brev8(rs1);
-}
 /* { dg-final { scan-assembler-times "pack\t" 1 } } */
 /* { dg-final { scan-assembler-times {\mpackh} 1 } } */
 /* { dg-final { scan-assembler-times {\mpackw} 1 } } */
-/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c
deleted file mode 100644
index 6d2a8fffbc1..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zbkc32.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_clmul(rs1, rs2);
-}
-
-uint32_t foo2(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_clmulh(rs1, rs2);
-}
-
-/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
-/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c
deleted file mode 100644
index 3708fb5fbb1..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zbkc64.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zbkc -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-#include <stdint-gcc.h>
-
-uint64_t foo1(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_clmul(rs1, rs2);
-}
-
-uint64_t foo2(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_clmulh(rs1, rs2);
-}
-
-/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
-/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c
deleted file mode 100644
index b41fd90de51..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zbkx32.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zbkx -mabi=ilp32" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint32_t foo3(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_xperm8(rs1, rs2);
-}
-
-uint32_t foo4(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_xperm4(rs1, rs2);
-}
-
-/* { dg-final { scan-assembler-times {\mxperm8} 1 } } */
-/* { dg-final { scan-assembler-times {\mxperm4} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c
deleted file mode 100644
index 9ed42b40718..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zbkx64.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zbkx -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint64_t foo1(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_xperm8(rs1, rs2);
-}
-
-uint64_t foo2(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_xperm4(rs1, rs2);
-}
-
-/* { dg-final { scan-assembler-times {\mxperm8} 1 } } */
-/* { dg-final { scan-assembler-times {\mxperm4} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknd32-2.c b/gcc/testsuite/gcc.target/riscv/zknd32-2.c
deleted file mode 100644
index f3549e786c7..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zknd32-2.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zknd -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_aes32dsi(rs1,rs2,0);
-}
-
-uint32_t foo2(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_aes32dsmi(rs1,rs2,0);
-}
-
-uint32_t foo3(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_aes32dsi(rs1,rs2,3);
-}
-
-uint32_t foo4(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_aes32dsmi(rs1,rs2,3);
-}
-
-/* { dg-final { scan-assembler-times "aes32dsi" 2 } } */
-/* { dg-final { scan-assembler-times "aes32dsmi" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknd64-2.c b/gcc/testsuite/gcc.target/riscv/zknd64-2.c
deleted file mode 100644
index cd0e79d60f5..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zknd64-2.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zknd -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint64_t foo1(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_aes64ds(rs1,rs2);
-}
-
-uint64_t foo2(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_aes64dsm(rs1,rs2);
-}
-
-uint64_t foo3(uint64_t rs1, unsigned rnum)
-{
-    return __builtin_riscv_aes64ks1i(rs1,0);
-}
-
-uint64_t foo3a(uint64_t rs1, unsigned rnum)
-{
-    return __builtin_riscv_aes64ks1i(rs1,10);
-}
-
-uint64_t foo4(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_aes64ks2(rs1,rs2);
-}
-
-uint64_t foo5(uint64_t rs1)
-{
-    return __builtin_riscv_aes64im(rs1);
-}
-
-/* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */
-/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */
-/* { dg-final { scan-assembler-times "aes64ks1i" 2 } } */
-/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
-/* { dg-final { scan-assembler-times {\maes64im} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/riscv/zkne32-2.c b/gcc/testsuite/gcc.target/riscv/zkne32-2.c
deleted file mode 100644
index 4ad1cdcdd80..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zkne32-2.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zkne -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_aes32esi(rs1, rs2, 0);
-}
-
-uint32_t foo2(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_aes32esmi(rs1, rs2, 0);
-}
-
-uint32_t foo3(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_aes32esi(rs1, rs2, 3);
-}
-
-uint32_t foo4(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_aes32esmi(rs1, rs2, 3);
-}
-
-/* { dg-final { scan-assembler-times "aes32esi" 2 } } */
-/* { dg-final { scan-assembler-times "aes32esmi" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zkne64-2.c b/gcc/testsuite/gcc.target/riscv/zkne64-2.c
deleted file mode 100644
index 144c394365b..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zkne64-2.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zkne -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint64_t foo1(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_aes64es(rs1,rs2);
-}
-
-uint64_t foo2(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_aes64esm(rs1,rs2);
-}
-
-uint64_t foo3(uint64_t rs1, unsigned rnum)
-{
-    return __builtin_riscv_aes64ks1i(rs1,0);
-}
-
-uint64_t foo3a(uint64_t rs1, unsigned rnum)
-{
-    return __builtin_riscv_aes64ks1i(rs1,10);
-}
-uint64_t foo4(uint64_t rs1, uint64_t rs2)
-{
-    return __builtin_riscv_aes64ks2(rs1,rs2);
-}
-
-/* { dg-final { scan-assembler-times "aes64es\t" 1 } } */
-/* { dg-final { scan-assembler-times "aes64esm" 1 } } */
-/* { dg-final { scan-assembler-times "aes64ks1i" 2 } } */
-/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c b/gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
deleted file mode 100644
index c51b143a8a5..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include "zknh-sha256-64.c"
-
-/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
-/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
-/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
-/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c b/gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
deleted file mode 100644
index 2ef37601e6f..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-unsigned int foo1(unsigned int rs1)
-{
-    return __builtin_riscv_sha256sig0(rs1);
-}
-
-unsigned int foo2(unsigned int rs1)
-{
-    return __builtin_riscv_sha256sig1(rs1);
-}
-
-unsigned int foo3(unsigned int rs1)
-{
-    return __builtin_riscv_sha256sum0(rs1);
-}
-
-unsigned int foo4(unsigned int rs1)
-{
-    return __builtin_riscv_sha256sum1(rs1);
-}
-
-/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
-/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
-/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
-/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
deleted file mode 100644
index f2bcae36a1f..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sha512sig0h(rs1,rs2);
-}
-
-uint32_t foo2(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sha512sig0l(rs1,rs2);
-}
-
-uint32_t foo3(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sha512sig1h(rs1,rs2);
-}
-
-uint32_t foo4(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sha512sig1l(rs1,rs2);
-}
-
-uint32_t foo5(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sha512sum0r(rs1,rs2);
-}
-
-uint32_t foo6(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sha512sum1r(rs1,rs2);
-}
-
-/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
-/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
-/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
-/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
-/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
-/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
deleted file mode 100644
index 4f248575e66..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint64_t foo1(uint64_t rs1)
-{
-    return __builtin_riscv_sha512sig0(rs1);
-}
-
-uint64_t foo2(uint64_t rs1)
-{
-    return __builtin_riscv_sha512sig1(rs1);
-}
-
-uint64_t foo3(uint64_t rs1)
-{
-    return __builtin_riscv_sha512sum0(rs1);
-}
-
-uint64_t foo4(uint64_t rs1)
-{
-    return __builtin_riscv_sha512sum1(rs1);
-}
-
-
-/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
-/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
-/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
-/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksed32-2.c b/gcc/testsuite/gcc.target/riscv/zksed32-2.c
deleted file mode 100644
index cee8cc217a9..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zksed32-2.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zksed -mabi=ilp32" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sm4ks(rs1,rs2,0);
-}
-
-uint32_t foo2(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sm4ed(rs1,rs2,0);
-}
-
-uint32_t foo3(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sm4ks(rs1,rs2,3);
-}
-
-uint32_t foo4(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sm4ed(rs1,rs2,3);
-}
-
-
-/* { dg-final { scan-assembler-times {\msm4ks} 2 } } */
-/* { dg-final { scan-assembler-times {\msm4ed} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksed64-2.c b/gcc/testsuite/gcc.target/riscv/zksed64-2.c
deleted file mode 100644
index ee20aa1535e..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zksed64-2.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zksed -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sm4ks(rs1,rs2,0);
-}
-
-uint32_t foo2(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sm4ed(rs1,rs2,0);
-}
-
-uint32_t foo3(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sm4ks(rs1,rs2,3);
-}
-
-uint32_t foo4(uint32_t rs1, uint32_t rs2)
-{
-    return __builtin_riscv_sm4ed(rs1,rs2,3);
-}
-
-
-/* { dg-final { scan-assembler-times {\msm4ks} 2 } } */
-/* { dg-final { scan-assembler-times {\msm4ed} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksh32.c b/gcc/testsuite/gcc.target/riscv/zksh32.c
deleted file mode 100644
index c182e557a85..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zksh32.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_zksh -mabi=ilp32" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1)
-{
-    return __builtin_riscv_sm3p0(rs1);
-}
-
-uint32_t foo2(uint32_t rs1)
-{
-    return __builtin_riscv_sm3p1(rs1);
-}
-
-
-/* { dg-final { scan-assembler-times {\msm3p0} 1 } } */
-/* { dg-final { scan-assembler-times {\msm3p1} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksh64.c b/gcc/testsuite/gcc.target/riscv/zksh64.c
deleted file mode 100644
index d794b39f77a..00000000000
--- a/gcc/testsuite/gcc.target/riscv/zksh64.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zksh -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
-
-#include <stdint-gcc.h>
-
-uint32_t foo1(uint32_t rs1)
-{
-    return __builtin_riscv_sm3p0(rs1);
-}
-
-uint32_t foo2(uint32_t rs1)
-{
-    return __builtin_riscv_sm3p1(rs1);
-}
-
-
-/* { dg-final { scan-assembler-times {\msm3p0} 1 } } */
-/* { dg-final { scan-assembler-times {\msm3p1} 1 } } */
-- 
2.34.1

[PATCH V3 2/3] RISC-V: Add C intrinsic for Scalar Crypto Extension

[Liao Shihua]

This patch adds C intrinsics for Scalar Crypto Extension.

gcc/ChangeLog:

        * config.gcc: Include riscv_crypto.h.
        * config/riscv/riscv_crypto.h: New file.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test.
        * gcc.target/riscv/scalar_crypto_intrinsic-64.c: New test.

---
 gcc/config.gcc                                |   2 +-
 gcc/config/riscv/riscv_crypto.h               | 309 ++++++++++++++++++
 .../riscv/scalar_crypto_intrinsic-32.c        | 114 +++++++
 .../riscv/scalar_crypto_intrinsic-64.c        | 122 +++++++
 4 files changed, 546 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..f8483d34ee9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	extra_objs="${extra_objs} thead.o riscv-target-attr.o"
 	d_target_objs="riscv-d.o"
-	extra_headers="riscv_vector.h"
+	extra_headers="riscv_vector.h riscv_crypto.h"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h"
 	;;
diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_crypto.h
new file mode 100644
index 00000000000..14ccc24c98d
--- /dev/null
+++ b/gcc/config/riscv/riscv_crypto.h
@@ -0,0 +1,309 @@
+/* RISC-V 'Scalar Crypto' Extension intrinsics include file.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef __RISCV_SCALAR_CRYPTO_H
+#define __RISCV_SCALAR_CRYPTO_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__riscv_zknd)
+
+#if __riscv_xlen == 32
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsi (rs1,rs2,bs);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32dsmi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32dsmi (rs1,rs2,bs);
+}
+
+#else
+#define __riscv_aes32dsi(x, y, bs) __builtin_riscv_aes32dsi (x, y, bs)
+#define __riscv_aes32dsmi(x, y, bs) __builtin_riscv_aes32dsmi (x, y, bs)
+#endif
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ds (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64ds (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64dsm (uint64_t rs1, uint64_t rs2)
+{
+  return __builtin_riscv_aes64dsm (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64im (uint64_t rs1)
+{
+  return __builtin_riscv_aes64im (rs1);
+}
+#endif
+#endif // __riscv_zknd
+
+#if (defined (__riscv_zknd) || defined (__riscv_zkne)) && (__riscv_xlen == 64)
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks1i (uint64_t rs1, const int rnum)
+{
+  return __builtin_riscv_aes64ks1i (rs1,rnum);
+}
+
+#else
+#define __riscv_aes64ks1i(x, rnum) __builtin_riscv_aes64ks1i (x, rnum)
+#endif
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64ks2 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_aes64ks2 (rs1,rs2);
+}
+
+#endif // __riscv_zknd || __riscv_zkne
+
+#if defined (__riscv_zkne)
+
+#if __riscv_xlen == 32
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32esi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32esi (rs1,rs2,bs);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes32esmi (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_aes32esmi (rs1,rs2,bs);
+}
+
+#else
+#define __riscv_aes32esi(x, y, bs) __builtin_riscv_aes32esi (x, y, bs)
+#define __riscv_aes32esmi(x, y, bs) __builtin_riscv_aes32esmi (x, y, bs)
+#endif
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64es (uint64_t rs1,uint64_t rs2)
+{
+  return __builtin_riscv_aes64es (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_aes64esm (uint64_t rs1,uint64_t rs2)
+{
+  return __builtin_riscv_aes64esm (rs1,rs2);
+}
+#endif
+#endif // __riscv_zkne
+
+#if defined (__riscv_zknh)
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha256sig0 (uint32_t rs1)
+{
+  return __builtin_riscv_sha256sig0 (rs1);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha256sig1 (uint32_t rs1)
+{
+  return __builtin_riscv_sha256sig1 (rs1);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha256sum0 (uint32_t rs1)
+{
+  return __builtin_riscv_sha256sum0 (rs1);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha256sum1 (uint32_t rs1)
+{
+  return __builtin_riscv_sha256sum1 (rs1);
+}
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sig0h (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_sha512sig0h (rs1,rs2);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sig0l (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_sha512sig0l (rs1,rs2);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sig1h (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_sha512sig1h (rs1,rs2);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sig1l (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_sha512sig1l (rs1,rs2);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sum0r (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_sha512sum0r (rs1,rs2);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sum1r (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_sha512sum1r (rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sig0 (uint64_t rs1)
+{
+  return __builtin_riscv_sha512sig0 (rs1);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sig1 (uint64_t rs1)
+{
+  return __builtin_riscv_sha512sig1 (rs1);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sum0 (uint64_t rs1)
+{
+  return __builtin_riscv_sha512sum0 (rs1);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sha512sum1 (uint64_t rs1)
+{
+  return __builtin_riscv_sha512sum1 (rs1);
+}
+#endif
+#endif // __riscv_zknh
+
+#if defined (__riscv_zksh)
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sm3p0 (uint32_t rs1)
+{
+    return __builtin_riscv_sm3p0 (rs1);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sm3p1 (uint32_t rs1)
+{
+    return __builtin_riscv_sm3p1 (rs1);
+}
+
+#endif // __riscv_zksh
+
+#if defined (__riscv_zksed)
+
+#ifdef __OPTIMIZE__
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sm4ed (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_sm4ed (rs1,rs2,bs);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_sm4ks (uint32_t rs1, uint32_t rs2, const int bs)
+{
+  return __builtin_riscv_sm4ks (rs1,rs2,bs);
+}
+
+#else
+#define __riscv_sm4ed(x, y, bs) __builtin_riscv_sm4ed(x, y, bs);
+#define __riscv_sm4ks(x, y, bs) __builtin_riscv_sm4ks(x, y, bs);
+#endif
+
+#endif // __riscv_zksed
+
+#if defined (__cplusplus)
+}
+#endif // __cplusplus
+#endif // __RISCV_SCALAR_CRYPTO_H
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c b/gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
new file mode 100644
index 00000000000..161f67b5c40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
@@ -0,0 +1,114 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zknd_zkne_zknh_zksed_zksh -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_crypto.h"
+
+uint32_t foo1 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_aes32dsi (rs1,rs2,1);
+}
+
+uint32_t foo2 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_aes32dsmi (rs1,rs2,1);
+}
+
+uint32_t foo3 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_aes32esi (rs1,rs2,1);
+}
+
+uint32_t foo4 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_aes32esmi (rs1,rs2,1);
+}
+
+uint32_t foo5 (uint32_t rs1)
+{
+    return __riscv_sha256sig0 (rs1);
+}
+
+uint32_t foo6 (uint32_t rs1)
+{
+    return __riscv_sha256sig1 (rs1);
+}
+
+uint32_t foo7 (uint32_t rs1)
+{
+    return __riscv_sha256sum0 (rs1);
+}
+
+uint32_t foo8 (uint32_t rs1)
+{
+    return __riscv_sha256sum1 (rs1);
+}
+
+uint32_t foo9 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sha512sig0h (rs1,rs2);
+}
+
+uint32_t foo10 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sha512sig0l (rs1,rs2);
+}
+
+uint32_t foo11 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sha512sig1h (rs1,rs2);
+}
+
+uint32_t foo12 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sha512sig1l (rs1,rs2);
+}
+
+uint32_t foo13 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sha512sum0r (rs1,rs2);
+}
+
+uint32_t foo14 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sha512sum1r (rs1,rs2);
+}
+
+uint32_t foo15 (uint32_t rs1)
+{
+    return __riscv_sm3p0 (rs1);
+}
+
+uint32_t foo16 (uint32_t rs1)
+{
+    return __riscv_sm3p1 (rs1);
+}
+
+uint32_t foo17 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sm4ed (rs1,rs2,1);
+}
+
+uint32_t foo18 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sm4ks (rs1,rs2,1);
+}
+
+/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32esi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c b/gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c
new file mode 100644
index 00000000000..a60319ae653
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c
@@ -0,0 +1,122 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zknd_zkne_zknh_zksed_zksh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_crypto.h"
+
+uint64_t foo1 (uint64_t rs1, uint64_t rs2)
+{
+    return __riscv_aes64ds (rs1,rs2);
+}
+
+uint64_t foo2 (uint64_t rs1, uint64_t rs2)
+{
+    return __riscv_aes64dsm (rs1,rs2);
+}
+
+uint64_t foo3 (uint64_t rs1)
+{
+    return __riscv_aes64im (rs1);
+}
+
+uint64_t foo4 (uint64_t rs1)
+{
+    return __riscv_aes64ks1i (rs1,1);
+}
+
+uint64_t foo5 (uint64_t rs1, uint64_t rs2)
+{
+    return __riscv_aes64ks2 (rs1,rs2);
+}
+
+uint64_t foo6 (uint64_t rs1, uint64_t rs2)
+{
+    return __riscv_aes64es (rs1,rs2);
+}
+
+uint64_t foo7 (uint64_t rs1, uint64_t rs2)
+{
+    return __riscv_aes64esm (rs1,rs2);
+}
+
+uint64_t foo8 (uint64_t rs1)
+{
+    return __riscv_sha512sig0 (rs1);
+}
+
+uint64_t foo9 (uint64_t rs1)
+{
+    return __riscv_sha512sig1 (rs1);
+}
+
+uint64_t foo10 (uint64_t rs1)
+{
+    return __riscv_sha512sum0 (rs1);
+}
+
+uint64_t foo11 (uint64_t rs1)
+{
+    return __riscv_sha512sum1 (rs1);
+}
+
+uint32_t foo12 (uint32_t rs1)
+{
+    return __riscv_sha256sig0 (rs1);
+}
+
+uint32_t foo13 (uint32_t rs1)
+{
+    return __riscv_sha256sig1 (rs1);
+}
+
+uint32_t foo14 (uint32_t rs1)
+{
+    return __riscv_sha256sum0 (rs1);
+}
+
+uint32_t foo15 (uint32_t rs1)
+{
+    return __riscv_sha256sum1 (rs1);
+}
+
+uint32_t foo16 (uint32_t rs1)
+{
+    return __riscv_sm3p0 (rs1);
+}
+
+uint32_t foo17 (uint32_t rs1)
+{
+    return __riscv_sm3p1 (rs1);
+}
+
+uint32_t foo18 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sm4ed (rs1,rs2,1);
+}
+
+uint32_t foo19 (uint32_t rs1, uint32_t rs2)
+{
+    return __riscv_sm4ks (rs1,rs2,1);
+}
+
+/* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */
+/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
+/* { dg-final { scan-assembler-times "aes64im" 1 } } */
+/* { dg-final { scan-assembler-times "aes64es\t" 1 } } */
+/* { dg-final { scan-assembler-times "aes64esm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
-- 
2.34.1

[PATCH V3 3/3] RISC-V: Add C intrinsic for Scalar Bitmanip Extension

[Liao Shihua]

This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Changed orcb, clmul, brev8 pattern's mode form X to GPR because orcbsi, clmul_si, 
brev8_si are both included in rv32 and rv64. Test them in scalar_bitmanip_intrinsic-64-emulated.c.

gcc/ChangeLog:

        * config.gcc: Include riscv_bitmanip.h.
        * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
        * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
        * config/riscv/riscv-builtins.cc (AVAIL): New AVAIL.
        (RISCV_BUILTIN_NO_PREFIX): New riscv_builtin_description.
        * config/riscv/riscv-cmo.def (RISCV_BUILTIN): New builtins.
        * config/riscv/riscv-ftypes.def (2): New ftypes.
        * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
        (RISCV_BUILTIN_NO_PREFIX): Ditto.
        * config/riscv/riscv_bitmanip.h: New file.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/scalar_bitmanip_intrinsic-32.c: New test.
        * gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c: New test.
        * gcc.target/riscv/scalar_bitmanip_intrinsic-64.c: New test.

---
 gcc/config.gcc                                |   2 +-
 gcc/config/riscv/bitmanip.md                  |  10 +-
 gcc/config/riscv/crypto.md                    |   4 +-
 gcc/config/riscv/riscv-builtins.cc            |  22 ++
 gcc/config/riscv/riscv-cmo.def                |  12 +-
 gcc/config/riscv/riscv-ftypes.def             |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def      |  22 +-
 gcc/config/riscv/riscv_bitmanip.h             | 297 ++++++++++++++++++
 .../riscv/scalar_bitmanip_intrinsic-32.c      |  96 ++++++
 .../scalar_bitmanip_intrinsic-64-emulated.c   |  32 ++
 .../riscv/scalar_bitmanip_intrinsic-64.c      | 114 +++++++
 11 files changed, 597 insertions(+), 16 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_bitmanip.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f8483d34ee9..5999ef5cbc8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	extra_objs="${extra_objs} thead.o riscv-target-attr.o"
 	d_target_objs="riscv-d.o"
-	extra_headers="riscv_vector.h riscv_crypto.h"
+	extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h"
 	;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 92bcdc30fe4..23a06514732 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -443,8 +443,8 @@
 ;; orc.b (or-combine) is added as an unspec for the benefit of the support
 ;; for optimized string functions (such as strcmp).
 (define_insn "orcb<mode>2"
-  [(set (match_operand:X 0 "register_operand" "=r")
-	(unspec:X [(match_operand:X 1 "register_operand" "r")] UNSPEC_ORC_B))]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+	(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")] UNSPEC_ORC_B))]
   "TARGET_ZBB"
   "orc.b\t%0,%1"
   [(set_attr "type" "bitmanip")])
@@ -852,9 +852,9 @@
 
 ;; ZBKC or ZBC extension
 (define_insn "riscv_clmul_<mode>"
-  [(set (match_operand:X 0 "register_operand" "=r")
-        (unspec:X [(match_operand:X 1 "register_operand" "r")
-                  (match_operand:X 2 "register_operand" "r")]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+        (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
+                  (match_operand:GPR 2 "register_operand" "r")]
                   UNSPEC_CLMUL))]
   "TARGET_ZBKC || TARGET_ZBC"
   "clmul\t%0,%1,%2"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 2b65fadeb15..bf3d1cd9a3c 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -72,8 +72,8 @@
 
 ;; ZBKB extension
 (define_insn "riscv_brev8_<mode>"
-  [(set (match_operand:X 0 "register_operand" "=r")
-        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+        (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")]
                   UNSPEC_BREV8))]
   "TARGET_ZBKB"
   "brev8\t%0,%1"
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 5ee11ebe3bc..fc6ff548b83 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -105,6 +105,7 @@ AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
 AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (crypto_zbkb, TARGET_ZBKB)
 AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
 AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
 AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
@@ -119,10 +120,15 @@ AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
 AVAIL (crypto_zksh, TARGET_ZKSH)
 AVAIL (crypto_zksed, TARGET_ZKSED)
+AVAIL (clmul_zbkc_or_zbc, (TARGET_ZBKC || TARGET_ZBC))
 AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) && !TARGET_64BIT)
 AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
 AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
 AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
+AVAIL (zbb, TARGET_ZBB)
+AVAIL (zbb64, TARGET_ZBB && TARGET_64BIT)
+AVAIL (zbb64_or_zbkb64, (TARGET_ZBKB || TARGET_ZBB) && TARGET_64BIT)
+AVAIL (zbb_or_zbkb, (TARGET_ZBKB || TARGET_ZBB))
 AVAIL (hint_pause, (!0))
 
 // CORE-V AVAIL
@@ -146,6 +152,22 @@ AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
   { CODE_FOR_riscv_ ## INSN, "__builtin_riscv_" NAME,			\
     BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
 
+/* Construct a riscv_builtin_description from the given arguments like RISCV_BUILTIN.
+
+   INSN is the name of the associated instruction pattern, without the
+   leading CODE_FOR_.
+
+   NAME is the name of the function itself, without the leading
+   "__builtin_riscv_".
+
+   BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields.
+
+   AVAIL is the name of the availability predicate, without the leading
+   riscv_builtin_avail_.  */
+#define RISCV_BUILTIN_NO_PREFIX(INSN, NAME, BUILTIN_TYPE,	FUNCTION_TYPE, AVAIL)	\
+  { CODE_FOR_ ## INSN, "__builtin_riscv_" NAME,			\
+    BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
+
 /* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT function
    mapped to instruction CODE_FOR_riscv_<INSN>,  FUNCTION_TYPE and AVAIL
    are as for RISCV_BUILTIN.  */
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index ff713b78e19..78cf1d84070 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -17,11 +17,11 @@ RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV
 RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetchi64),
 
 // zbkc or zbc
-RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
-RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
-RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
-RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
+RISCV_BUILTIN (clmul_si, "clmul_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc_or_zbc),
+RISCV_BUILTIN (clmul_di, "clmul_64", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
+RISCV_BUILTIN (clmulh_si, "clmulh_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
+RISCV_BUILTIN (clmulh_di, "clmulh_64", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
 
 // zbc
-RISCV_BUILTIN (clmulr_si, "clmulr", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmulr_zbc32),
-RISCV_BUILTIN (clmulr_di, "clmulr", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmulr_zbc64),
+RISCV_BUILTIN (clmulr_si, "clmulr_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmulr_zbc32),
+RISCV_BUILTIN (clmulr_di, "clmulr_64", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UDI, clmulr_zbc64),
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 3e7d5c69503..9d02438902c 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -40,9 +40,11 @@ DEF_RISCV_FTYPE (1, (SI, HI))
 DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (USI, UHI, UHI))
 DEF_RISCV_FTYPE (2, (USI, USI, USI))
+DEF_RISCV_FTYPE (2, (USI, USI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UQI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UHI, UHI))
 DEF_RISCV_FTYPE (2, (UDI, USI, USI))
+DEF_RISCV_FTYPE (2, (UDI, UDI, UQI))
 DEF_RISCV_FTYPE (2, (UDI, UDI, USI))
 DEF_RISCV_FTYPE (2, (UDI, UDI, UDI))
 DEF_RISCV_FTYPE (2, (SI, USI, USI))
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
index 3db9ed4a03e..bc2f2466595 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -29,8 +29,8 @@ RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UHI_UHI, cr
 RISCV_BUILTIN (zip, "zip", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, crypto_zbkb32),
 RISCV_BUILTIN (unzip, "unzip", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, crypto_zbkb32),
 
-RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, crypto_zbkb32),
-RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, crypto_zbkb64),
+RISCV_BUILTIN (brev8_si, "brev8_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, crypto_zbkb),
+RISCV_BUILTIN (brev8_di, "brev8_64", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, crypto_zbkb64),
 
 // ZBKX
 RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, crypto_zbkx32),
@@ -78,3 +78,21 @@ RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cry
 // ZKSED
 RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, crypto_zksed),
 RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, crypto_zksed),
+
+
+// ZBB
+
+RISCV_BUILTIN_NO_PREFIX (clzsi2,"clz_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb),
+RISCV_BUILTIN_NO_PREFIX (clzdi2,"clz_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64),
+RISCV_BUILTIN_NO_PREFIX (ctzsi2,"ctz_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb),
+RISCV_BUILTIN_NO_PREFIX (ctzdi2,"ctz_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64),
+RISCV_BUILTIN_NO_PREFIX (popcountsi2,"popcount_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb),
+RISCV_BUILTIN_NO_PREFIX (popcountdi2,"popcount_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64),
+RISCV_BUILTIN_NO_PREFIX (orcbsi2,"orc_b_32", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI,zbb),
+RISCV_BUILTIN_NO_PREFIX (orcbdi2,"orc_b_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI,zbb64),
+
+// ZBKB
+RISCV_BUILTIN_NO_PREFIX (rotrsi3,"ror_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI,zbb_or_zbkb),
+RISCV_BUILTIN_NO_PREFIX (rotlsi3,"rol_32",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI,zbb_or_zbkb),
+RISCV_BUILTIN_NO_PREFIX (rotrdi3,"ror_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UQI,zbb64_or_zbkb64),
+RISCV_BUILTIN_NO_PREFIX (rotldi3,"rol_64",RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI_UQI,zbb64_or_zbkb64),
diff --git a/gcc/config/riscv/riscv_bitmanip.h b/gcc/config/riscv/riscv_bitmanip.h
new file mode 100644
index 00000000000..88275ec98db
--- /dev/null
+++ b/gcc/config/riscv/riscv_bitmanip.h
@@ -0,0 +1,297 @@
+/* RISC-V  Bitmanip Extension intrinsics include file.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef __RISCV_BITMANIP_H
+#define __RISCV_BITMANIP_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__riscv_zbb)
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clz_32 (uint32_t x)
+{
+  return __builtin_riscv_clz_32 (x);
+}
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ctz_32 (uint32_t x)
+{
+  return __builtin_riscv_ctz_32 (x);
+}
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_cpop_32 (uint32_t x)
+{
+  return __builtin_riscv_popcount_32 (x);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_orc_b_32 (uint32_t x)
+{
+  return __builtin_riscv_orc_b_32 (x);
+}
+
+#if __riscv_xlen == 64
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clz_64 (uint64_t x)
+{
+  return __builtin_riscv_clz_64 (x);
+}
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ctz_64 (uint64_t x)
+{
+  return __builtin_riscv_ctz_64 (x);
+}
+
+extern __inline unsigned
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_cpop_64 (uint64_t x)
+{
+  return __builtin_riscv_popcount_64 (x);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_orc_b_64 (uint64_t x)
+{
+  return __builtin_riscv_orc_b_64 (x);
+}
+
+#endif
+
+#endif // __riscv_zbb
+
+#if defined (__riscv_zbb) || defined (__riscv_zbkb)
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ror_32 (uint32_t x, uint32_t shamt)
+{
+    return __builtin_riscv_ror_32 (x,shamt);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rol_32 (uint32_t x, uint32_t shamt)
+{
+    return __builtin_riscv_rol_32 (x,shamt);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rev8_32 (uint32_t x)
+{
+    return __builtin_bswap32 (x);
+}
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ror_64 (uint64_t x, uint32_t shamt)
+{
+    return __builtin_riscv_ror_64 (x,shamt);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rol_64 (uint64_t x, uint32_t shamt)
+{
+    return __builtin_riscv_rol_64 (x,shamt);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rev8_64 (uint64_t x)
+{
+    return __builtin_bswap64 (x);
+}
+
+#endif
+
+#endif // __riscv_zbb || __riscv_zbkb
+
+#if defined (__riscv_zbkb)
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_brev8_32 (uint32_t x)
+{
+    return __builtin_riscv_brev8_32 (x);
+}
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_zip_32 (uint32_t x)
+{
+    return __builtin_riscv_zip (x);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_unzip_32 (uint32_t x)
+{
+    return __builtin_riscv_unzip (x);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_brev8_64 (uint64_t x)
+{
+    return __builtin_riscv_brev8_64 (x);
+}
+
+#endif
+
+#endif // __riscv_zbkb
+
+#if defined (__riscv_zbc) || defined (__riscv_zbkc)
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmul_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_clmul_32 (rs1,rs2);
+}
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulh_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_clmulh_32 (rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmul_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_clmul_64 (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulh_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_clmulh_64 (rs1,rs2);
+}
+
+#endif
+
+#endif // __riscv_zbc || __riscv_zbkc
+
+#if defined (__riscv_zbc)
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulr_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_clmulr_32 (rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulr_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_clmulr_64 (rs1,rs2);
+}
+
+#endif
+
+#endif // __riscv_zbc
+
+#if defined (__riscv_zbkx)
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm4_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_xperm4 (rs1,rs2);
+}
+
+extern __inline uint32_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm8_32 (uint32_t rs1, uint32_t rs2)
+{
+    return __builtin_riscv_xperm8 (rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm4_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_xperm4 (rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm8_64 (uint64_t rs1, uint64_t rs2)
+{
+    return __builtin_riscv_xperm8 (rs1,rs2);
+}
+
+#endif
+
+#endif // __riscv_zbkx
+
+#if defined (__cplusplus)
+}
+#endif // __cplusplus
+#endif // __RISCV_BITMANIP_H
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
new file mode 100644
index 00000000000..49f9bcc5aeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb_zbc_zbkb_zbkc_zbkx -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_bitmanip.h"
+
+unsigned foo1 (uint32_t x)
+{
+    return __riscv_clz_32 (x);
+}
+
+unsigned foo2 (uint32_t x)
+{
+    return __riscv_ctz_32 (x);
+}
+
+unsigned foo3 (uint32_t x)
+{
+    return __riscv_cpop_32 (x);
+}
+
+uint32_t foo4 (uint32_t x)
+{
+    return __riscv_orc_b_32 (x);
+}
+
+uint32_t foo5 (uint32_t x, uint32_t shamt)
+{
+    return __riscv_ror_32 (x,shamt);
+}
+
+uint32_t foo6 (uint32_t x, uint32_t shamt)
+{
+    return __riscv_rol_32 (x,shamt);
+}
+
+uint32_t foo7 (uint32_t x)
+{
+    return __riscv_rev8_32 (x);
+}
+
+uint32_t foo8 (uint32_t x)
+{
+    return __riscv_brev8_32 (x);
+}
+
+uint32_t foo9 (uint32_t x)
+{
+    return __riscv_zip_32 (x);
+}
+
+uint32_t foo10 (uint32_t x)
+{
+    return __riscv_unzip_32 (x);
+}
+
+uint32_t foo11 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_clmul_32 (rs1,rs2);
+}
+
+uint32_t foo12 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_clmulh_32 (rs1,rs2);
+}
+
+uint32_t foo13 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_clmulr_32 (rs1,rs2);
+}
+
+uint32_t foo14 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_xperm4_32 (rs1,rs2);
+}
+
+uint32_t foo15 (uint32_t rs1,uint32_t rs2)
+{
+    return __riscv_xperm8_32 (rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "clz" 1 } } */
+/* { dg-final { scan-assembler-times "ctz" 1 } } */
+/* { dg-final { scan-assembler-times "cpop" 1 } } */
+/* { dg-final { scan-assembler-times "orc.b" 1 } } */
+/* { dg-final { scan-assembler-times "ror" 1 } } */
+/* { dg-final { scan-assembler-times "rol" 1 } } */
+/* { dg-final { scan-assembler-times {\mrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mzip} 1 } } */
+/* { dg-final { scan-assembler-times {\munzip} 1 } } */
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
+/* { dg-final { scan-assembler-times "clmulr" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
new file mode 100644
index 00000000000..f417422f3a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb_zbc_zbkb_zbkc -mabi=lp64d " } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-O0" "-flto"} } */
+
+#include "riscv_bitmanip.h"
+
+uint32_t foo (uint32_t rs1)
+{
+    return __riscv_rev8_32 (rs1);
+}
+
+int32_t foo2(uint32_t rs1)
+{
+    return __riscv_brev8_32 (rs1);
+}
+
+uint32_t foo3 (uint32_t rs1)
+{
+    return __riscv_orc_b_32 (rs1);
+
+}
+
+uint32_t foo4 (uint32_t rs1)
+{
+    return __riscv_clmul_32 (rs1,rs1);
+}
+
+/* { dg-final { scan-assembler-times {\mrev8} 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
+/* { dg-final { scan-assembler-times "clmul" 1 } } */
+/* { dg-final { scan-assembler-times "orc.b" 1 } } */
+/* { dg-final { scan-assembler-times "sext.w" 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
new file mode 100644
index 00000000000..f4d255a61c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
@@ -0,0 +1,114 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb_zbc_zbkb_zbkc_zbkx -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_bitmanip.h"
+
+unsigned foo1 (uint32_t x)
+{
+    return __riscv_clz_32 (x);
+}
+
+unsigned foo2 (uint32_t x)
+{
+    return __riscv_ctz_32 (x);
+}
+
+unsigned foo3 (uint32_t x)
+{
+    return __riscv_cpop_32 (x);
+}
+
+uint32_t foo4 (uint32_t x, uint8_t shamt)
+{
+    return __riscv_ror_32 (x,shamt);
+}
+
+uint32_t foo5 (uint32_t x, uint8_t shamt)
+{
+    return __riscv_rol_32 (x,shamt);
+}
+
+unsigned foo6 (uint64_t x)
+{
+    return __riscv_clz_64 (x);
+}
+
+unsigned foo7 (uint64_t x)
+{
+    return __riscv_ctz_64 (x);
+}
+
+unsigned foo8 (uint64_t x)
+{
+    return __riscv_cpop_64 (x);
+}
+
+uint64_t foo9 (uint64_t x)
+{
+    return __riscv_orc_b_64 (x);
+}
+
+uint64_t foo10 (uint64_t rs1, uint8_t rs2)
+{
+    return __riscv_ror_64 (rs1,rs2);
+}
+
+uint64_t foo11 (uint64_t rs1, uint8_t rs2)
+{
+    return __riscv_rol_64 (rs1,rs2);
+}
+
+uint64_t foo12 (uint64_t x)
+{
+    return __riscv_rev8_64 (x);
+}
+
+uint64_t foo13 (uint64_t x)
+{
+    return __riscv_brev8_64 (x);
+}
+
+uint64_t foo14 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_clmul_64 (rs1,rs2);
+}
+
+uint64_t foo15 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_clmulh_64 (rs1,rs2);
+}
+
+uint64_t foo16 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_clmulr_64 (rs1,rs2);
+}
+
+uint64_t foo17 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_xperm4_64 (rs1,rs2);
+}
+
+uint64_t foo18 (uint64_t rs1,uint64_t rs2)
+{
+    return __riscv_xperm8_64 (rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "clzw" 1 } } */
+/* { dg-final { scan-assembler-times "ctzw" 1 } } */
+/* { dg-final { scan-assembler-times "cpopw" 1 } } */
+/* { dg-final { scan-assembler-times "rorw" 1 } } */
+/* { dg-final { scan-assembler-times "rolw" 1 } } */
+/* { dg-final { scan-assembler-times "clz\t" 1 } } */
+/* { dg-final { scan-assembler-times "ctz\t" 1 } } */
+/* { dg-final { scan-assembler-times "cpop\t" 1 } } */
+/* { dg-final { scan-assembler-times "orc.b" 1 } } */
+/* { dg-final { scan-assembler-times "ror\t" 1 } } */
+/* { dg-final { scan-assembler-times "rol\t" 1 } } */
+/* { dg-final { scan-assembler-times {\mrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
+/* { dg-final { scan-assembler-times "clmulr" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
-- 
2.34.1

Re: [PATCH V3 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

[Christoph Müllner]

The tests still fail.

gcc: Unexpected fails for rv64gc lp64d medlow
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-32.c   -O0  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-32.c   -O1  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-32.c   -O2  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-32.c   -Os  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-32.c  -Oz  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-32.c   -O0  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-32.c   -O1  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-32.c   -O2  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-32.c   -Os  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-32.c  -Oz  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c   -O0  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c   -O1  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c   -O2  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c   -Os  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c  -Oz  (test for
excess errors)

Note, this is not only a rv32/rv64 issue, because also -64.c tests fail.

gcc: Unexpected fails for rv32gc ilp32d medlow
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c   -O1
(test for excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c   -O2
(test for excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c   -Os
(test for excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c  -Oz
(test for excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64.c   -O0  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64.c   -O1  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64.c   -O2  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64.c   -Os  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_bitmanip_intrinsic-64.c  -Oz  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c   -O0  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c   -O1  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c   -O2  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c   -Os  (test for
excess errors)
FAIL: gcc.target/riscv/scalar_crypto_intrinsic-64.c  -Oz  (test for
excess errors)




On Tue, Dec 26, 2023 at 6:47 AM Liao Shihua <shihua@iscas.ac.cn> wrote:
>
> Update v2 -> v3:
>   1. Change pattern mode form X to GPR in orcb, clmul, and brev8.
>   2. Add emulated testsuite.
>   3. Removed duplicate testsuite between built-in and intrinsic.
>   4. Typo fix.
>
> Update v1 -> v2:
>   1. Rename *_intrinsic-* to *_intrinsic-XLEN.
>   2. Typo fix.
>   3. Intrinsics with immediate arguments will use marcos at O0 .
>
> It's a little patch add just provides a mapping from the RV intrinsics to the builtin
> names within GCC.
>
> Liao Shihua (3):
>   RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function
>     testsuites
>   RISC-V: Add C intrinsic for Scalar Crypto Extension
>   RISC-V: Add C intrinsic for Scalar Bitmanip Extension
>
>  gcc/config.gcc                                |   2 +-
>  gcc/config/riscv/bitmanip.md                  |  10 +-
>  gcc/config/riscv/crypto.md                    |   4 +-
>  gcc/config/riscv/riscv-builtins.cc            |  22 ++
>  gcc/config/riscv/riscv-cmo.def                |  12 +-
>  gcc/config/riscv/riscv-ftypes.def             |   2 +
>  gcc/config/riscv/riscv-scalar-crypto.def      |  22 +-
>  gcc/config/riscv/riscv_bitmanip.h             | 297 +++++++++++++++++
>  gcc/config/riscv/riscv_crypto.h               | 309 ++++++++++++++++++
>  .../riscv/scalar_bitmanip_intrinsic-32.c      |  96 ++++++
>  .../scalar_bitmanip_intrinsic-64-emulated.c   |  32 ++
>  .../riscv/scalar_bitmanip_intrinsic-64.c      | 114 +++++++
>  .../riscv/scalar_crypto_intrinsic-32.c        | 114 +++++++
>  .../riscv/scalar_crypto_intrinsic-64.c        | 122 +++++++
>  gcc/testsuite/gcc.target/riscv/zbbw.c         |  26 --
>  gcc/testsuite/gcc.target/riscv/zbc32.c        |  23 --
>  gcc/testsuite/gcc.target/riscv/zbc64.c        |  23 --
>  gcc/testsuite/gcc.target/riscv/zbkb32.c       |  18 -
>  gcc/testsuite/gcc.target/riscv/zbkb64.c       |   5 -
>  gcc/testsuite/gcc.target/riscv/zbkc32.c       |  17 -
>  gcc/testsuite/gcc.target/riscv/zbkc64.c       |  17 -
>  gcc/testsuite/gcc.target/riscv/zbkx32.c       |  18 -
>  gcc/testsuite/gcc.target/riscv/zbkx64.c       |  18 -
>  gcc/testsuite/gcc.target/riscv/zknd32-2.c     |  28 --
>  gcc/testsuite/gcc.target/riscv/zknd64-2.c     |  42 ---
>  gcc/testsuite/gcc.target/riscv/zkne32-2.c     |  28 --
>  gcc/testsuite/gcc.target/riscv/zkne64-2.c     |  34 --
>  .../gcc.target/riscv/zknh-sha256-32.c         |  10 -
>  .../gcc.target/riscv/zknh-sha256-64.c         |  28 --
>  .../gcc.target/riscv/zknh-sha512-32.c         |  42 ---
>  .../gcc.target/riscv/zknh-sha512-64.c         |  31 --
>  gcc/testsuite/gcc.target/riscv/zksed32-2.c    |  29 --
>  gcc/testsuite/gcc.target/riscv/zksed64-2.c    |  29 --
>  gcc/testsuite/gcc.target/riscv/zksh32.c       |  19 --
>  gcc/testsuite/gcc.target/riscv/zksh64.c       |  19 --
>  35 files changed, 1142 insertions(+), 520 deletions(-)
>  create mode 100644 gcc/config/riscv/riscv_bitmanip.h
>  create mode 100644 gcc/config/riscv/riscv_crypto.h
>  create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc32.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc64.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd32-2.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zknd64-2.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne32-2.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zkne64-2.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed32-2.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zksed64-2.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c
>
> --
> 2.34.1
>