[committed] i386: Remove *stack_protect_set_4s_<mode>_di alternative that will never match

[committed] i386: Remove *stack_protect_set_4s_<mode>_di alternative that will never match

[Uros Bizjak]

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The relevant peephole2 will never generate alternative (=m,=&a,0,m) because
operand 1 is not dead before the peephole2 pattern.

gcc/ChangeLog:

* config/i386/i386.md (*stack_protect_set_4s_<mode>_di):
Remove alternative 0.

Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}.

Uros.

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diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 01fc6ecc351..ffd9f2d0381 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -24481,19 +24481,16 @@ (define_insn "*stack_protect_set_4z_<mode>_di"
    (set_attr "length" "24")])
 
 (define_insn "*stack_protect_set_4s_<mode>_di"
-  [(set (match_operand:PTR 0 "memory_operand" "=m,m")
-	(unspec:PTR [(match_operand:PTR 3 "memory_operand" "m,m")]
+  [(set (match_operand:PTR 0 "memory_operand" "=m")
+	(unspec:PTR [(match_operand:PTR 3 "memory_operand" "m")]
 		    UNSPEC_SP_SET))
-   (set (match_operand:DI 1 "register_operand" "=&a,&r")
-	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "0,rm")))]
+   (set (match_operand:DI 1 "register_operand" "=&r")
+	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))]
   "TARGET_64BIT && reload_completed"
 {
   output_asm_insn ("mov{<imodesuffix>}\t{%3, %<k>1|%<k>1, %3}", operands);
   output_asm_insn ("mov{<imodesuffix>}\t{%<k>1, %0|%0, %<k>1}", operands);
-  if (which_alternative)
-    return "movs{lq|x}\t{%2, %1|%1, %2}";
-  else
-    return "{cltq|cdqe}";
+  return "movs{lq|x}\t{%2, %1|%1, %2}";
 }
   [(set_attr "type" "multi")
    (set_attr "length" "24")])