* [PATCH] i386: Fix up *<dwi>3_doubleword_mask [PR105911
@ 2022-06-10 19:27 Jakub Jelinek
2022-06-12 17:30 ` Uros Bizjak
0 siblings, 1 reply; 2+ messages in thread
From: Jakub Jelinek @ 2022-06-10 19:27 UTC (permalink / raw)
To: Uros Bizjak; +Cc: gcc-patches
Hi!
Another regression caused by my recent patch.
This time because define_insn_and_split only requires that the
constant mask is const_int_operand. When it was only SImode,
that wasn't a problem, HImode neither, but for DImode if we need
to and the shift count we might run into a problem that it isn't
a representable signed 32-bit immediate.
But, we don't really care about the upper bits of the mask, so
we can just mask the CONST_INT with the mode mask.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2022-06-10 Jakub Jelinek <jakub@redhat.com>
PR target/105911
* config/i386/i386.md ((*ashl<dwi>3_doubleword_mask,
*<insn><dwi>3_doubleword_mask): Use operands[3] masked with
(<MODE_SIZE> * BITS_PER_UNIT) - 1 as AND operand instead of
operands[3] unmodified.
* gcc.dg/pr105911.c: New test.
--- gcc/config/i386/i386.md.jj 2022-06-08 08:21:26.000000000 +0200
+++ gcc/config/i386/i386.md 2022-06-10 11:37:21.931171567 +0200
@@ -11937,7 +11937,8 @@ (define_insn_and_split "*ashl<dwi>3_doub
rtx xops[3];
xops[0] = gen_reg_rtx (GET_MODE (operands[2]));
xops[1] = operands[2];
- xops[2] = operands[3];
+ xops[2] = GEN_INT (INTVAL (operands[3])
+ & ((<MODE_SIZE> * BITS_PER_UNIT) - 1));
ix86_expand_binary_operator (AND, GET_MODE (operands[2]), xops);
operands[2] = xops[0];
}
@@ -12905,7 +12906,8 @@ (define_insn_and_split "*<insn><dwi>3_do
rtx xops[3];
xops[0] = gen_reg_rtx (GET_MODE (operands[2]));
xops[1] = operands[2];
- xops[2] = operands[3];
+ xops[2] = GEN_INT (INTVAL (operands[3])
+ & ((<MODE_SIZE> * BITS_PER_UNIT) - 1));
ix86_expand_binary_operator (AND, GET_MODE (operands[2]), xops);
operands[2] = xops[0];
}
--- gcc/testsuite/gcc.dg/pr105911.c.jj 2022-06-10 11:45:38.314044503 +0200
+++ gcc/testsuite/gcc.dg/pr105911.c 2022-06-10 11:45:18.068253633 +0200
@@ -0,0 +1,16 @@
+/* PR target/105911 */
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2" } */
+
+__int128 v, x;
+unsigned __int128 w;
+
+void bar (__int128, __int128);
+
+void
+foo (void)
+{
+ bar (v /= v, v >> (v &= 0x100000001));
+ bar (w /= w, w >> (w &= 0x300000003));
+ bar (x /= x, x << (x &= 0x700000007));
+}
Jakub
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] i386: Fix up *<dwi>3_doubleword_mask [PR105911
2022-06-10 19:27 [PATCH] i386: Fix up *<dwi>3_doubleword_mask [PR105911 Jakub Jelinek
@ 2022-06-12 17:30 ` Uros Bizjak
0 siblings, 0 replies; 2+ messages in thread
From: Uros Bizjak @ 2022-06-12 17:30 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: gcc-patches
On Fri, Jun 10, 2022 at 9:27 PM Jakub Jelinek <jakub@redhat.com> wrote:
>
> Hi!
>
> Another regression caused by my recent patch.
>
> This time because define_insn_and_split only requires that the
> constant mask is const_int_operand. When it was only SImode,
> that wasn't a problem, HImode neither, but for DImode if we need
> to and the shift count we might run into a problem that it isn't
> a representable signed 32-bit immediate.
>
> But, we don't really care about the upper bits of the mask, so
> we can just mask the CONST_INT with the mode mask.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2022-06-10 Jakub Jelinek <jakub@redhat.com>
>
> PR target/105911
> * config/i386/i386.md ((*ashl<dwi>3_doubleword_mask,
> *<insn><dwi>3_doubleword_mask): Use operands[3] masked with
> (<MODE_SIZE> * BITS_PER_UNIT) - 1 as AND operand instead of
> operands[3] unmodified.
>
> * gcc.dg/pr105911.c: New test.
OK.
Thanks,
Uros.
>
> --- gcc/config/i386/i386.md.jj 2022-06-08 08:21:26.000000000 +0200
> +++ gcc/config/i386/i386.md 2022-06-10 11:37:21.931171567 +0200
> @@ -11937,7 +11937,8 @@ (define_insn_and_split "*ashl<dwi>3_doub
> rtx xops[3];
> xops[0] = gen_reg_rtx (GET_MODE (operands[2]));
> xops[1] = operands[2];
> - xops[2] = operands[3];
> + xops[2] = GEN_INT (INTVAL (operands[3])
> + & ((<MODE_SIZE> * BITS_PER_UNIT) - 1));
> ix86_expand_binary_operator (AND, GET_MODE (operands[2]), xops);
> operands[2] = xops[0];
> }
> @@ -12905,7 +12906,8 @@ (define_insn_and_split "*<insn><dwi>3_do
> rtx xops[3];
> xops[0] = gen_reg_rtx (GET_MODE (operands[2]));
> xops[1] = operands[2];
> - xops[2] = operands[3];
> + xops[2] = GEN_INT (INTVAL (operands[3])
> + & ((<MODE_SIZE> * BITS_PER_UNIT) - 1));
> ix86_expand_binary_operator (AND, GET_MODE (operands[2]), xops);
> operands[2] = xops[0];
> }
> --- gcc/testsuite/gcc.dg/pr105911.c.jj 2022-06-10 11:45:38.314044503 +0200
> +++ gcc/testsuite/gcc.dg/pr105911.c 2022-06-10 11:45:18.068253633 +0200
> @@ -0,0 +1,16 @@
> +/* PR target/105911 */
> +/* { dg-do compile { target int128 } } */
> +/* { dg-options "-O2" } */
> +
> +__int128 v, x;
> +unsigned __int128 w;
> +
> +void bar (__int128, __int128);
> +
> +void
> +foo (void)
> +{
> + bar (v /= v, v >> (v &= 0x100000001));
> + bar (w /= w, w >> (w &= 0x300000003));
> + bar (x /= x, x << (x &= 0x700000007));
> +}
>
> Jakub
>
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