[PATCH] RISC-V regression test: Fix FAIL bb-slp-cond-1.c for RVV

[PATCH] RISC-V regression test: Fix FAIL bb-slp-cond-1.c for RVV

[Juzhe-Zhong]

Previously, in this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635392.html
I use vect64 && vect128 to represent both RVV and AMDGCN. However, it caused additional FAIL on ARM SVE.
I don't know why ARM SVE vect64 is set as true since their AdvSIMD is 128bit vector and they don't use 64bit vector.

So, here we leverage current AMDGCN solution, just add RISCV like AMDGCN.

gcc/testsuite/ChangeLog:

	* gcc.dg/vect/bb-slp-cond-1.c: Add riscv.

---
 gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
index c8024429e9c..4089eb51b2e 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
@@ -47,6 +47,6 @@ int main ()
 }
 
 /* { dg-final { scan-tree-dump {(no need for alias check [^\n]* when VF is 1|no alias between [^\n]* when [^\n]* is outside \(-16, 16\))} "vect" { target vect_element_align } } } */
-/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target { vect_element_align && { ! amdgcn-*-* } } } } } */
-/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target amdgcn-*-* } } } */
+/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target { vect_element_align && { ! { amdgcn-*-* riscv*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target { amdgcn-*-* riscv*-*-* } } } } */
 
-- 
2.36.3

Re: [PATCH] RISC-V regression test: Fix FAIL bb-slp-cond-1.c for RVV

[Richard Biener]

On Tue, Nov 7, 2023 at 9:07 AM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> Previously, in this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635392.html
> I use vect64 && vect128 to represent both RVV and AMDGCN. However, it caused additional FAIL on ARM SVE.
> I don't know why ARM SVE vect64 is set as true since their AdvSIMD is 128bit vector and they don't use 64bit vector.
>
> So, here we leverage current AMDGCN solution, just add RISCV like AMDGCN.

OK.

> gcc/testsuite/ChangeLog:
>
>         * gcc.dg/vect/bb-slp-cond-1.c: Add riscv.
>
> ---
>  gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
> index c8024429e9c..4089eb51b2e 100644
> --- a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
> +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c
> @@ -47,6 +47,6 @@ int main ()
>  }
>
>  /* { dg-final { scan-tree-dump {(no need for alias check [^\n]* when VF is 1|no alias between [^\n]* when [^\n]* is outside \(-16, 16\))} "vect" { target vect_element_align } } } */
> -/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target { vect_element_align && { ! amdgcn-*-* } } } } } */
> -/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target amdgcn-*-* } } } */
> +/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target { vect_element_align && { ! { amdgcn-*-* riscv*-*-* } } } } } } */
> +/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target { amdgcn-*-* riscv*-*-* } } } } */
>
> --
> 2.36.3
>