[AArch64] [BE] [2/2] Make large opaque integer modes endianness-safe.

[AArch64] [BE] [2/2] Make large opaque integer modes endianness-safe.

[David Sherwood]

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Hi,

This is the second patch of the work to fix:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59810

and removes the CANNOT_CHANGE_MODE_CLASS macro, which now permits subregs of
vector registers to work correctly on aarch64_be.

NOTE: This patch depends upon the following:
[AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe.
[AArch64] [BE] Fix vector load/stores to not use ld1/st1

Thanks,
David.

ChangeLog:

    gcc/:
    2014-13-10  David Sherwood  <david.sherwood@arm.com>

        * config/aarch64/aarch64.h (CLEAR_INSN_CACHE): Removed.
        * config/aarch64/aarch64.c (aarch64_cannot_change_mode_class): Removed.
        * config/aarch64/aarch64-protos.h (aarch64_cannot_change_mode_class):
        Removed.

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diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 7710f1f1d5db7903819732bd241fb9fc9b02e9e3..d1568914e07e20dadb6cf0b7fbb1d4b31cbd23bf 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -175,9 +175,6 @@ struct tune_params
 HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
 int aarch64_get_condition_code (rtx);
 bool aarch64_bitmask_imm (HOST_WIDE_INT val, enum machine_mode);
-bool aarch64_cannot_change_mode_class (enum machine_mode,
-				       enum machine_mode,
-				       enum reg_class);
 enum aarch64_symbol_type
 aarch64_classify_symbolic_expression (rtx, enum aarch64_symbol_context);
 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index db950da8f5ec7f8447943533966fd90eeb133276..28c97859aa093de605b156e01d313ea1c2c4e499 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -843,9 +843,6 @@ do {									     \
   extern void  __aarch64_sync_cache_range (void *, void *);	\
   __aarch64_sync_cache_range (beg, end)
 
-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)	\
-  aarch64_cannot_change_mode_class (FROM, TO, CLASS)
-
 #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD
 
 /* Choose appropriate mode for caller saves, so we do the minimum
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 9d050584e145b6e488c5df7ef4a6c71f8ef9db32..42d91cf7306b31e10f10d3682a4cd1e86d3771fb 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -9560,54 +9560,6 @@ aarch64_vectorize_vec_perm_const_ok (enum machine_mode vmode,
   return ret;
 }
 
-/* Implement target hook CANNOT_CHANGE_MODE_CLASS.  */
-bool
-aarch64_cannot_change_mode_class (enum machine_mode from,
-				  enum machine_mode to,
-				  enum reg_class rclass)
-{
-  /* Full-reg subregs are allowed on general regs or any class if they are
-     the same size.  */
-  if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to)
-      || !reg_classes_intersect_p (FP_REGS, rclass))
-    return false;
-
-  /* Limited combinations of subregs are safe on FPREGs.  Particularly,
-     1. Vector Mode to Scalar mode where 1 unit of the vector is accessed.
-     2. Scalar to Scalar for integer modes or same size float modes.
-     3. Vector to Vector modes.
-     4. On little-endian only, Vector-Structure to Vector modes.  */
-  if (GET_MODE_SIZE (from) > GET_MODE_SIZE (to))
-    {
-      if (aarch64_vector_mode_supported_p (from)
-	  && GET_MODE_SIZE (GET_MODE_INNER (from)) == GET_MODE_SIZE (to))
-	return false;
-
-      if (GET_MODE_NUNITS (from) == 1
-	  && GET_MODE_NUNITS (to) == 1
-	  && (GET_MODE_CLASS (from) == MODE_INT
-	      || from == to))
-	return false;
-
-      if (aarch64_vector_mode_supported_p (from)
-	  && aarch64_vector_mode_supported_p (to))
-	return false;
-
-      /* Within an vector structure straddling multiple vector registers
-	 we are in a mixed-endian representation.  As such, we can't
-	 easily change modes for BYTES_BIG_ENDIAN.  Otherwise, we can
-	 switch between vectors and vector structures cheaply.  */
-      if (!BYTES_BIG_ENDIAN)
-	if ((aarch64_vector_mode_supported_p (from)
-	      && aarch64_vect_struct_mode_p (to))
-	    || (aarch64_vector_mode_supported_p (to)
-	      && aarch64_vect_struct_mode_p (from)))
-	  return false;
-    }
-
-  return true;
-}
-
 rtx
 aarch64_reverse_mask (enum machine_mode mode)
 {

Re: [AArch64] [BE] [2/2] Make large opaque integer modes endianness-safe.

[Marcus Shawcroft]

On 13 October 2014 11:01, David Sherwood <david.sherwood@arm.com> wrote:
> Hi,
>
> This is the second patch of the work to fix:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59810
>
> and removes the CANNOT_CHANGE_MODE_CLASS macro, which now permits subregs of
> vector registers to work correctly on aarch64_be.
>
> NOTE: This patch depends upon the following:
> [AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe.
> [AArch64] [BE] Fix vector load/stores to not use ld1/st1
>
> Thanks,
> David.
>
> ChangeLog:
>
>     gcc/:
>     2014-13-10  David Sherwood  <david.sherwood@arm.com>
>
>         * config/aarch64/aarch64.h (CLEAR_INSN_CACHE): Removed.

CANNOT_CHANGE_MODE_CLASS rather than CLEAR_INSN_CACHE.


>         * config/aarch64/aarch64.c (aarch64_cannot_change_mode_class): Removed.
>         * config/aarch64/aarch64-protos.h (aarch64_cannot_change_mode_class):
>         Removed.

The first line of the ChangeLog entry should also reference the PR
number it resolves.

OK with corrected ChangeLog entry.  Thanks /Marcus

RE: [AArch64] [BE] [2/2] Make large opaque integer modes endianness-safe.

[David Sherwood]

Hi,

Sorry to bother you again, but if someone has time could they take
a look at this change please?

Thanks!
David.

-----Original Message-----
From: David Sherwood [mailto:david.sherwood@arm.com] 
Sent: 13 October 2014 11:02
To: gcc-patches@gcc.gnu.org
Subject: [AArch64] [BE] [2/2] Make large opaque integer modes endianness-safe.

Hi,

This is the second patch of the work to fix:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59810

and removes the CANNOT_CHANGE_MODE_CLASS macro, which now permits subregs of
vector registers to work correctly on aarch64_be.

NOTE: This patch depends upon the following:
[AArch64] [BE] [1/2] Make large opaque integer modes endianness-safe.
[AArch64] [BE] Fix vector load/stores to not use ld1/st1

Thanks,
David.

ChangeLog:

    gcc/:
    2014-13-10  David Sherwood  <david.sherwood@arm.com>

        * config/aarch64/aarch64.h (CLEAR_INSN_CACHE): Removed.
        * config/aarch64/aarch64.c (aarch64_cannot_change_mode_class): Removed.
        * config/aarch64/aarch64-protos.h (aarch64_cannot_change_mode_class):
        Removed.