From: Jim Wilson <jimw@sifive.com>
To: Kito Cheng <kito.cheng@gmail.com>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>,
Kito Cheng <kito.cheng@sifive.com>,
Andrew Waterman <aswaterman@gmail.com>,
GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] RISC-V: Zihintpause: add __builtin_riscv_pause
Date: Thu, 18 Feb 2021 12:21:06 -0800 [thread overview]
Message-ID: <CAFyWVaZAULetVHuSwkrqwCLhbuo13fzbzUqft8P4d7fsVmvTsA@mail.gmail.com> (raw)
In-Reply-To: <CA+yXCZDFve5xgaVPZJzv9P6+8YPwbx=nwtT2gWvH31KoC-8OjA@mail.gmail.com>
On Thu, Jan 7, 2021 at 12:50 AM Kito Cheng <kito.cheng@gmail.com> wrote:
> My point is tracking info and consistent behavior/scheme with other
> extensions, so personally I strongly prefer it should be guarded with
> -march.
>
It is a hint. We should allow it even if the architecture extension is not
enabled.
For comparison, I suggest you look at the aarch64 port. They have 3 kinds
of hints: branch protection (bti), pointer authentication, and speculation
control. They deliberately allow you to emit the instructions even if the
hardware doesn't support the feature because they are hints, and execute as
nops if the hardware support is missing. The rationale is that the code
will work with or without the hardware support, but will work better with
the hardware support, so it is best to always allow it. We should do the
same with RISC-V hints.
I agree that we need to include LLVM folks in the discussion to make sure
that GCC and LLVM handle this the same way.
Jim
next prev parent reply other threads:[~2021-02-18 20:21 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-06 17:33 Philipp Tomsich
2021-01-07 3:35 ` Kito Cheng
2021-01-07 3:50 ` Andrew Waterman
2021-01-07 5:41 ` Kito Cheng
2021-01-07 6:53 ` Philipp Tomsich
2021-01-07 8:49 ` Kito Cheng
2021-02-18 20:21 ` Jim Wilson [this message]
2022-11-13 20:41 Philipp Tomsich
2022-11-15 16:40 ` Jeff Law
2022-11-15 22:12 ` Philipp Tomsich
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