Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR

[Kito Cheng <kito.cheng@sifive.com>]

> Could you try something like this? that should be more generic:
>
> (define_split
>  [(set (match_operand:VB 0 "register_operand")
>        (if_then_else:VB
>          (unspec:VB
>            [(match_operand:VB 1 "vector_all_trues_mask_operand")
>             (match_operand 4 "vector_length_operand")
>             (match_operand 5 "const_int_operand")
>             (match_operand 6 "const_int_operand")
>             (reg:SI VL_REGNUM)
>             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>          (match_operand:VB 3 "vector_move_operand")
>          (match_operand:VB 2 "vector_undef_operand")))]
>  "TARGET_VECTOR && reload_completed"

Remove the reload_completed should work well, but you might need more
test, I didn't run full test on this change :P

>  [(const_int 0)]
>  {
>    emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX (<MODE>mode),
>                             RVV_VUNDEF (<MODE>mode), CONST0_RTX (<MODE>mode),
>                             operands[4], operands[5]));
>    DONE;
>  }
> )