From: Hans Boehm <hboehm@google.com>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: jeffreyalaw@gmail.com, "Patrick O'Neill" <patrick@rivosinc.com>,
gcc-patches@gcc.gnu.org, gnu-toolchain@rivosinc.com,
Vineet Gupta <vineetg@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
kito.cheng@sifive.com, Daniel Lustig <dlustig@nvidia.com>,
cmuellner@gcc.gnu.org, Andrea Parri <andrea@rivosinc.com>
Subject: Re: [PATCH v5 06/11] RISC-V: Strengthen atomic stores
Date: Fri, 28 Apr 2023 15:21:46 -0700 [thread overview]
Message-ID: <CAMOCf+g42gZ2wdB8D4mjeUU+aLxWRJvZbvWdND9HXYA-y7FY7g@mail.gmail.com> (raw)
In-Reply-To: <CAMOCf+iF_JFx8+Gi1EKrQ6H2e64sNfm+YWYGYp6HQjBdmDMbGg@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2200 bytes --]
The RISC-V psABI pull request is at
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378 . Pointers to
Paul Kirth's corresponding LLVM patches are also there.
On Fri, Apr 28, 2023 at 2:42 PM Hans Boehm <hboehm@google.com> wrote:
> The concern with making the new behavior non-default is of course that the
> generated code will eventually end up on an A.7-capable platform.
>
> An A.6-classic option for compiling code that will never run on a newer
> machine seems OK. But I'm not sure that seq_cst stores are dynamically
> frequent enough in C++ code for this to be worth the trouble. Unlike loads,
> they are also costly on x86, programmers may also have been somewhat
> trained to avoid them where possible. (And probably where not possible, too
> :-( )
>
> Hans
>
> On Fri, Apr 28, 2023 at 10:43 AM Palmer Dabbelt <palmer@rivosinc.com>
> wrote:
>
>> On Fri, 28 Apr 2023 10:40:15 PDT (-0700), jeffreyalaw@gmail.com wrote:
>> >
>> >
>> > On 4/27/23 10:22, Patrick O'Neill wrote:
>> >> This change makes atomic stores strictly stronger than table A.6 of the
>> >> ISA manual. This mapping makes the overall patchset compatible with
>> >> table A.7 as well.
>> >>
>> >> 2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
>> >>
>> >> PR 89835
>> > Should be "PR target/89835"
>> >
>> >>
>> >> gcc/ChangeLog:
>> >>
>> >> * config/riscv/sync.md:
>> > Needs some text here :-)
>> >
>> >
>> > I'm not objecting to this patch, but I think we've got an option
>> > question about whether or not this approach is too expensive for
>> > existing or soon arriving implementations.
>> >
>> > If the decision on that topic is to just pay the cost, then this patch
>> > is fine. If we decide to make compatibility optional to avoid the
>> > additional cost, then this will need suitable adjustments.
>>
>> IMO the only hardware that's going to be here by gcc-14 and to have
>> enough concurrency for these to matter is the Ventana stuff. I think
>> you're the only one who can figure out if these are slow, at least until
>> that stuff is availiable outside the lab.
>>
>> So are they too slow for you?
>>
>> >
>> > Jeff
>>
>
next prev parent reply other threads:[~2023-04-28 22:21 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220407182918.294892-1-patrick@rivosinc.com>
2023-04-05 21:01 ` [PATCH v2 0/8] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 1/8] RISCV: Eliminate SYNC memory models Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 2/8] RISCV: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 3/8] RISCV: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 4/8] RISCV: Add AMO release bits Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 5/8] RISCV: Eliminate AMO op fences Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 6/8] RISCV: Weaken compare_exchange LR/SC pairs Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 7/8] RISCV: Weaken atomic stores Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 8/8] RISCV: Weaken mem_thread_fence Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 00/10] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 01/10] RISCV: Eliminate SYNC memory models Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 03/10] RISCV: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 04/10] RISCV: Add AMO release bits Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 05/10] RISCV: Strengthen atomic stores Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 06/10] RISCV: Eliminate AMO op fences Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 07/10] RISCV: Weaken compare_exchange LR/SC pairs Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 08/10] RISCV: Weaken mem_thread_fence Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 09/10] RISCV: Weaken atomic loads Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 10/10] RISCV: Table A.6 conformance tests Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 00/10] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 01/10] RISCV: Eliminate SYNC memory models Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 03/10] RISCV: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 04/10] RISCV: Add AMO release bits Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 05/10] RISCV: Strengthen atomic stores Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 06/10] RISCV: Eliminate AMO op fences Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 07/10] RISCV: Weaken compare_exchange LR/SC pairs Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 08/10] RISCV: Weaken mem_thread_fence Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 09/10] RISCV: Weaken atomic loads Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 10/10] RISCV: Table A.6 conformance tests Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 00/11] RISC-V: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 01/11] RISC-V: Eliminate SYNC memory models Patrick O'Neill
2023-04-28 16:23 ` Jeff Law
2023-05-02 20:12 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 02/11] RISC-V: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-04-28 16:50 ` Jeff Law
2023-05-02 20:12 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 03/11] RISC-V: Enforce subword atomic " Patrick O'Neill
2023-05-02 20:14 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 04/11] RISC-V: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-04-28 17:23 ` Jeff Law
2023-05-02 20:15 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 05/11] RISC-V: Add AMO release bits Patrick O'Neill
2023-04-28 17:34 ` Jeff Law
2023-05-02 20:16 ` Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 06/11] RISC-V: Strengthen atomic stores Patrick O'Neill
2023-04-28 17:40 ` Jeff Law
2023-04-28 17:43 ` Palmer Dabbelt
2023-04-28 21:42 ` Hans Boehm
2023-04-28 22:21 ` Hans Boehm [this message]
2023-04-30 17:10 ` Jeff Law
2023-05-02 20:18 ` [Committed " Patrick O'Neill
2023-05-02 16:11 ` [PATCH v5 " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 07/11] RISC-V: Eliminate AMO op fences Patrick O'Neill
2023-04-28 17:43 ` Jeff Law
2023-05-02 20:19 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 08/11] RISC-V: Weaken LR/SC pairs Patrick O'Neill
2023-04-28 17:56 ` Jeff Law
2023-05-02 20:19 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 09/11] RISC-V: Weaken mem_thread_fence Patrick O'Neill
2023-04-28 18:00 ` Jeff Law
2023-05-02 20:20 ` [Committed " Patrick O'Neill
2023-05-03 12:18 ` [PATCH v5 " Andreas Schwab
2023-05-03 12:22 ` Martin Liška
2023-04-27 16:23 ` [PATCH v5 10/11] RISC-V: Weaken atomic loads Patrick O'Neill
2023-04-28 18:04 ` Jeff Law
2023-05-02 20:20 ` [Committed " Patrick O'Neill
2023-04-27 16:23 ` [PATCH v5 11/11] RISC-V: Table A.6 conformance tests Patrick O'Neill
2023-04-28 18:07 ` Jeff Law
2023-05-02 20:28 ` [Committed " Patrick O'Neill
2023-04-27 17:20 ` [PATCH v5 00/11] RISC-V: Implement ISA Manual Table A.6 Mappings Andrea Parri
2023-04-28 16:14 ` Jeff Law
2023-04-28 16:29 ` Palmer Dabbelt
2023-04-28 17:44 ` Patrick O'Neill
2023-04-28 18:18 ` Patrick O'Neill
[not found] ` <CAMOCf+hK9nedV+UeENbTn=Uy3RpYLeMt04mLiLmDsZyNm83CCg@mail.gmail.com>
2023-04-30 16:37 ` Jeff Law
2023-07-25 18:01 ` [gcc13 backport 00/12] " Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 01/12] RISC-V: Eliminate SYNC memory models Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 02/12] RISC-V: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 03/12] RISC-V: Enforce subword atomic " Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 04/12] RISC-V: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 05/12] RISC-V: Add AMO release bits Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 06/12] RISC-V: Strengthen atomic stores Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 07/12] RISC-V: Eliminate AMO op fences Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 08/12] RISC-V: Weaken LR/SC pairs Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 09/12] RISC-V: Weaken mem_thread_fence Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 10/12] RISC-V: Weaken atomic loads Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 11/12] RISC-V: Table A.6 conformance tests Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 12/12] riscv: fix error: control reaches end of non-void function Patrick O'Neill
2023-07-26 1:22 ` Kito Cheng
2023-07-26 17:41 ` Patrick O'Neill
2023-07-25 19:50 ` [gcc13 backport 00/12] RISC-V: Implement ISA Manual Table A.6 Mappings Jakub Jelinek
2023-07-25 20:01 ` Palmer Dabbelt
2023-07-25 21:02 ` Jeff Law
2023-07-25 21:16 ` Palmer Dabbelt
2023-07-25 19:58 ` Palmer Dabbelt
2023-07-31 16:19 ` [Committed] " Patrick O'Neill
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