From: Palmer Dabbelt <palmer@rivosinc.com>
To: Patrick O'Neill <patrick@rivosinc.com>, jakub@redhat.com
Cc: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com,
Vineet Gupta <vineetg@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
kito.cheng@sifive.com, Daniel Lustig <dlustig@nvidia.com>,
cmuellner@gcc.gnu.org, Andrea Parri <andrea@rivosinc.com>,
hboehm@google.com, Patrick O'Neill <patrick@rivosinc.com>
Subject: Re: [gcc13 backport 00/12] RISC-V: Implement ISA Manual Table A.6 Mappings
Date: Tue, 25 Jul 2023 12:58:42 -0700 (PDT) [thread overview]
Message-ID: <mhng-c86333a4-82a1-422e-8086-6b0d4bab7ada@palmer-ri-x1c9a> (raw)
In-Reply-To: <20230725180206.284777-1-patrick@rivosinc.com>
On Tue, 25 Jul 2023 11:01:54 PDT (-0700), Patrick O'Neill wrote:
> Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
> Jeff Law.
> If there aren't any objections I'll commit this cherry-picked series
> on Thursday (July 27th).
+Jakub
According to the "GCC 13.1.1 Status Report (2023-07-20)", it looks like
we're frozen for 13.2 and thus would need a release maintainer to sign
off on anything we backport until 13.2 is released.
I'm not opposed to the backport, but it does looks like we're down to no
P1 regressions which means we might release very soon. So we should at
least make sure this gets through all the tests and such. It's kind of
splitting hairs as this is a pretty bad set of bugs we're fixing and
distros are probably going to just backport it anyway, so not sure what
the right answer is.
> Patchset on trunk:
> https://inbox.sourceware.org/gcc-patches/20230427162301.1151333-1-patrick@rivosinc.com/
> First commit: f37a36bce81b50a43ec1613c1d08d803642f7506
>
> Also includes bugfix from:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109713
> commit: 4bd434fbfc7865961a8e10d7e9601b28765ce7be
>
> [1] https://inbox.sourceware.org/gcc/mhng-b7423fca-67ec-4ce4-9694-4e062632ceb0@palmer-ri-x1c9/T/#t
>
> Martin Liska (1):
> riscv: fix error: control reaches end of non-void function
>
> Patrick O'Neill (11):
> RISC-V: Eliminate SYNC memory models
> RISC-V: Enforce Libatomic LR/SC SEQ_CST
> RISC-V: Enforce subword atomic LR/SC SEQ_CST
> RISC-V: Enforce atomic compare_exchange SEQ_CST
> RISC-V: Add AMO release bits
> RISC-V: Strengthen atomic stores
> RISC-V: Eliminate AMO op fences
> RISC-V: Weaken LR/SC pairs
> RISC-V: Weaken mem_thread_fence
> RISC-V: Weaken atomic loads
> RISC-V: Table A.6 conformance tests
>
> gcc/config/riscv/riscv-protos.h | 3 +
> gcc/config/riscv/riscv.cc | 66 ++++--
> gcc/config/riscv/sync.md | 196 ++++++++++++------
> .../riscv/amo-table-a-6-amo-add-1.c | 15 ++
> .../riscv/amo-table-a-6-amo-add-2.c | 15 ++
> .../riscv/amo-table-a-6-amo-add-3.c | 15 ++
> .../riscv/amo-table-a-6-amo-add-4.c | 15 ++
> .../riscv/amo-table-a-6-amo-add-5.c | 15 ++
> .../riscv/amo-table-a-6-compare-exchange-1.c | 9 +
> .../riscv/amo-table-a-6-compare-exchange-2.c | 9 +
> .../riscv/amo-table-a-6-compare-exchange-3.c | 9 +
> .../riscv/amo-table-a-6-compare-exchange-4.c | 9 +
> .../riscv/amo-table-a-6-compare-exchange-5.c | 9 +
> .../riscv/amo-table-a-6-compare-exchange-6.c | 10 +
> .../riscv/amo-table-a-6-compare-exchange-7.c | 9 +
> .../gcc.target/riscv/amo-table-a-6-fence-1.c | 14 ++
> .../gcc.target/riscv/amo-table-a-6-fence-2.c | 15 ++
> .../gcc.target/riscv/amo-table-a-6-fence-3.c | 15 ++
> .../gcc.target/riscv/amo-table-a-6-fence-4.c | 15 ++
> .../gcc.target/riscv/amo-table-a-6-fence-5.c | 15 ++
> .../gcc.target/riscv/amo-table-a-6-load-1.c | 16 ++
> .../gcc.target/riscv/amo-table-a-6-load-2.c | 17 ++
> .../gcc.target/riscv/amo-table-a-6-load-3.c | 18 ++
> .../gcc.target/riscv/amo-table-a-6-store-1.c | 16 ++
> .../gcc.target/riscv/amo-table-a-6-store-2.c | 17 ++
> .../riscv/amo-table-a-6-store-compat-3.c | 18 ++
> .../riscv/amo-table-a-6-subword-amo-add-1.c | 9 +
> .../riscv/amo-table-a-6-subword-amo-add-2.c | 9 +
> .../riscv/amo-table-a-6-subword-amo-add-3.c | 9 +
> .../riscv/amo-table-a-6-subword-amo-add-4.c | 9 +
> .../riscv/amo-table-a-6-subword-amo-add-5.c | 9 +
> gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +
> libgcc/config/riscv/atomic.c | 4 +-
> 33 files changed, 563 insertions(+), 75 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c
next prev parent reply other threads:[~2023-07-25 19:58 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220407182918.294892-1-patrick@rivosinc.com>
2023-04-05 21:01 ` [PATCH v2 0/8] RISCV: " Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 1/8] RISCV: Eliminate SYNC memory models Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 2/8] RISCV: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 3/8] RISCV: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 4/8] RISCV: Add AMO release bits Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 5/8] RISCV: Eliminate AMO op fences Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 6/8] RISCV: Weaken compare_exchange LR/SC pairs Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 7/8] RISCV: Weaken atomic stores Patrick O'Neill
2023-04-05 21:01 ` [PATCH v2 8/8] RISCV: Weaken mem_thread_fence Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 00/10] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 01/10] RISCV: Eliminate SYNC memory models Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 03/10] RISCV: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 04/10] RISCV: Add AMO release bits Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 05/10] RISCV: Strengthen atomic stores Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 06/10] RISCV: Eliminate AMO op fences Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 07/10] RISCV: Weaken compare_exchange LR/SC pairs Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 08/10] RISCV: Weaken mem_thread_fence Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 09/10] RISCV: Weaken atomic loads Patrick O'Neill
2023-04-10 18:23 ` [PATCH v3 10/10] RISCV: Table A.6 conformance tests Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 00/10] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 01/10] RISCV: Eliminate SYNC memory models Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 03/10] RISCV: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 04/10] RISCV: Add AMO release bits Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 05/10] RISCV: Strengthen atomic stores Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 06/10] RISCV: Eliminate AMO op fences Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 07/10] RISCV: Weaken compare_exchange LR/SC pairs Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 08/10] RISCV: Weaken mem_thread_fence Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 09/10] RISCV: Weaken atomic loads Patrick O'Neill
2023-04-14 17:09 ` [PATCH v4 10/10] RISCV: Table A.6 conformance tests Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 00/11] RISC-V: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 01/11] RISC-V: Eliminate SYNC memory models Patrick O'Neill
2023-04-28 16:23 ` Jeff Law
2023-05-02 20:12 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 02/11] RISC-V: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-04-28 16:50 ` Jeff Law
2023-05-02 20:12 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 03/11] RISC-V: Enforce subword atomic " Patrick O'Neill
2023-05-02 20:14 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 04/11] RISC-V: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-04-28 17:23 ` Jeff Law
2023-05-02 20:15 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 05/11] RISC-V: Add AMO release bits Patrick O'Neill
2023-04-28 17:34 ` Jeff Law
2023-05-02 20:16 ` Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 06/11] RISC-V: Strengthen atomic stores Patrick O'Neill
2023-04-28 17:40 ` Jeff Law
2023-04-28 17:43 ` Palmer Dabbelt
2023-04-28 21:42 ` Hans Boehm
2023-04-28 22:21 ` Hans Boehm
2023-04-30 17:10 ` Jeff Law
2023-05-02 20:18 ` [Committed " Patrick O'Neill
2023-05-02 16:11 ` [PATCH v5 " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 07/11] RISC-V: Eliminate AMO op fences Patrick O'Neill
2023-04-28 17:43 ` Jeff Law
2023-05-02 20:19 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 08/11] RISC-V: Weaken LR/SC pairs Patrick O'Neill
2023-04-28 17:56 ` Jeff Law
2023-05-02 20:19 ` [Committed " Patrick O'Neill
2023-04-27 16:22 ` [PATCH v5 09/11] RISC-V: Weaken mem_thread_fence Patrick O'Neill
2023-04-28 18:00 ` Jeff Law
2023-05-02 20:20 ` [Committed " Patrick O'Neill
2023-05-03 12:18 ` [PATCH v5 " Andreas Schwab
2023-05-03 12:22 ` Martin Liška
2023-04-27 16:23 ` [PATCH v5 10/11] RISC-V: Weaken atomic loads Patrick O'Neill
2023-04-28 18:04 ` Jeff Law
2023-05-02 20:20 ` [Committed " Patrick O'Neill
2023-04-27 16:23 ` [PATCH v5 11/11] RISC-V: Table A.6 conformance tests Patrick O'Neill
2023-04-28 18:07 ` Jeff Law
2023-05-02 20:28 ` [Committed " Patrick O'Neill
2023-04-27 17:20 ` [PATCH v5 00/11] RISC-V: Implement ISA Manual Table A.6 Mappings Andrea Parri
2023-04-28 16:14 ` Jeff Law
2023-04-28 16:29 ` Palmer Dabbelt
2023-04-28 17:44 ` Patrick O'Neill
2023-04-28 18:18 ` Patrick O'Neill
[not found] ` <CAMOCf+hK9nedV+UeENbTn=Uy3RpYLeMt04mLiLmDsZyNm83CCg@mail.gmail.com>
2023-04-30 16:37 ` Jeff Law
2023-07-25 18:01 ` [gcc13 backport 00/12] " Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 01/12] RISC-V: Eliminate SYNC memory models Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 02/12] RISC-V: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 03/12] RISC-V: Enforce subword atomic " Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 04/12] RISC-V: Enforce atomic compare_exchange SEQ_CST Patrick O'Neill
2023-07-25 18:01 ` [gcc13 backport 05/12] RISC-V: Add AMO release bits Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 06/12] RISC-V: Strengthen atomic stores Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 07/12] RISC-V: Eliminate AMO op fences Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 08/12] RISC-V: Weaken LR/SC pairs Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 09/12] RISC-V: Weaken mem_thread_fence Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 10/12] RISC-V: Weaken atomic loads Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 11/12] RISC-V: Table A.6 conformance tests Patrick O'Neill
2023-07-25 18:02 ` [gcc13 backport 12/12] riscv: fix error: control reaches end of non-void function Patrick O'Neill
2023-07-26 1:22 ` Kito Cheng
2023-07-26 17:41 ` Patrick O'Neill
2023-07-25 19:50 ` [gcc13 backport 00/12] RISC-V: Implement ISA Manual Table A.6 Mappings Jakub Jelinek
2023-07-25 20:01 ` Palmer Dabbelt
2023-07-25 21:02 ` Jeff Law
2023-07-25 21:16 ` Palmer Dabbelt
2023-07-25 19:58 ` Palmer Dabbelt [this message]
2023-07-31 16:19 ` [Committed] " Patrick O'Neill
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=mhng-c86333a4-82a1-422e-8086-6b0d4bab7ada@palmer-ri-x1c9a \
--to=palmer@rivosinc.com \
--cc=andrea@rivosinc.com \
--cc=andrew@sifive.com \
--cc=cmuellner@gcc.gnu.org \
--cc=dlustig@nvidia.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=hboehm@google.com \
--cc=jakub@redhat.com \
--cc=jeffreyalaw@gmail.com \
--cc=kito.cheng@sifive.com \
--cc=patrick@rivosinc.com \
--cc=vineetg@rivosinc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).