* [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments
@ 2023-08-03 8:08 Jan Beulich
2023-08-03 8:09 ` [PATCH 01/10] x86: "prefix_extra" tidying Jan Beulich
` (10 more replies)
0 siblings, 11 replies; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:08 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
Having noticed various bogus uses, I thought I'd go through and audit
them all. This is the result, with some other attributes also adjusted
as noticed in the process. (I think this tidying also is a good thing
to have ahead of APX further complicating insn length calculations.)
01: "prefix_extra" tidying
02: "sse4arg" adjustments
03: "ssemuladd" adjustments
04: "prefix_extra" can't really be "2"
05: replace/correct bogus "prefix_extra"
06: drop stray "prefix_extra"
07: add (adjust) XOP insn attributes
08: add missing "prefix" attribute to VF{,C}MULC
09: correct "length_immediate" in a few cases
10: drop redundant "prefix_data16" attributes
Jan
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 01/10] x86: "prefix_extra" tidying
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
@ 2023-08-03 8:09 ` Jan Beulich
2023-08-04 1:50 ` Hongtao Liu
2023-08-03 8:10 ` [PATCH 02/10] x86: "sse4arg" adjustments Jan Beulich
` (9 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:09 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
Drop SSE5 leftovers from both its comment and its default calculation.
A value of 2 simply cannot occur anymore. Instead extend the comment to
mention the use of the attribute in "length_vex", clarifying why
"prefix_extra" can actually be meaningful on VEX-encoded insns despite
those not having any real prefixes except possibly segment overrides.
gcc/
* config/i386/i386.md (prefix_extra): Correct comment. Fold
cases yielding 2 into ones yielding 1.
---
I question the 3DNow! aspect here: There's no extra prefix there. It's
an immediate instead which "sub-divides" major opcode 0f0f.
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -620,13 +620,11 @@
(const_int 0)))
;; There are also additional prefixes in 3DNOW, SSSE3.
-;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
-;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
+;; While generally inapplicable to VEX/XOP/EVEX encodings, "length_vex" uses
+;; the attribute evaluating to zero to know that VEX2 encoding may be usable.
(define_attr "prefix_extra" ""
- (cond [(eq_attr "type" "ssemuladd,sse4arg")
- (const_int 2)
- (eq_attr "type" "sseiadd1,ssecvt1")
+ (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
(const_int 1)
]
(const_int 0)))
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 02/10] x86: "sse4arg" adjustments
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
2023-08-03 8:09 ` [PATCH 01/10] x86: "prefix_extra" tidying Jan Beulich
@ 2023-08-03 8:10 ` Jan Beulich
2023-08-04 1:54 ` Hongtao Liu
2023-08-03 8:10 ` [PATCH 03/10] x86: "ssemuladd" adjustments Jan Beulich
` (8 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:10 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
Record common properties in other attributes' default calculations:
There's always a 1-byte immediate, and they're always encoded in a VEX3-
like manner (note that "prefix_extra" already evaluates to 1 in this
case). The drop now (or already previously) redundant explicit
attributes, adding "mode" ones where they were missing.
Furthermore use "sse4arg" consistently for all VPCOM* insns; so far
signed comparisons did use it, while unsigned ones used "ssecmp". Note
that while they have (not counting the explicit or implicit immediate
operand) they really only have 3 operands, the operator is also counted
in those patterns. That's relevant for establishing the "memory"
attribute's value, and at the same time benign when there are only
register operands.
Note that despite also having 4 operands, multiply-add insns aren't
affected by this change, as they use "ssemuladd" for "type".
gcc/
* config/i386/i386.md (length_immediate): Handle "sse4arg".
(prefix): Likewise.
(*xop_pcmov_<mode>): Add "mode" attribute.
* config/i386/mmx.md (*xop_maskcmp<mode>3): Drop "prefix_data16",
"prefix_rep", "prefix_extra", and "length_immediate" attributes.
(*xop_maskcmp_uns<mode>3): Likewise. Switch "type" to "sse4arg".
(*xop_pcmov_<mode>): Add "mode" attribute.
* config/i386/sse.md (xop_pcmov_<mode><avxsizesuffix>): Add "mode"
attribute.
(xop_maskcmp<mode>3): Drop "prefix_data16", "prefix_rep",
"prefix_extra", and "length_immediate" attributes.
(xop_maskcmp_uns<mode>3): Likewise. Switch "type" to "sse4arg".
(xop_maskcmp_uns2<mode>3): Drop "prefix_data16", "prefix_extra",
and "length_immediate" attributes. Switch "type" to "sse4arg".
(xop_pcom_tf<mode>3): Likewise.
(xop_vpermil2<mode>3): Drop "length_immediate" attribute.
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -536,6 +536,8 @@
(cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
bitmanip,imulx,msklog,mskmov")
(const_int 0)
+ (eq_attr "type" "sse4arg")
+ (const_int 1)
(eq_attr "unit" "i387,sse,mmx")
(const_int 0)
(eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1,
@@ -635,6 +637,8 @@
(const_string "vex")
(eq_attr "mode" "XI,V16SF,V8DF")
(const_string "evex")
+ (eq_attr "type" "sse4arg")
+ (const_string "vex")
]
(const_string "orig")))
@@ -23286,7 +23290,8 @@
(match_operand:MODEF 3 "register_operand" "x")))]
"TARGET_XOP"
"vpcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
- [(set_attr "type" "sse4arg")])
+ [(set_attr "type" "sse4arg")
+ (set_attr "mode" "TI")])
;; These versions of the min/max patterns are intentionally ignorant of
;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2909,10 +2909,6 @@
"TARGET_XOP"
"vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*xop_maskcmp<mode>3"
@@ -2923,10 +2919,6 @@
"TARGET_XOP"
"vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*xop_maskcmp_uns<mode>3"
@@ -2936,11 +2928,7 @@
(match_operand:MMXMODEI 3 "register_operand" "x")]))]
"TARGET_XOP"
"vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
+ [(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
(define_insn "*xop_maskcmp_uns<mode>3"
@@ -2950,11 +2938,7 @@
(match_operand:VI_16_32 3 "register_operand" "x")]))]
"TARGET_XOP"
"vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
+ [(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
(define_expand "vec_cmp<mode><mode>"
@@ -3144,7 +3128,8 @@
(match_operand:MMXMODE124 2 "register_operand" "x")))]
"TARGET_XOP && TARGET_MMX_WITH_SSE"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")])
+ [(set_attr "type" "sse4arg")
+ (set_attr "mode" "TI")])
(define_insn "*xop_pcmov_<mode>"
[(set (match_operand:VI_16_32 0 "register_operand" "=x")
@@ -3154,7 +3139,8 @@
(match_operand:VI_16_32 2 "register_operand" "x")))]
"TARGET_XOP"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")])
+ [(set_attr "type" "sse4arg")
+ (set_attr "mode" "TI")])
;; XOP permute instructions
(define_insn "mmx_ppermv64"
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -24821,7 +24821,8 @@
(match_operand:V_128_256 2 "nonimmediate_operand" "xm,x")))]
"TARGET_XOP"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")])
+ [(set_attr "type" "sse4arg")
+ (set_attr "mode" "<sseinsnmode>")])
;; Recognize XOP's vpcmov from canonical (xor (and (xor t f) c) f)
(define_split
@@ -25739,10 +25740,6 @@
"TARGET_XOP"
"vpcom%Y1<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "xop_maskcmp_uns<mode>3"
@@ -25752,11 +25749,7 @@
(match_operand:VI_128 3 "nonimmediate_operand" "xm")]))]
"TARGET_XOP"
"vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
+ [(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
@@ -25771,10 +25764,7 @@
UNSPEC_XOP_UNSIGNED_CMP))]
"TARGET_XOP"
"vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
+ [(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
;; Pcomtrue and pcomfalse support. These are useless instructions, but are
@@ -25792,10 +25782,7 @@
? "vpcomtrue<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
: "vpcomfalse<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}");
}
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
+ [(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
(define_insn "xop_vpermil2<mode>3"
@@ -25809,7 +25796,6 @@
"TARGET_XOP"
"vpermil2<ssemodesuffix>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}"
[(set_attr "type" "sse4arg")
- (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 03/10] x86: "ssemuladd" adjustments
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
2023-08-03 8:09 ` [PATCH 01/10] x86: "prefix_extra" tidying Jan Beulich
2023-08-03 8:10 ` [PATCH 02/10] x86: "sse4arg" adjustments Jan Beulich
@ 2023-08-03 8:10 ` Jan Beulich
2023-08-04 1:55 ` Hongtao Liu
2023-08-03 8:11 ` [PATCH 04/10] x86: "prefix_extra" can't really be "2" Jan Beulich
` (7 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:10 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
They're all VEX3- (also covering XOP) or EVEX-encoded. Express that in
the default calculation of "prefix". FMA4 insns also all have a 1-byte
immediate operand.
Where the default calculation is not sufficient / applicable, add
explicit "prefix" attributes. While there also add a "mode" attribute to
fma_<complexpairopname>_<mode>_pair.
gcc/
* config/i386/i386.md (isa): Move up.
(length_immediate): Handle "fma4".
(prefix): Handle "ssemuladd".
* config/i386/sse.md (*fma_fmadd_<mode>): Add "prefix" attribute.
(<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>):
Likewise.
(<avx512>_fmadd_<mode>_mask<round_name>): Likewise.
(<avx512>_fmadd_<mode>_mask3<round_name>): Likewise.
(<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>):
Likewise.
(<avx512>_fmsub_<mode>_mask<round_name>): Likewise.
(<avx512>_fmsub_<mode>_mask3<round_name>): Likewise.
(*fma_fnmadd_<mode>): Likewise.
(<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>):
Likewise.
(<avx512>_fnmadd_<mode>_mask<round_name>): Likewise.
(<avx512>_fnmadd_<mode>_mask3<round_name>): Likewise.
(<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>):
Likewise.
(<avx512>_fnmsub_<mode>_mask<round_name>): Likewise.
(<avx512>_fnmsub_<mode>_mask3<round_name>): Likewise.
(<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>):
Likewise.
(<avx512>_fmaddsub_<mode>_mask<round_name>): Likewise.
(<avx512>_fmaddsub_<mode>_mask3<round_name>): Likewise.
(<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>):
Likewise.
(<avx512>_fmsubadd_<mode>_mask<round_name>): Likewise.
(<avx512>_fmsubadd_<mode>_mask3<round_name>): Likewise.
(*fmai_fmadd_<mode>): Likewise.
(*fmai_fmsub_<mode>): Likewise.
(*fmai_fnmadd_<mode><round_name>): Likewise.
(*fmai_fnmsub_<mode><round_name>): Likewise.
(avx512f_vmfmadd_<mode>_mask<round_name>): Likewise.
(avx512f_vmfmadd_<mode>_mask3<round_name>): Likewise.
(avx512f_vmfmadd_<mode>_maskz_1<round_name>): Likewise.
(*avx512f_vmfmsub_<mode>_mask<round_name>): Likewise.
(avx512f_vmfmsub_<mode>_mask3<round_name>): Likewise.
(*avx512f_vmfmsub_<mode>_maskz_1<round_name>): Likewise.
(avx512f_vmfnmadd_<mode>_mask<round_name>): Likewise.
(avx512f_vmfnmadd_<mode>_mask3<round_name>): Likewise.
(avx512f_vmfnmadd_<mode>_maskz_1<round_name>): Likewise.
(*avx512f_vmfnmsub_<mode>_mask<round_name>): Likewise.
(*avx512f_vmfnmsub_<mode>_mask3<round_name>): Likewise.
(*avx512f_vmfnmsub_<mode>_maskz_1<round_name>): Likewise.
(*fma4i_vmfmadd_<mode>): Likewise.
(*fma4i_vmfmsub_<mode>): Likewise.
(*fma4i_vmfnmadd_<mode>): Likewise.
(*fma4i_vmfnmsub_<mode>): Likewise.
(fma_<complexopname>_<mode><sdc_maskz_name><round_name>): Likewise.
(<avx512>_<complexopname>_<mode>_mask<round_name>): Likewise.
(avx512fp16_fma_<complexopname>sh_v8hf<mask_scalarcz_name><round_scalarcz_name>):
Likewise.
(avx512fp16_<complexopname>sh_v8hf_mask<round_name>): Likewise.
(xop_p<macs><ssemodesuffix><ssemodesuffix>): Likewise.
(xop_p<macs>dql): Likewise.
(xop_p<macs>dqh): Likewise.
(xop_p<macs>wd): Likewise.
(xop_p<madcs>wd): Likewise.
(fma_<complexpairopname>_<mode>_pair): Likewise. Add "mode" attribute.
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -531,12 +531,23 @@
(const_string "unknown")]
(const_string "integer")))
+;; Used to control the "enabled" attribute on a per-instruction basis.
+(define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx,
+ x64_avx,x64_avx512bw,x64_avx512dq,aes,
+ sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
+ avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
+ avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
+ avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma,
+ avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl"
+ (const_string "base"))
+
;; The (bounding maximum) length of an instruction immediate.
(define_attr "length_immediate" ""
(cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
bitmanip,imulx,msklog,mskmov")
(const_int 0)
- (eq_attr "type" "sse4arg")
+ (ior (eq_attr "type" "sse4arg")
+ (eq_attr "isa" "fma4"))
(const_int 1)
(eq_attr "unit" "i387,sse,mmx")
(const_int 0)
@@ -637,6 +648,10 @@
(const_string "vex")
(eq_attr "mode" "XI,V16SF,V8DF")
(const_string "evex")
+ (eq_attr "type" "ssemuladd")
+ (if_then_else (eq_attr "isa" "fma4")
+ (const_string "vex")
+ (const_string "maybe_evex"))
(eq_attr "type" "sse4arg")
(const_string "vex")
]
@@ -842,16 +857,6 @@
;; Define attribute to indicate unaligned ssemov insns
(define_attr "movu" "0,1" (const_string "0"))
-;; Used to control the "enabled" attribute on a per-instruction basis.
-(define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx,
- x64_avx,x64_avx512bw,x64_avx512dq,aes,
- sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
- avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
- avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
- avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma,
- avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl"
- (const_string "base"))
-
;; Define instruction set of MMX instructions
(define_attr "mmx_isa" "base,native,sse,sse_noavx,avx"
(const_string "base"))
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5422,6 +5422,7 @@
vfmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cond_fma<mode>"
@@ -5461,6 +5462,7 @@
vfmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmadd_<mode>_mask3<round_name>"
@@ -5475,6 +5477,7 @@
"TARGET_AVX512F"
"vfmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fmsub_<mode>"
@@ -5522,6 +5525,7 @@
vfmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cond_fms<mode>"
@@ -5563,6 +5567,7 @@
vfmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmsub_<mode>_mask3<round_name>"
@@ -5578,6 +5583,7 @@
"TARGET_AVX512F && <round_mode512bit_condition>"
"vfmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fnmadd_<mode>"
@@ -5625,6 +5631,7 @@
vfnmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfnmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cond_fnma<mode>"
@@ -5666,6 +5673,7 @@
vfnmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfnmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fnmadd_<mode>_mask3<round_name>"
@@ -5681,6 +5689,7 @@
"TARGET_AVX512F && <round_mode512bit_condition>"
"vfnmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fnmsub_<mode>"
@@ -5730,6 +5739,7 @@
vfnmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfnmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cond_fnms<mode>"
@@ -5773,6 +5783,7 @@
vfnmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfnmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fnmsub_<mode>_mask3<round_name>"
@@ -5789,6 +5800,7 @@
"TARGET_AVX512F"
"vfnmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
;; FMA parallel floating point multiply addsub and subadd operations.
@@ -5889,6 +5901,7 @@
vfmaddsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfmaddsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmaddsub_<mode>_mask<round_name>"
@@ -5906,6 +5919,7 @@
vfmaddsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmaddsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmaddsub_<mode>_mask3<round_name>"
@@ -5921,6 +5935,7 @@
"TARGET_AVX512F"
"vfmaddsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fmsubadd_<mode>"
@@ -5956,6 +5971,7 @@
vfmsubadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
vfmsubadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmsubadd_<mode>_mask<round_name>"
@@ -5974,6 +5990,7 @@
vfmsubadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
vfmsubadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "<avx512>_fmsubadd_<mode>_mask3<round_name>"
@@ -5990,6 +6007,7 @@
"TARGET_AVX512F"
"vfmsubadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
;; FMA3 floating point scalar intrinsics. These merge result with
@@ -6057,6 +6075,7 @@
vfmadd132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
vfmadd213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fmai_fmsub_<mode>"
@@ -6074,6 +6093,7 @@
vfmsub132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
vfmsub213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fmai_fnmadd_<mode><round_name>"
@@ -6091,6 +6111,7 @@
vfnmadd132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
vfnmadd213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "*fmai_fnmsub_<mode><round_name>"
@@ -6109,6 +6130,7 @@
vfnmsub132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
vfnmsub213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfmadd_<mode>_mask<round_name>"
@@ -6128,6 +6150,7 @@
vfmadd132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
vfmadd213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfmadd_<mode>_mask3<round_name>"
@@ -6145,6 +6168,7 @@
"TARGET_AVX512F"
"vfmadd231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "avx512f_vmfmadd_<mode>_maskz<round_expand_name>"
@@ -6178,6 +6202,7 @@
vfmadd132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
vfmadd213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfmsub_<mode>_mask<round_name>"
@@ -6198,6 +6223,7 @@
vfmsub132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
vfmsub213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfmsub_<mode>_mask3<round_name>"
@@ -6216,6 +6242,7 @@
"TARGET_AVX512F"
"vfmsub231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfmsub_<mode>_maskz_1<round_name>"
@@ -6236,6 +6263,7 @@
vfmsub132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
vfmsub213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfnmadd_<mode>_mask<round_name>"
@@ -6256,6 +6284,7 @@
vfnmadd132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
vfnmadd213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx512f_vmfnmadd_<mode>_mask3<round_name>"
@@ -6274,6 +6303,7 @@
"TARGET_AVX512F"
"vfnmadd231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "avx512f_vmfnmadd_<mode>_maskz<round_expand_name>"
@@ -6308,6 +6338,7 @@
vfnmadd132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
vfnmadd213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfnmsub_<mode>_mask<round_name>"
@@ -6329,6 +6360,7 @@
vfnmsub132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
vfnmsub213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfnmsub_<mode>_mask3<round_name>"
@@ -6348,6 +6380,7 @@
"TARGET_AVX512F"
"vfnmsub231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn "*avx512f_vmfnmsub_<mode>_maskz_1<round_name>"
@@ -6369,6 +6402,7 @@
vfnmsub132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
vfnmsub213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
;; FMA4 floating point scalar intrinsics. These write the
@@ -6398,6 +6432,7 @@
"TARGET_FMA4"
"vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfmsub_<mode>"
@@ -6413,6 +6448,7 @@
"TARGET_FMA4"
"vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfnmadd_<mode>"
@@ -6428,6 +6464,7 @@
"TARGET_FMA4"
"vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfnmsub_<mode>"
@@ -6444,6 +6481,7 @@
"TARGET_FMA4"
"vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -6591,6 +6629,7 @@
"TARGET_AVX512FP16 && <sdc_mask_mode512bit_condition> && <round_mode512bit_condition>"
"v<complexopname><ssemodesuffix>\t{<round_sdc_mask_op4>%2, %1, %0<sdc_mask_op4>|%0<sdc_mask_op4>, %1, %2<round_sdc_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_insn_and_split "fma_<mode>_fadd_fmul"
@@ -6654,7 +6693,9 @@
UNSPEC_COMPLEX_F_C_MA_PAIR))]
"TARGET_AVX512FP16"
"v<complexpairopname>ph\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssemuladd")])
+ [(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<MODE>")])
(define_insn_and_split "fma_<mode>_fmaddc_bcst"
[(set (match_operand:VF_AVX512FP16VL 0 "register_operand")
@@ -6726,6 +6767,7 @@
"TARGET_AVX512FP16 && <round_mode512bit_condition>"
"v<complexopname><ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "cmul<conj_op><mode>3"
@@ -6913,6 +6955,7 @@
"TARGET_AVX512FP16"
"v<complexopname>sh\t{<round_scalarcz_mask_op4>%2, %1, %0<mask_scalarcz_operand4>|%0<mask_scalarcz_operand4>, %1, %2<round_scalarcz_mask_op4>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "V8HF")])
(define_insn "avx512fp16_<complexopname>sh_v8hf_mask<round_name>"
@@ -6932,6 +6975,7 @@
"TARGET_AVX512FP16"
"v<complexopname>sh\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "evex")
(set_attr "mode" "V8HF")])
(define_insn "avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>"
@@ -24721,6 +24765,7 @@
"TARGET_XOP"
"vp<macs><ssemodesuffix><ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(define_insn "xop_p<macs>dql"
@@ -24739,6 +24784,7 @@
"TARGET_XOP"
"vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(define_insn "xop_p<macs>dqh"
@@ -24757,6 +24803,7 @@
"TARGET_XOP"
"vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
;; XOP parallel integer multiply/add instructions for the intrinisics
@@ -24778,6 +24825,7 @@
"TARGET_XOP"
"vp<macs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(define_insn "xop_p<madcs>wd"
@@ -24810,6 +24858,7 @@
"TARGET_XOP"
"vp<madcs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemuladd")
+ (set_attr "prefix" "vex")
(set_attr "mode" "TI")])
;; XOP parallel XMM conditional moves
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 04/10] x86: "prefix_extra" can't really be "2"
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
` (2 preceding siblings ...)
2023-08-03 8:10 ` [PATCH 03/10] x86: "ssemuladd" adjustments Jan Beulich
@ 2023-08-03 8:11 ` Jan Beulich
2023-08-04 1:55 ` Hongtao Liu
2023-08-03 8:12 ` [PATCH 05/10] x86: replace/correct bogus "prefix_extra" Jan Beulich
` (6 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:11 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
In the three remaining instances separate "prefix_0f" and "prefix_rep"
are what is wanted instead.
gcc/
* config/i386/i386.md (rd<fsgs>base<mode>): Add "prefix_0f" and
"prefix_rep". Drop "prefix_extra".
(wr<fsgs>base<mode>): Likewise.
(ptwrite<mode>): Likewise.
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -25914,7 +25914,8 @@
"TARGET_64BIT && TARGET_FSGSBASE"
"rd<fsgs>base\t%0"
[(set_attr "type" "other")
- (set_attr "prefix_extra" "2")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_rep" "1")])
(define_insn "wr<fsgs>base<mode>"
[(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
@@ -25922,7 +25923,8 @@
"TARGET_64BIT && TARGET_FSGSBASE"
"wr<fsgs>base\t%0"
[(set_attr "type" "other")
- (set_attr "prefix_extra" "2")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_rep" "1")])
(define_insn "ptwrite<mode>"
[(unspec_volatile [(match_operand:SWI48 0 "nonimmediate_operand" "rm")]
@@ -25930,7 +25932,8 @@
"TARGET_PTWRITE"
"ptwrite\t%0"
[(set_attr "type" "other")
- (set_attr "prefix_extra" "2")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_rep" "1")])
(define_insn "@rdrand<mode>"
[(set (match_operand:SWI248 0 "register_operand" "=r")
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 05/10] x86: replace/correct bogus "prefix_extra"
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
` (3 preceding siblings ...)
2023-08-03 8:11 ` [PATCH 04/10] x86: "prefix_extra" can't really be "2" Jan Beulich
@ 2023-08-03 8:12 ` Jan Beulich
2023-08-04 1:56 ` Hongtao Liu
2023-08-03 8:12 ` [PATCH 06/10] x86: drop stray "prefix_extra" Jan Beulich
` (5 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:12 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
In the rdrand and rdseed cases "prefix_0f" is meant instead. For
mmx_floatv2siv2sf2 1 is correct only for the first alternative. For
the integer min/max cases 1 uniformly applies to legacy and VEX
encodings (the UB and SW variants are dealt with separately anyway).
Same for {,V}MOVNTDQA.
Unlike {,V}PEXTRW, which has two encoding forms, {,V}PINSRW only has
a single form in 0f space. (In *vec_extract<mode> note that the
dropped part if the condition also referenced non-existing alternative
2.)
Of the integer compare insns, only the 64-bit element forms are encoded
in 0f38 space.
gcc/
* config/i386/i386.md (@rdrand<mode>): Add "prefix_0f". Drop
"prefix_extra".
(@rdseed<mode>): Likewise.
* config/i386/mmx.md (<code><mode>3 [smaxmin and umaxmin cases]):
Adjust "prefix_extra".
* config/i386/sse.md (@vec_set<mode>_0): Likewise.
(*sse4_1_<code><mode>3<mask_name>): Likewise.
(*avx2_eq<mode>3): Likewise.
(avx2_gt<mode>3): Likewise.
(<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
(*vec_extract<mode>): Likewise.
(<vi8_sse4_1_avx2_avx512>_movntdqa): Likewise.
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -25943,7 +25943,7 @@
"TARGET_RDRND"
"rdrand\t%0"
[(set_attr "type" "other")
- (set_attr "prefix_extra" "1")])
+ (set_attr "prefix_0f" "1")])
(define_insn "@rdseed<mode>"
[(set (match_operand:SWI248 0 "register_operand" "=r")
@@ -25953,7 +25953,7 @@
"TARGET_RDSEED"
"rdseed\t%0"
[(set_attr "type" "other")
- (set_attr "prefix_extra" "1")])
+ (set_attr "prefix_0f" "1")])
(define_expand "pause"
[(set (match_dup 0)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2483,7 +2483,7 @@
vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1,1,*")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "TI")])
@@ -2532,7 +2532,7 @@
vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1,1,*")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "TI")])
@@ -2561,7 +2561,7 @@
vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1,1,*")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "TI")])
@@ -2623,7 +2623,7 @@
vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1,1,*")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "TI")])
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -11064,7 +11064,7 @@
(const_string "1")
(const_string "*")))
(set (attr "prefix_extra")
- (if_then_else (eq_attr "alternative" "5,6,7,8,9")
+ (if_then_else (eq_attr "alternative" "5,6,9")
(const_string "1")
(const_string "*")))
(set (attr "length_immediate")
@@ -16779,7 +16779,7 @@
vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1,1,*")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "TI")])
@@ -16813,7 +16813,10 @@
"TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecmp")
- (set_attr "prefix_extra" "1")
+ (set (attr "prefix_extra")
+ (if_then_else (eq (const_string "<MODE>mode") (const_string "V4DImode"))
+ (const_string "1")
+ (const_string "*")))
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
@@ -17048,7 +17051,10 @@
"TARGET_AVX2"
"vpcmpgt<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecmp")
- (set_attr "prefix_extra" "1")
+ (set (attr "prefix_extra")
+ (if_then_else (eq (const_string "<MODE>mode") (const_string "V4DImode"))
+ (const_string "1")
+ (const_string "*")))
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
@@ -18843,7 +18849,7 @@
(const_string "*")))
(set (attr "prefix_extra")
(if_then_else
- (and (not (match_test "TARGET_AVX"))
+ (ior (eq_attr "prefix" "evex")
(match_test "GET_MODE_NUNITS (<MODE>mode) == 8"))
(const_string "*")
(const_string "1")))
@@ -20004,8 +20010,7 @@
(set_attr "prefix_data16" "1")
(set (attr "prefix_extra")
(if_then_else
- (and (eq_attr "alternative" "0,2")
- (eq (const_string "<MODE>mode") (const_string "V8HImode")))
+ (eq (const_string "<MODE>mode") (const_string "V8HImode"))
(const_string "*")
(const_string "1")))
(set_attr "length_immediate" "1")
@@ -22349,7 +22354,7 @@
"%vmovntdqa\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
- (set_attr "prefix_extra" "1,1,*")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 06/10] x86: drop stray "prefix_extra"
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
` (4 preceding siblings ...)
2023-08-03 8:12 ` [PATCH 05/10] x86: replace/correct bogus "prefix_extra" Jan Beulich
@ 2023-08-03 8:12 ` Jan Beulich
2023-08-04 1:56 ` Hongtao Liu
2023-08-03 8:12 ` [PATCH 07/10] x86: add (adjust) XOP insn attributes Jan Beulich
` (4 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:12 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
While the attribute is relevant for legacy- and VEX-encoded insns, it is
of no relevance for EVEX-encoded ones.
While there in <mask_codefor>avx512dq_broadcast<mode><mask_name>_1 add
the missing "length_immediate".
gcc/
* config/i386/sse.md
(*<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Drop
"prefix_extra".
(avx512dq_vextract<shuffletype>64x2_1_mask): Likewise.
(*avx512dq_vextract<shuffletype>64x2_1): Likewise.
(avx512f_vextract<shuffletype>32x4_1_mask): Likewise.
(*avx512f_vextract<shuffletype>32x4_1): Likewise.
(vec_extract_lo_<mode>_mask [AVX512 forms]): Likewise.
(vec_extract_lo_<mode> [AVX512 forms]): Likewise.
(vec_extract_hi_<mode>_mask [AVX512 forms]): Likewise.
(vec_extract_hi_<mode> [AVX512 forms]): Likewise.
(@vec_extract_lo_<mode> [AVX512 forms]): Likewise.
(@vec_extract_hi_<mode> [AVX512 forms]): Likewise.
(vec_extract_lo_v64qi): Likewise.
(vec_extract_hi_v64qi): Likewise.
(*vec_widen_umult_even_v16si<mask_name>): Likewise.
(*vec_widen_smult_even_v16si<mask_name>): Likewise.
(*avx512f_<code><mode>3<mask_name>): Likewise.
(*vec_extractv4ti): Likewise.
(avx512bw_<code>v32qiv32hi2<mask_name>): Likewise.
(<mask_codefor>avx512dq_broadcast<mode><mask_name>_1): Likewise.
Add "length_immediate".
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4030,7 +4030,6 @@
vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
[(set_attr "type" "ssecmp")
- (set_attr "prefix_extra" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -4128,7 +4127,6 @@
vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
[(set_attr "type" "ssecmp")
- (set_attr "prefix_extra" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -11487,7 +11485,6 @@
return "vextract<shuffletype>64x2\t{%2, %1, %0%{%5%}%N4|%0%{%5%}%N4, %1, %2}";
}
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -11506,7 +11503,6 @@
return "vextract<shuffletype>64x2\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -11554,7 +11550,6 @@
return "vextract<shuffletype>32x4\t{%2, %1, %0%{%7%}%N6|%0%{%7%}%N6, %1, %2}";
}
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -11577,7 +11572,6 @@
return "vextract<shuffletype>32x4\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -11671,7 +11665,6 @@
&& (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
"vextract<shuffletype>64x4\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "evex")
@@ -11691,7 +11684,6 @@
return "#";
}
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,store,load")
(set_attr "prefix" "evex")
@@ -11710,7 +11702,6 @@
&& (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
"vextract<shuffletype>64x4\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -11724,7 +11715,6 @@
"TARGET_AVX512F"
"vextract<shuffletype>64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -11744,7 +11734,6 @@
&& (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
"vextract<shuffletype>32x8\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -11762,7 +11751,6 @@
vextract<shuffletype>32x8\t{$0x1, %1, %0|%0, %1, 0x1}
vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "isa" "avx512dq,noavx512dq")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
@@ -11850,7 +11838,6 @@
&& (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
"vextract<shuffletype>32x8\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "evex")
@@ -11880,7 +11867,6 @@
return "#";
}
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,load,store")
(set_attr "prefix" "evex")
@@ -11923,7 +11909,6 @@
&& (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
"vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "evex")
@@ -11961,7 +11946,6 @@
&& (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
"vextract<shuffletype>64x2\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<sseinsnmode>")])
@@ -12013,7 +11997,6 @@
&& (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
"vextract<shuffletype>32x4\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -12102,7 +12085,6 @@
operands[1] = gen_lowpart (<ssehalfvecmode>mode, operands[1]);
}
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,load,store")
(set_attr "prefix" "evex")
@@ -12123,7 +12105,6 @@
"TARGET_AVX512F"
"vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
@@ -12204,7 +12185,6 @@
operands[1] = gen_lowpart (V32QImode, operands[1]);
}
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,load,store")
(set_attr "prefix" "evex")
@@ -12233,7 +12213,6 @@
"TARGET_AVX512F"
"vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
@@ -15446,7 +15425,6 @@
"TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
- (set_attr "prefix_extra" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
@@ -15562,7 +15540,6 @@
"TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
- (set_attr "prefix_extra" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
@@ -16585,7 +16562,6 @@
"TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseiadd")
- (set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -20322,7 +20298,6 @@
"TARGET_AVX512F"
"vextracti32x4\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
@@ -21893,7 +21868,6 @@
}
[(set_attr "type" "sseishft")
(set_attr "atom_unit" "sishuf")
- (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -22666,7 +22640,6 @@
"TARGET_AVX512BW"
"vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
- (set_attr "prefix_extra" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
@@ -26796,7 +26769,7 @@
vshuf<shuffletype>32x4\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}
vbroadcast<shuffletype>32x8\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
- (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1,*")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -26813,7 +26786,7 @@
vshuf<shuffletype>64x2\t{$0x0, %<xtg_mode>1, %<xtg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<xtg_mode>1, %<xtg_mode>1, 0x0}
vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
- (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 07/10] x86: add (adjust) XOP insn attributes
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
` (5 preceding siblings ...)
2023-08-03 8:12 ` [PATCH 06/10] x86: drop stray "prefix_extra" Jan Beulich
@ 2023-08-03 8:12 ` Jan Beulich
2023-08-04 1:57 ` Hongtao Liu
2023-08-03 8:13 ` [PATCH 08/10] x86: add missing "prefix" attribute to VF{,C}MULC Jan Beulich
` (3 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:12 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
Many were lacking "prefix" and "prefix_extra", some had a bogus value of
2 for "prefix_extra" (presumably inherited from their SSE5 counterparts,
which are long gone) and a meaningless "prefix_data16" one. Where
missing, "mode" attributes are also added. (Note that "sse4arg" and
"ssemuladd" ones don't need further adjustment in this regard.)
gcc/
* config/i386/sse.md (xop_phadd<u>bw): Add "prefix",
"prefix_extra", and "mode" attributes.
(xop_phadd<u>bd): Likewise.
(xop_phadd<u>bq): Likewise.
(xop_phadd<u>wd): Likewise.
(xop_phadd<u>wq): Likewise.
(xop_phadd<u>dq): Likewise.
(xop_phsubbw): Likewise.
(xop_phsubwd): Likewise.
(xop_phsubdq): Likewise.
(xop_rotl<mode>3): Add "prefix" and "prefix_extra" attributes.
(xop_rotr<mode>3): Likewise.
(xop_frcz<mode>2): Likewise.
(*xop_vmfrcz<mode>2): Likewise.
(xop_vrotl<mode>3): Add "prefix" attribute. Change
"prefix_extra" to 1.
(xop_sha<mode>3): Likewise.
(xop_shl<mode>3): Likewise.
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -24897,7 +24897,10 @@
(const_int 13) (const_int 15)])))))]
"TARGET_XOP"
"vphadd<u>bw\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>bd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
@@ -24926,7 +24929,10 @@
(const_int 11) (const_int 15)]))))))]
"TARGET_XOP"
"vphadd<u>bd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>bq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -24971,7 +24977,10 @@
(parallel [(const_int 7) (const_int 15)])))))))]
"TARGET_XOP"
"vphadd<u>bq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>wd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
@@ -24988,7 +24997,10 @@
(const_int 5) (const_int 7)])))))]
"TARGET_XOP"
"vphadd<u>wd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>wq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -25013,7 +25025,10 @@
(parallel [(const_int 3) (const_int 7)]))))))]
"TARGET_XOP"
"vphadd<u>wq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phadd<u>dq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -25028,7 +25043,10 @@
(parallel [(const_int 1) (const_int 3)])))))]
"TARGET_XOP"
"vphadd<u>dq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phsubbw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
@@ -25049,7 +25067,10 @@
(const_int 13) (const_int 15)])))))]
"TARGET_XOP"
"vphsubbw\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phsubwd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
@@ -25066,7 +25087,10 @@
(const_int 5) (const_int 7)])))))]
"TARGET_XOP"
"vphsubwd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
(define_insn "xop_phsubdq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
@@ -25081,7 +25105,10 @@
(parallel [(const_int 1) (const_int 3)])))))]
"TARGET_XOP"
"vphsubdq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
+ [(set_attr "type" "sseiadd1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "mode" "TI")])
;; XOP permute instructions
(define_insn "xop_pperm"
@@ -25209,6 +25236,8 @@
"TARGET_XOP"
"vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
@@ -25224,6 +25253,8 @@
return \"vprot<ssemodesuffix>\t{%3, %1, %0|%0, %1, %3}\";
}
[(set_attr "type" "sseishft")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
@@ -25264,8 +25295,8 @@
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
;; XOP packed shift instructions.
@@ -25501,8 +25532,8 @@
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpsha<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "xop_shl<mode>3"
@@ -25520,8 +25551,8 @@
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpshl<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_expand "<insn><mode>3"
@@ -25733,6 +25764,8 @@
"TARGET_XOP"
"vfrcz<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "<MODE>")])
(define_expand "xop_vmfrcz<mode>2"
@@ -25757,6 +25790,8 @@
"TARGET_XOP"
"vfrcz<ssescalarmodesuffix>\t{%1, %0|%0, %<iptr>1}"
[(set_attr "type" "ssecvt1")
+ (set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "<MODE>")])
(define_insn "xop_maskcmp<mode>3"
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 08/10] x86: add missing "prefix" attribute to VF{,C}MULC
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
` (6 preceding siblings ...)
2023-08-03 8:12 ` [PATCH 07/10] x86: add (adjust) XOP insn attributes Jan Beulich
@ 2023-08-03 8:13 ` Jan Beulich
2023-08-04 1:57 ` Hongtao Liu
2023-08-03 8:13 ` [PATCH 09/10] x86: correct "length_immediate" in a few cases Jan Beulich
` (2 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:13 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
gcc/
* config/i386/sse.md
(<avx512>_<complexopname>_<mode><maskc_name><round_name>): Add
"prefix" attribute.
(avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>):
Likewise.
---
Talking of "prefix": Shouldn't at least V32HF and V32BF have it also
default to "evex"? (It won't matter right here, but it may matter
elsewhere.)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -6790,6 +6790,7 @@
return "v<complexopname><ssemodesuffix>\t{<round_maskc_op3>%2, %1, %0<maskc_operand3>|%0<maskc_operand3>, %1, %2<round_maskc_op3>}";
}
[(set_attr "type" "ssemul")
+ (set_attr "prefix" "evex")
(set_attr "mode" "<MODE>")])
(define_expand "avx512fp16_fmaddcsh_v8hf_maskz<round_expand_name>"
@@ -6993,6 +6994,7 @@
return "v<complexopname>sh\t{<round_scalarc_mask_op3>%2, %1, %0<mask_scalarc_operand3>|%0<mask_scalarc_operand3>, %1, %2<round_scalarc_mask_op3>}";
}
[(set_attr "type" "ssemul")
+ (set_attr "prefix" "evex")
(set_attr "mode" "V8HF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 09/10] x86: correct "length_immediate" in a few cases
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
` (7 preceding siblings ...)
2023-08-03 8:13 ` [PATCH 08/10] x86: add missing "prefix" attribute to VF{,C}MULC Jan Beulich
@ 2023-08-03 8:13 ` Jan Beulich
2023-08-04 1:57 ` Hongtao Liu
2023-08-03 8:14 ` [PATCH 10/10] x86: drop redundant "prefix_data16" attributes Jan Beulich
2023-08-04 2:01 ` [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Hongtao Liu
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:13 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
When first added explicitly in 3ddffba914b2 ("i386.md
(sse4_1_round<mode>2): Add avx512f alternative"), "*" should not have
been used for the pre-existing alternative. The attribute was plain
missing. Subsequent changes adding more alternatives then generously
extended the bogus pattern.
Apparently something similar happened to the two mmx_pblendvb_* insns.
gcc/
* config/i386/i386.md (sse4_1_round<mode>2): Make
"length_immediate" uniformly 1.
* config/i386/mmx.md (mmx_pblendvb_v8qi): Likewise.
(mmx_pblendvb_<mode>): Likewise.
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -21594,7 +21594,7 @@
vrndscale<ssemodesuffix>\t{%2, %1, %d0|%d0, %1, %2}"
[(set_attr "type" "ssecvt")
(set_attr "prefix_extra" "1,1,1,*,*")
- (set_attr "length_immediate" "*,*,*,1,1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,evex,evex")
(set_attr "isa" "noavx512f,noavx512f,noavx512f,avx512f,avx512f")
(set_attr "avx_partial_xmm_update" "false,false,true,false,true")
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3094,7 +3094,7 @@
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "*,*,1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "btver2_decode" "vector")
(set_attr "mode" "TI")])
@@ -3114,7 +3114,7 @@
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "*,*,1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "btver2_decode" "vector")
(set_attr "mode" "TI")])
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 10/10] x86: drop redundant "prefix_data16" attributes
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
` (8 preceding siblings ...)
2023-08-03 8:13 ` [PATCH 09/10] x86: correct "length_immediate" in a few cases Jan Beulich
@ 2023-08-03 8:14 ` Jan Beulich
2023-08-04 1:58 ` Hongtao Liu
2023-08-04 2:01 ` [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Hongtao Liu
10 siblings, 1 reply; 22+ messages in thread
From: Jan Beulich @ 2023-08-03 8:14 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
The attribute defaults to 1 for TI-mode insns of type sselog, sselog1,
sseiadd, sseimul, and sseishft.
In *<code>v8hi3 [smaxmin] and *<code>v16qi3 [umaxmin] also drop the
similarly stray "prefix_extra" at this occasion. These two max/min
flavors are encoded in 0f space.
gcc/
* config/i386/mmx.md (*mmx_pinsrd): Drop "prefix_data16".
(*mmx_pinsrb): Likewise.
(*mmx_pextrb): Likewise.
(*mmx_pextrb_zext): Likewise.
(mmx_pshufbv8qi3): Likewise.
(mmx_pshufbv4qi3): Likewise.
(mmx_pswapdv2si2): Likewise.
(*pinsrb): Likewise.
(*pextrb): Likewise.
(*pextrb_zext): Likewise.
* config/i386/sse.md (*sse4_1_mulv2siv2di3<mask_name>): Likewise.
(*sse2_eq<mode>3): Likewise.
(*sse2_gt<mode>3): Likewise.
(<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
(*vec_extract<mode>): Likewise.
(*vec_extract<PEXTR_MODE12:mode>_zext): Likewise.
(*vec_extractv16qi_zext): Likewise.
(ssse3_ph<plusminus_mnemonic>wv8hi3): Likewise.
(ssse3_pmaddubsw128): Likewise.
(*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Likewise.
(<ssse3_avx2>_pshufb<mode>3<mask_name>): Likewise.
(<ssse3_avx2>_psign<mode>3): Likewise.
(<ssse3_avx2>_palignr<mode>): Likewise.
(*abs<mode>2): Likewise.
(sse4_2_pcmpestr): Likewise.
(sse4_2_pcmpestri): Likewise.
(sse4_2_pcmpestrm): Likewise.
(sse4_2_pcmpestr_cconly): Likewise.
(sse4_2_pcmpistr): Likewise.
(sse4_2_pcmpistri): Likewise.
(sse4_2_pcmpistrm): Likewise.
(sse4_2_pcmpistr_cconly): Likewise.
(vgf2p8affineinvqb_<mode><mask_name>): Likewise.
(vgf2p8affineqb_<mode><mask_name>): Likewise.
(vgf2p8mulb_<mode><mask_name>): Likewise.
(*<code>v8hi3 [smaxmin]): Drop "prefix_data16" and
"prefix_extra".
(*<code>v16qi3 [umaxmin]): Likewise.
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3863,7 +3863,6 @@
}
}
[(set_attr "isa" "noavx,avx")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "type" "sselog")
(set_attr "length_immediate" "1")
@@ -3950,7 +3949,6 @@
}
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
@@ -4002,7 +4000,6 @@
%vpextrb\t{%2, %1, %k0|%k0, %1, %2}
%vpextrb\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -4017,7 +4014,6 @@
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -4035,7 +4031,6 @@
vpshufb\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "btver2_decode" "vector")
@@ -4053,7 +4048,6 @@
vpshufb\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "btver2_decode" "vector")
@@ -4191,7 +4185,6 @@
(set_attr "mmx_isa" "native,*")
(set_attr "type" "mmxcvt,sselog1")
(set_attr "prefix_extra" "1,*")
- (set_attr "prefix_data16" "*,1")
(set_attr "length_immediate" "*,1")
(set_attr "mode" "DI,TI")])
@@ -4531,7 +4524,6 @@
}
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
@@ -4575,7 +4567,6 @@
%vpextrb\t{%2, %1, %k0|%k0, %1, %2}
%vpextrb\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -4590,7 +4581,6 @@
"TARGET_SSE4_1"
"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15614,7 +15614,6 @@
vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseimul")
- (set_attr "prefix_data16" "1,1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "TI")])
@@ -16688,8 +16687,6 @@
vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix_extra" "*,1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
@@ -16772,8 +16769,6 @@
vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix_extra" "*,1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
@@ -17001,7 +16996,6 @@
vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
@@ -17063,7 +17057,6 @@
vpcmpgt<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
@@ -18819,12 +18812,6 @@
(match_test "GET_MODE_NUNITS (<MODE>mode) == 2"))
(const_string "1")
(const_string "*")))
- (set (attr "prefix_data16")
- (if_then_else
- (and (not (match_test "TARGET_AVX"))
- (match_test "GET_MODE_NUNITS (<MODE>mode) == 8"))
- (const_string "1")
- (const_string "*")))
(set (attr "prefix_extra")
(if_then_else
(ior (eq_attr "prefix" "evex")
@@ -19985,7 +19972,6 @@
%vpextr<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "*,sse4")
(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
(set (attr "prefix_extra")
(if_then_else
(eq (const_string "<MODE>mode") (const_string "V8HImode"))
@@ -20006,7 +19992,6 @@
"TARGET_SSE2"
"%vpextr<PEXTR_MODE12:ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
(set (attr "prefix_extra")
(if_then_else
(eq (const_string "<PEXTR_MODE12:MODE>mode") (const_string "V8HImode"))
@@ -20026,7 +20011,6 @@
"TARGET_SSE4_1"
"%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -21240,7 +21224,6 @@
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
@@ -21511,7 +21494,6 @@
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
@@ -21639,7 +21621,6 @@
vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseimul")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -21763,7 +21744,6 @@
vpshufb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "btver2_decode" "vector")
@@ -21830,7 +21810,6 @@
vpsign<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")])
@@ -21898,7 +21877,6 @@
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseishft")
(set_attr "atom_unit" "sishuf")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
@@ -21992,7 +21970,6 @@
"TARGET_SSSE3"
"%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<sseinsnmode>")])
@@ -24244,7 +24221,6 @@
DONE;
}
[(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,load")
@@ -24270,7 +24246,6 @@
"TARGET_SSE4_2"
"%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
[(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "length_immediate" "1")
@@ -24298,7 +24273,6 @@
"TARGET_SSE4_2"
"%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
[(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -24324,7 +24298,6 @@
%vpcmpestri\t{%6, %4, %2|%2, %4, %6}
%vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
[(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,load,none,load")
@@ -24379,7 +24352,6 @@
DONE;
}
[(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,load")
@@ -24401,7 +24373,6 @@
"TARGET_SSE4_2"
"%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
[(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -24425,7 +24396,6 @@
"TARGET_SSE4_2"
"%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
[(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -24449,7 +24419,6 @@
%vpcmpistri\t{%4, %3, %2|%2, %3, %4}
%vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
[(set_attr "type" "sselog")
- (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "memory" "none,load,none,load")
@@ -29268,7 +29237,6 @@
gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
[(set_attr "isa" "noavx,avx")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -29285,7 +29253,6 @@
gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
[(set_attr "isa" "noavx,avx")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -29301,7 +29268,6 @@
gf2p8mulb\t{%2, %0| %0, %2}
vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,avx")
- (set_attr "prefix_data16" "1,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 01/10] x86: "prefix_extra" tidying
2023-08-03 8:09 ` [PATCH 01/10] x86: "prefix_extra" tidying Jan Beulich
@ 2023-08-04 1:50 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:50 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:10 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Drop SSE5 leftovers from both its comment and its default calculation.
> A value of 2 simply cannot occur anymore. Instead extend the comment to
> mention the use of the attribute in "length_vex", clarifying why
> "prefix_extra" can actually be meaningful on VEX-encoded insns despite
> those not having any real prefixes except possibly segment overrides.
>
Ok.
> gcc/
>
> * config/i386/i386.md (prefix_extra): Correct comment. Fold
> cases yielding 2 into ones yielding 1.
> ---
> I question the 3DNow! aspect here: There's no extra prefix there. It's
> an immediate instead which "sub-divides" major opcode 0f0f.
>
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -620,13 +620,11 @@
> (const_int 0)))
>
> ;; There are also additional prefixes in 3DNOW, SSSE3.
> -;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
> -;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
> ;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
> +;; While generally inapplicable to VEX/XOP/EVEX encodings, "length_vex" uses
> +;; the attribute evaluating to zero to know that VEX2 encoding may be usable.
> (define_attr "prefix_extra" ""
> - (cond [(eq_attr "type" "ssemuladd,sse4arg")
> - (const_int 2)
> - (eq_attr "type" "sseiadd1,ssecvt1")
> + (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
> (const_int 1)
> ]
> (const_int 0)))
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 02/10] x86: "sse4arg" adjustments
2023-08-03 8:10 ` [PATCH 02/10] x86: "sse4arg" adjustments Jan Beulich
@ 2023-08-04 1:54 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:54 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:10 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Record common properties in other attributes' default calculations:
> There's always a 1-byte immediate, and they're always encoded in a VEX3-
> like manner (note that "prefix_extra" already evaluates to 1 in this
> case). The drop now (or already previously) redundant explicit
> attributes, adding "mode" ones where they were missing.
>
> Furthermore use "sse4arg" consistently for all VPCOM* insns; so far
> signed comparisons did use it, while unsigned ones used "ssecmp". Note
> that while they have (not counting the explicit or implicit immediate
> operand) they really only have 3 operands, the operator is also counted
> in those patterns. That's relevant for establishing the "memory"
> attribute's value, and at the same time benign when there are only
> register operands.
>
> Note that despite also having 4 operands, multiply-add insns aren't
> affected by this change, as they use "ssemuladd" for "type".
Ok. (I'm not quite familiar for those xop instructions encoding, you
must have better understanding than me, so just rubber-stamp the
patch.
>
> gcc/
>
> * config/i386/i386.md (length_immediate): Handle "sse4arg".
> (prefix): Likewise.
> (*xop_pcmov_<mode>): Add "mode" attribute.
> * config/i386/mmx.md (*xop_maskcmp<mode>3): Drop "prefix_data16",
> "prefix_rep", "prefix_extra", and "length_immediate" attributes.
> (*xop_maskcmp_uns<mode>3): Likewise. Switch "type" to "sse4arg".
> (*xop_pcmov_<mode>): Add "mode" attribute.
> * config/i386/sse.md (xop_pcmov_<mode><avxsizesuffix>): Add "mode"
> attribute.
> (xop_maskcmp<mode>3): Drop "prefix_data16", "prefix_rep",
> "prefix_extra", and "length_immediate" attributes.
> (xop_maskcmp_uns<mode>3): Likewise. Switch "type" to "sse4arg".
> (xop_maskcmp_uns2<mode>3): Drop "prefix_data16", "prefix_extra",
> and "length_immediate" attributes. Switch "type" to "sse4arg".
> (xop_pcom_tf<mode>3): Likewise.
> (xop_vpermil2<mode>3): Drop "length_immediate" attribute.
>
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -536,6 +536,8 @@
> (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
> bitmanip,imulx,msklog,mskmov")
> (const_int 0)
> + (eq_attr "type" "sse4arg")
> + (const_int 1)
> (eq_attr "unit" "i387,sse,mmx")
> (const_int 0)
> (eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1,
> @@ -635,6 +637,8 @@
> (const_string "vex")
> (eq_attr "mode" "XI,V16SF,V8DF")
> (const_string "evex")
> + (eq_attr "type" "sse4arg")
> + (const_string "vex")
> ]
> (const_string "orig")))
>
> @@ -23286,7 +23290,8 @@
> (match_operand:MODEF 3 "register_operand" "x")))]
> "TARGET_XOP"
> "vpcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
> - [(set_attr "type" "sse4arg")])
> + [(set_attr "type" "sse4arg")
> + (set_attr "mode" "TI")])
>
> ;; These versions of the min/max patterns are intentionally ignorant of
> ;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -2909,10 +2909,6 @@
> "TARGET_XOP"
> "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
> [(set_attr "type" "sse4arg")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_rep" "0")
> - (set_attr "prefix_extra" "2")
> - (set_attr "length_immediate" "1")
> (set_attr "mode" "TI")])
>
> (define_insn "*xop_maskcmp<mode>3"
> @@ -2923,10 +2919,6 @@
> "TARGET_XOP"
> "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
> [(set_attr "type" "sse4arg")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_rep" "0")
> - (set_attr "prefix_extra" "2")
> - (set_attr "length_immediate" "1")
> (set_attr "mode" "TI")])
>
> (define_insn "*xop_maskcmp_uns<mode>3"
> @@ -2936,11 +2928,7 @@
> (match_operand:MMXMODEI 3 "register_operand" "x")]))]
> "TARGET_XOP"
> "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
> - [(set_attr "type" "ssecmp")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_rep" "0")
> - (set_attr "prefix_extra" "2")
> - (set_attr "length_immediate" "1")
> + [(set_attr "type" "sse4arg")
> (set_attr "mode" "TI")])
>
> (define_insn "*xop_maskcmp_uns<mode>3"
> @@ -2950,11 +2938,7 @@
> (match_operand:VI_16_32 3 "register_operand" "x")]))]
> "TARGET_XOP"
> "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
> - [(set_attr "type" "ssecmp")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_rep" "0")
> - (set_attr "prefix_extra" "2")
> - (set_attr "length_immediate" "1")
> + [(set_attr "type" "sse4arg")
> (set_attr "mode" "TI")])
>
> (define_expand "vec_cmp<mode><mode>"
> @@ -3144,7 +3128,8 @@
> (match_operand:MMXMODE124 2 "register_operand" "x")))]
> "TARGET_XOP && TARGET_MMX_WITH_SSE"
> "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> - [(set_attr "type" "sse4arg")])
> + [(set_attr "type" "sse4arg")
> + (set_attr "mode" "TI")])
>
> (define_insn "*xop_pcmov_<mode>"
> [(set (match_operand:VI_16_32 0 "register_operand" "=x")
> @@ -3154,7 +3139,8 @@
> (match_operand:VI_16_32 2 "register_operand" "x")))]
> "TARGET_XOP"
> "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> - [(set_attr "type" "sse4arg")])
> + [(set_attr "type" "sse4arg")
> + (set_attr "mode" "TI")])
>
> ;; XOP permute instructions
> (define_insn "mmx_ppermv64"
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -24821,7 +24821,8 @@
> (match_operand:V_128_256 2 "nonimmediate_operand" "xm,x")))]
> "TARGET_XOP"
> "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> - [(set_attr "type" "sse4arg")])
> + [(set_attr "type" "sse4arg")
> + (set_attr "mode" "<sseinsnmode>")])
>
> ;; Recognize XOP's vpcmov from canonical (xor (and (xor t f) c) f)
> (define_split
> @@ -25739,10 +25740,6 @@
> "TARGET_XOP"
> "vpcom%Y1<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
> [(set_attr "type" "sse4arg")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_rep" "0")
> - (set_attr "prefix_extra" "2")
> - (set_attr "length_immediate" "1")
> (set_attr "mode" "TI")])
>
> (define_insn "xop_maskcmp_uns<mode>3"
> @@ -25752,11 +25749,7 @@
> (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))]
> "TARGET_XOP"
> "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
> - [(set_attr "type" "ssecmp")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_rep" "0")
> - (set_attr "prefix_extra" "2")
> - (set_attr "length_immediate" "1")
> + [(set_attr "type" "sse4arg")
> (set_attr "mode" "TI")])
>
> ;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
> @@ -25771,10 +25764,7 @@
> UNSPEC_XOP_UNSIGNED_CMP))]
> "TARGET_XOP"
> "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
> - [(set_attr "type" "ssecmp")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_extra" "2")
> - (set_attr "length_immediate" "1")
> + [(set_attr "type" "sse4arg")
> (set_attr "mode" "TI")])
>
> ;; Pcomtrue and pcomfalse support. These are useless instructions, but are
> @@ -25792,10 +25782,7 @@
> ? "vpcomtrue<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> : "vpcomfalse<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}");
> }
> - [(set_attr "type" "ssecmp")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_extra" "2")
> - (set_attr "length_immediate" "1")
> + [(set_attr "type" "sse4arg")
> (set_attr "mode" "TI")])
>
> (define_insn "xop_vpermil2<mode>3"
> @@ -25809,7 +25796,6 @@
> "TARGET_XOP"
> "vpermil2<ssemodesuffix>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}"
> [(set_attr "type" "sse4arg")
> - (set_attr "length_immediate" "1")
> (set_attr "mode" "<MODE>")])
>
> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 03/10] x86: "ssemuladd" adjustments
2023-08-03 8:10 ` [PATCH 03/10] x86: "ssemuladd" adjustments Jan Beulich
@ 2023-08-04 1:55 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:55 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:11 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> They're all VEX3- (also covering XOP) or EVEX-encoded. Express that in
> the default calculation of "prefix". FMA4 insns also all have a 1-byte
> immediate operand.
>
> Where the default calculation is not sufficient / applicable, add
> explicit "prefix" attributes. While there also add a "mode" attribute to
> fma_<complexpairopname>_<mode>_pair.
Ok.
>
> gcc/
>
> * config/i386/i386.md (isa): Move up.
> (length_immediate): Handle "fma4".
> (prefix): Handle "ssemuladd".
> * config/i386/sse.md (*fma_fmadd_<mode>): Add "prefix" attribute.
> (<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>):
> Likewise.
> (<avx512>_fmadd_<mode>_mask<round_name>): Likewise.
> (<avx512>_fmadd_<mode>_mask3<round_name>): Likewise.
> (<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>):
> Likewise.
> (<avx512>_fmsub_<mode>_mask<round_name>): Likewise.
> (<avx512>_fmsub_<mode>_mask3<round_name>): Likewise.
> (*fma_fnmadd_<mode>): Likewise.
> (<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>):
> Likewise.
> (<avx512>_fnmadd_<mode>_mask<round_name>): Likewise.
> (<avx512>_fnmadd_<mode>_mask3<round_name>): Likewise.
> (<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>):
> Likewise.
> (<avx512>_fnmsub_<mode>_mask<round_name>): Likewise.
> (<avx512>_fnmsub_<mode>_mask3<round_name>): Likewise.
> (<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>):
> Likewise.
> (<avx512>_fmaddsub_<mode>_mask<round_name>): Likewise.
> (<avx512>_fmaddsub_<mode>_mask3<round_name>): Likewise.
> (<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>):
> Likewise.
> (<avx512>_fmsubadd_<mode>_mask<round_name>): Likewise.
> (<avx512>_fmsubadd_<mode>_mask3<round_name>): Likewise.
> (*fmai_fmadd_<mode>): Likewise.
> (*fmai_fmsub_<mode>): Likewise.
> (*fmai_fnmadd_<mode><round_name>): Likewise.
> (*fmai_fnmsub_<mode><round_name>): Likewise.
> (avx512f_vmfmadd_<mode>_mask<round_name>): Likewise.
> (avx512f_vmfmadd_<mode>_mask3<round_name>): Likewise.
> (avx512f_vmfmadd_<mode>_maskz_1<round_name>): Likewise.
> (*avx512f_vmfmsub_<mode>_mask<round_name>): Likewise.
> (avx512f_vmfmsub_<mode>_mask3<round_name>): Likewise.
> (*avx512f_vmfmsub_<mode>_maskz_1<round_name>): Likewise.
> (avx512f_vmfnmadd_<mode>_mask<round_name>): Likewise.
> (avx512f_vmfnmadd_<mode>_mask3<round_name>): Likewise.
> (avx512f_vmfnmadd_<mode>_maskz_1<round_name>): Likewise.
> (*avx512f_vmfnmsub_<mode>_mask<round_name>): Likewise.
> (*avx512f_vmfnmsub_<mode>_mask3<round_name>): Likewise.
> (*avx512f_vmfnmsub_<mode>_maskz_1<round_name>): Likewise.
> (*fma4i_vmfmadd_<mode>): Likewise.
> (*fma4i_vmfmsub_<mode>): Likewise.
> (*fma4i_vmfnmadd_<mode>): Likewise.
> (*fma4i_vmfnmsub_<mode>): Likewise.
> (fma_<complexopname>_<mode><sdc_maskz_name><round_name>): Likewise.
> (<avx512>_<complexopname>_<mode>_mask<round_name>): Likewise.
> (avx512fp16_fma_<complexopname>sh_v8hf<mask_scalarcz_name><round_scalarcz_name>):
> Likewise.
> (avx512fp16_<complexopname>sh_v8hf_mask<round_name>): Likewise.
> (xop_p<macs><ssemodesuffix><ssemodesuffix>): Likewise.
> (xop_p<macs>dql): Likewise.
> (xop_p<macs>dqh): Likewise.
> (xop_p<macs>wd): Likewise.
> (xop_p<madcs>wd): Likewise.
> (fma_<complexpairopname>_<mode>_pair): Likewise. Add "mode" attribute.
>
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -531,12 +531,23 @@
> (const_string "unknown")]
> (const_string "integer")))
>
> +;; Used to control the "enabled" attribute on a per-instruction basis.
> +(define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx,
> + x64_avx,x64_avx512bw,x64_avx512dq,aes,
> + sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
> + avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
> + avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
> + avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma,
> + avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl"
> + (const_string "base"))
> +
> ;; The (bounding maximum) length of an instruction immediate.
> (define_attr "length_immediate" ""
> (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
> bitmanip,imulx,msklog,mskmov")
> (const_int 0)
> - (eq_attr "type" "sse4arg")
> + (ior (eq_attr "type" "sse4arg")
> + (eq_attr "isa" "fma4"))
> (const_int 1)
> (eq_attr "unit" "i387,sse,mmx")
> (const_int 0)
> @@ -637,6 +648,10 @@
> (const_string "vex")
> (eq_attr "mode" "XI,V16SF,V8DF")
> (const_string "evex")
> + (eq_attr "type" "ssemuladd")
> + (if_then_else (eq_attr "isa" "fma4")
> + (const_string "vex")
> + (const_string "maybe_evex"))
> (eq_attr "type" "sse4arg")
> (const_string "vex")
> ]
> @@ -842,16 +857,6 @@
> ;; Define attribute to indicate unaligned ssemov insns
> (define_attr "movu" "0,1" (const_string "0"))
>
> -;; Used to control the "enabled" attribute on a per-instruction basis.
> -(define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx,
> - x64_avx,x64_avx512bw,x64_avx512dq,aes,
> - sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
> - avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
> - avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
> - avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma,
> - avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl"
> - (const_string "base"))
> -
> ;; Define instruction set of MMX instructions
> (define_attr "mmx_isa" "base,native,sse,sse_noavx,avx"
> (const_string "base"))
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -5422,6 +5422,7 @@
> vfmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
> vfmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "cond_fma<mode>"
> @@ -5461,6 +5462,7 @@
> vfmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
> vfmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "<avx512>_fmadd_<mode>_mask3<round_name>"
> @@ -5475,6 +5477,7 @@
> "TARGET_AVX512F"
> "vfmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fma_fmsub_<mode>"
> @@ -5522,6 +5525,7 @@
> vfmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
> vfmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "cond_fms<mode>"
> @@ -5563,6 +5567,7 @@
> vfmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
> vfmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "<avx512>_fmsub_<mode>_mask3<round_name>"
> @@ -5578,6 +5583,7 @@
> "TARGET_AVX512F && <round_mode512bit_condition>"
> "vfmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fma_fnmadd_<mode>"
> @@ -5625,6 +5631,7 @@
> vfnmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
> vfnmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "cond_fnma<mode>"
> @@ -5666,6 +5673,7 @@
> vfnmadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
> vfnmadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "<avx512>_fnmadd_<mode>_mask3<round_name>"
> @@ -5681,6 +5689,7 @@
> "TARGET_AVX512F && <round_mode512bit_condition>"
> "vfnmadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fma_fnmsub_<mode>"
> @@ -5730,6 +5739,7 @@
> vfnmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
> vfnmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "cond_fnms<mode>"
> @@ -5773,6 +5783,7 @@
> vfnmsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
> vfnmsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "<avx512>_fnmsub_<mode>_mask3<round_name>"
> @@ -5789,6 +5800,7 @@
> "TARGET_AVX512F"
> "vfnmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> ;; FMA parallel floating point multiply addsub and subadd operations.
> @@ -5889,6 +5901,7 @@
> vfmaddsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
> vfmaddsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "<avx512>_fmaddsub_<mode>_mask<round_name>"
> @@ -5906,6 +5919,7 @@
> vfmaddsub132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
> vfmaddsub213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "<avx512>_fmaddsub_<mode>_mask3<round_name>"
> @@ -5921,6 +5935,7 @@
> "TARGET_AVX512F"
> "vfmaddsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fma_fmsubadd_<mode>"
> @@ -5956,6 +5971,7 @@
> vfmsubadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>}
> vfmsubadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "<avx512>_fmsubadd_<mode>_mask<round_name>"
> @@ -5974,6 +5990,7 @@
> vfmsubadd132<ssemodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %3, %2<round_op5>}
> vfmsubadd213<ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "<avx512>_fmsubadd_<mode>_mask3<round_name>"
> @@ -5990,6 +6007,7 @@
> "TARGET_AVX512F"
> "vfmsubadd231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> ;; FMA3 floating point scalar intrinsics. These merge result with
> @@ -6057,6 +6075,7 @@
> vfmadd132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
> vfmadd213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fmai_fmsub_<mode>"
> @@ -6074,6 +6093,7 @@
> vfmsub132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
> vfmsub213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fmai_fnmadd_<mode><round_name>"
> @@ -6091,6 +6111,7 @@
> vfnmadd132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
> vfnmadd213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fmai_fnmsub_<mode><round_name>"
> @@ -6109,6 +6130,7 @@
> vfnmsub132<ssescalarmodesuffix>\t{<round_op4>%2, %3, %0|%0, %<iptr>3, %<iptr>2<round_op4>}
> vfnmsub213<ssescalarmodesuffix>\t{<round_op4>%3, %2, %0|%0, %<iptr>2, %<iptr>3<round_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "avx512f_vmfmadd_<mode>_mask<round_name>"
> @@ -6128,6 +6150,7 @@
> vfmadd132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
> vfmadd213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "avx512f_vmfmadd_<mode>_mask3<round_name>"
> @@ -6145,6 +6168,7 @@
> "TARGET_AVX512F"
> "vfmadd231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "avx512f_vmfmadd_<mode>_maskz<round_expand_name>"
> @@ -6178,6 +6202,7 @@
> vfmadd132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
> vfmadd213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*avx512f_vmfmsub_<mode>_mask<round_name>"
> @@ -6198,6 +6223,7 @@
> vfmsub132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
> vfmsub213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "avx512f_vmfmsub_<mode>_mask3<round_name>"
> @@ -6216,6 +6242,7 @@
> "TARGET_AVX512F"
> "vfmsub231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*avx512f_vmfmsub_<mode>_maskz_1<round_name>"
> @@ -6236,6 +6263,7 @@
> vfmsub132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
> vfmsub213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "avx512f_vmfnmadd_<mode>_mask<round_name>"
> @@ -6256,6 +6284,7 @@
> vfnmadd132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
> vfnmadd213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "avx512f_vmfnmadd_<mode>_mask3<round_name>"
> @@ -6274,6 +6303,7 @@
> "TARGET_AVX512F"
> "vfnmadd231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "avx512f_vmfnmadd_<mode>_maskz<round_expand_name>"
> @@ -6308,6 +6338,7 @@
> vfnmadd132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
> vfnmadd213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*avx512f_vmfnmsub_<mode>_mask<round_name>"
> @@ -6329,6 +6360,7 @@
> vfnmsub132<ssescalarmodesuffix>\t{<round_op5>%2, %3, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}
> vfnmsub213<ssescalarmodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %<iptr>2, %<iptr>3<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*avx512f_vmfnmsub_<mode>_mask3<round_name>"
> @@ -6348,6 +6380,7 @@
> "TARGET_AVX512F"
> "vfnmsub231<ssescalarmodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %<iptr>3, %<iptr>2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*avx512f_vmfnmsub_<mode>_maskz_1<round_name>"
> @@ -6369,6 +6402,7 @@
> vfnmsub132<ssescalarmodesuffix>\t{<round_op6>%2, %3, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>3, %<iptr>2<round_op6>}
> vfnmsub213<ssescalarmodesuffix>\t{<round_op6>%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %<iptr>2, %<iptr>3<round_op6>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> ;; FMA4 floating point scalar intrinsics. These write the
> @@ -6398,6 +6432,7 @@
> "TARGET_FMA4"
> "vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fma4i_vmfmsub_<mode>"
> @@ -6413,6 +6448,7 @@
> "TARGET_FMA4"
> "vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fma4i_vmfnmadd_<mode>"
> @@ -6428,6 +6464,7 @@
> "TARGET_FMA4"
> "vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "*fma4i_vmfnmsub_<mode>"
> @@ -6444,6 +6481,7 @@
> "TARGET_FMA4"
> "vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %<iptr>2, %<iptr>3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "<MODE>")])
>
> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
> @@ -6591,6 +6629,7 @@
> "TARGET_AVX512FP16 && <sdc_mask_mode512bit_condition> && <round_mode512bit_condition>"
> "v<complexopname><ssemodesuffix>\t{<round_sdc_mask_op4>%2, %1, %0<sdc_mask_op4>|%0<sdc_mask_op4>, %1, %2<round_sdc_mask_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn_and_split "fma_<mode>_fadd_fmul"
> @@ -6654,7 +6693,9 @@
> UNSPEC_COMPLEX_F_C_MA_PAIR))]
> "TARGET_AVX512FP16"
> "v<complexpairopname>ph\t{%2, %1, %0|%0, %1, %2}"
> - [(set_attr "type" "ssemuladd")])
> + [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> + (set_attr "mode" "<MODE>")])
>
> (define_insn_and_split "fma_<mode>_fmaddc_bcst"
> [(set (match_operand:VF_AVX512FP16VL 0 "register_operand")
> @@ -6726,6 +6767,7 @@
> "TARGET_AVX512FP16 && <round_mode512bit_condition>"
> "v<complexopname><ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "cmul<conj_op><mode>3"
> @@ -6913,6 +6955,7 @@
> "TARGET_AVX512FP16"
> "v<complexopname>sh\t{<round_scalarcz_mask_op4>%2, %1, %0<mask_scalarcz_operand4>|%0<mask_scalarcz_operand4>, %1, %2<round_scalarcz_mask_op4>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "V8HF")])
>
> (define_insn "avx512fp16_<complexopname>sh_v8hf_mask<round_name>"
> @@ -6932,6 +6975,7 @@
> "TARGET_AVX512FP16"
> "v<complexopname>sh\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "V8HF")])
>
> (define_insn "avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>"
> @@ -24721,6 +24765,7 @@
> "TARGET_XOP"
> "vp<macs><ssemodesuffix><ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "TI")])
>
> (define_insn "xop_p<macs>dql"
> @@ -24739,6 +24784,7 @@
> "TARGET_XOP"
> "vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "TI")])
>
> (define_insn "xop_p<macs>dqh"
> @@ -24757,6 +24803,7 @@
> "TARGET_XOP"
> "vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "TI")])
>
> ;; XOP parallel integer multiply/add instructions for the intrinisics
> @@ -24778,6 +24825,7 @@
> "TARGET_XOP"
> "vp<macs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "TI")])
>
> (define_insn "xop_p<madcs>wd"
> @@ -24810,6 +24858,7 @@
> "TARGET_XOP"
> "vp<madcs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
> [(set_attr "type" "ssemuladd")
> + (set_attr "prefix" "vex")
> (set_attr "mode" "TI")])
>
> ;; XOP parallel XMM conditional moves
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 04/10] x86: "prefix_extra" can't really be "2"
2023-08-03 8:11 ` [PATCH 04/10] x86: "prefix_extra" can't really be "2" Jan Beulich
@ 2023-08-04 1:55 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:55 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:11 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> In the three remaining instances separate "prefix_0f" and "prefix_rep"
> are what is wanted instead.
Ok.
>
> gcc/
>
> * config/i386/i386.md (rd<fsgs>base<mode>): Add "prefix_0f" and
> "prefix_rep". Drop "prefix_extra".
> (wr<fsgs>base<mode>): Likewise.
> (ptwrite<mode>): Likewise.
>
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -25914,7 +25914,8 @@
> "TARGET_64BIT && TARGET_FSGSBASE"
> "rd<fsgs>base\t%0"
> [(set_attr "type" "other")
> - (set_attr "prefix_extra" "2")])
> + (set_attr "prefix_0f" "1")
> + (set_attr "prefix_rep" "1")])
>
> (define_insn "wr<fsgs>base<mode>"
> [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
> @@ -25922,7 +25923,8 @@
> "TARGET_64BIT && TARGET_FSGSBASE"
> "wr<fsgs>base\t%0"
> [(set_attr "type" "other")
> - (set_attr "prefix_extra" "2")])
> + (set_attr "prefix_0f" "1")
> + (set_attr "prefix_rep" "1")])
>
> (define_insn "ptwrite<mode>"
> [(unspec_volatile [(match_operand:SWI48 0 "nonimmediate_operand" "rm")]
> @@ -25930,7 +25932,8 @@
> "TARGET_PTWRITE"
> "ptwrite\t%0"
> [(set_attr "type" "other")
> - (set_attr "prefix_extra" "2")])
> + (set_attr "prefix_0f" "1")
> + (set_attr "prefix_rep" "1")])
>
> (define_insn "@rdrand<mode>"
> [(set (match_operand:SWI248 0 "register_operand" "=r")
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 05/10] x86: replace/correct bogus "prefix_extra"
2023-08-03 8:12 ` [PATCH 05/10] x86: replace/correct bogus "prefix_extra" Jan Beulich
@ 2023-08-04 1:56 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:56 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:14 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> In the rdrand and rdseed cases "prefix_0f" is meant instead. For
> mmx_floatv2siv2sf2 1 is correct only for the first alternative. For
> the integer min/max cases 1 uniformly applies to legacy and VEX
> encodings (the UB and SW variants are dealt with separately anyway).
> Same for {,V}MOVNTDQA.
>
> Unlike {,V}PEXTRW, which has two encoding forms, {,V}PINSRW only has
> a single form in 0f space. (In *vec_extract<mode> note that the
> dropped part if the condition also referenced non-existing alternative
> 2.)
>
> Of the integer compare insns, only the 64-bit element forms are encoded
> in 0f38 space.
Ok.
>
> gcc/
>
> * config/i386/i386.md (@rdrand<mode>): Add "prefix_0f". Drop
> "prefix_extra".
> (@rdseed<mode>): Likewise.
> * config/i386/mmx.md (<code><mode>3 [smaxmin and umaxmin cases]):
> Adjust "prefix_extra".
> * config/i386/sse.md (@vec_set<mode>_0): Likewise.
> (*sse4_1_<code><mode>3<mask_name>): Likewise.
> (*avx2_eq<mode>3): Likewise.
> (avx2_gt<mode>3): Likewise.
> (<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
> (*vec_extract<mode>): Likewise.
> (<vi8_sse4_1_avx2_avx512>_movntdqa): Likewise.
>
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -25943,7 +25943,7 @@
> "TARGET_RDRND"
> "rdrand\t%0"
> [(set_attr "type" "other")
> - (set_attr "prefix_extra" "1")])
> + (set_attr "prefix_0f" "1")])
>
> (define_insn "@rdseed<mode>"
> [(set (match_operand:SWI248 0 "register_operand" "=r")
> @@ -25953,7 +25953,7 @@
> "TARGET_RDSEED"
> "rdseed\t%0"
> [(set_attr "type" "other")
> - (set_attr "prefix_extra" "1")])
> + (set_attr "prefix_0f" "1")])
>
> (define_expand "pause"
> [(set (match_dup 0)
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -2483,7 +2483,7 @@
> vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "sseiadd")
> - (set_attr "prefix_extra" "1,1,*")
> + (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,orig,vex")
> (set_attr "mode" "TI")])
>
> @@ -2532,7 +2532,7 @@
> vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "sseiadd")
> - (set_attr "prefix_extra" "1,1,*")
> + (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,orig,vex")
> (set_attr "mode" "TI")])
>
> @@ -2561,7 +2561,7 @@
> vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "sseiadd")
> - (set_attr "prefix_extra" "1,1,*")
> + (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,orig,vex")
> (set_attr "mode" "TI")])
>
> @@ -2623,7 +2623,7 @@
> vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "sseiadd")
> - (set_attr "prefix_extra" "1,1,*")
> + (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,orig,vex")
> (set_attr "mode" "TI")])
>
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -11064,7 +11064,7 @@
> (const_string "1")
> (const_string "*")))
> (set (attr "prefix_extra")
> - (if_then_else (eq_attr "alternative" "5,6,7,8,9")
> + (if_then_else (eq_attr "alternative" "5,6,9")
> (const_string "1")
> (const_string "*")))
> (set (attr "length_immediate")
> @@ -16779,7 +16779,7 @@
> vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "sseiadd")
> - (set_attr "prefix_extra" "1,1,*")
> + (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,orig,vex")
> (set_attr "mode" "TI")])
>
> @@ -16813,7 +16813,10 @@
> "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "ssecmp")
> - (set_attr "prefix_extra" "1")
> + (set (attr "prefix_extra")
> + (if_then_else (eq (const_string "<MODE>mode") (const_string "V4DImode"))
> + (const_string "1")
> + (const_string "*")))
> (set_attr "prefix" "vex")
> (set_attr "mode" "OI")])
>
> @@ -17048,7 +17051,10 @@
> "TARGET_AVX2"
> "vpcmpgt<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "ssecmp")
> - (set_attr "prefix_extra" "1")
> + (set (attr "prefix_extra")
> + (if_then_else (eq (const_string "<MODE>mode") (const_string "V4DImode"))
> + (const_string "1")
> + (const_string "*")))
> (set_attr "prefix" "vex")
> (set_attr "mode" "OI")])
>
> @@ -18843,7 +18849,7 @@
> (const_string "*")))
> (set (attr "prefix_extra")
> (if_then_else
> - (and (not (match_test "TARGET_AVX"))
> + (ior (eq_attr "prefix" "evex")
> (match_test "GET_MODE_NUNITS (<MODE>mode) == 8"))
> (const_string "*")
> (const_string "1")))
> @@ -20004,8 +20010,7 @@
> (set_attr "prefix_data16" "1")
> (set (attr "prefix_extra")
> (if_then_else
> - (and (eq_attr "alternative" "0,2")
> - (eq (const_string "<MODE>mode") (const_string "V8HImode")))
> + (eq (const_string "<MODE>mode") (const_string "V8HImode"))
> (const_string "*")
> (const_string "1")))
> (set_attr "length_immediate" "1")
> @@ -22349,7 +22354,7 @@
> "%vmovntdqa\t{%1, %0|%0, %1}"
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "ssemov")
> - (set_attr "prefix_extra" "1,1,*")
> + (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,orig,maybe_evex")
> (set_attr "mode" "<sseinsnmode>")])
>
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 06/10] x86: drop stray "prefix_extra"
2023-08-03 8:12 ` [PATCH 06/10] x86: drop stray "prefix_extra" Jan Beulich
@ 2023-08-04 1:56 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:56 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:16 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> While the attribute is relevant for legacy- and VEX-encoded insns, it is
> of no relevance for EVEX-encoded ones.
>
> While there in <mask_codefor>avx512dq_broadcast<mode><mask_name>_1 add
> the missing "length_immediate".
Ok.
>
> gcc/
>
> * config/i386/sse.md
> (*<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Drop
> "prefix_extra".
> (avx512dq_vextract<shuffletype>64x2_1_mask): Likewise.
> (*avx512dq_vextract<shuffletype>64x2_1): Likewise.
> (avx512f_vextract<shuffletype>32x4_1_mask): Likewise.
> (*avx512f_vextract<shuffletype>32x4_1): Likewise.
> (vec_extract_lo_<mode>_mask [AVX512 forms]): Likewise.
> (vec_extract_lo_<mode> [AVX512 forms]): Likewise.
> (vec_extract_hi_<mode>_mask [AVX512 forms]): Likewise.
> (vec_extract_hi_<mode> [AVX512 forms]): Likewise.
> (@vec_extract_lo_<mode> [AVX512 forms]): Likewise.
> (@vec_extract_hi_<mode> [AVX512 forms]): Likewise.
> (vec_extract_lo_v64qi): Likewise.
> (vec_extract_hi_v64qi): Likewise.
> (*vec_widen_umult_even_v16si<mask_name>): Likewise.
> (*vec_widen_smult_even_v16si<mask_name>): Likewise.
> (*avx512f_<code><mode>3<mask_name>): Likewise.
> (*vec_extractv4ti): Likewise.
> (avx512bw_<code>v32qiv32hi2<mask_name>): Likewise.
> (<mask_codefor>avx512dq_broadcast<mode><mask_name>_1): Likewise.
> Add "length_immediate".
>
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -4030,7 +4030,6 @@
> vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
> vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
> [(set_attr "type" "ssecmp")
> - (set_attr "prefix_extra" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> @@ -4128,7 +4127,6 @@
> vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
> vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
> [(set_attr "type" "ssecmp")
> - (set_attr "prefix_extra" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> @@ -11487,7 +11485,6 @@
> return "vextract<shuffletype>64x2\t{%2, %1, %0%{%5%}%N4|%0%{%5%}%N4, %1, %2}";
> }
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -11506,7 +11503,6 @@
> return "vextract<shuffletype>64x2\t{%2, %1, %0|%0, %1, %2}";
> }
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -11554,7 +11550,6 @@
> return "vextract<shuffletype>32x4\t{%2, %1, %0%{%7%}%N6|%0%{%7%}%N6, %1, %2}";
> }
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -11577,7 +11572,6 @@
> return "vextract<shuffletype>32x4\t{%2, %1, %0|%0, %1, %2}";
> }
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -11671,7 +11665,6 @@
> && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
> "vextract<shuffletype>64x4\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,store")
> (set_attr "prefix" "evex")
> @@ -11691,7 +11684,6 @@
> return "#";
> }
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,store,load")
> (set_attr "prefix" "evex")
> @@ -11710,7 +11702,6 @@
> && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
> "vextract<shuffletype>64x4\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -11724,7 +11715,6 @@
> "TARGET_AVX512F"
> "vextract<shuffletype>64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -11744,7 +11734,6 @@
> && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
> "vextract<shuffletype>32x8\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -11762,7 +11751,6 @@
> vextract<shuffletype>32x8\t{$0x1, %1, %0|%0, %1, 0x1}
> vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "isa" "avx512dq,noavx512dq")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> @@ -11850,7 +11838,6 @@
> && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
> "vextract<shuffletype>32x8\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,store")
> (set_attr "prefix" "evex")
> @@ -11880,7 +11867,6 @@
> return "#";
> }
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,load,store")
> (set_attr "prefix" "evex")
> @@ -11923,7 +11909,6 @@
> && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
> "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,store")
> (set_attr "prefix" "evex")
> @@ -11961,7 +11946,6 @@
> && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
> "vextract<shuffletype>64x2\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "vex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -12013,7 +11997,6 @@
> && (!MEM_P (operands[0]) || rtx_equal_p (operands[0], operands[2]))"
> "vextract<shuffletype>32x4\t{$0x0, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x0}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -12102,7 +12085,6 @@
> operands[1] = gen_lowpart (<ssehalfvecmode>mode, operands[1]);
> }
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,load,store")
> (set_attr "prefix" "evex")
> @@ -12123,7 +12105,6 @@
> "TARGET_AVX512F"
> "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "XI")])
> @@ -12204,7 +12185,6 @@
> operands[1] = gen_lowpart (V32QImode, operands[1]);
> }
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,load,store")
> (set_attr "prefix" "evex")
> @@ -12233,7 +12213,6 @@
> "TARGET_AVX512F"
> "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "XI")])
> @@ -15446,7 +15425,6 @@
> "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "type" "sseimul")
> - (set_attr "prefix_extra" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "XI")])
>
> @@ -15562,7 +15540,6 @@
> "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "type" "sseimul")
> - (set_attr "prefix_extra" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "XI")])
>
> @@ -16585,7 +16562,6 @@
> "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "type" "sseiadd")
> - (set_attr "prefix_extra" "1")
> (set_attr "prefix" "maybe_evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> @@ -20322,7 +20298,6 @@
> "TARGET_AVX512F"
> "vextracti32x4\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sselog")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "XI")])
> @@ -21893,7 +21868,6 @@
> }
> [(set_attr "type" "sseishft")
> (set_attr "atom_unit" "sishuf")
> - (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -22666,7 +22640,6 @@
> "TARGET_AVX512BW"
> "vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
> [(set_attr "type" "ssemov")
> - (set_attr "prefix_extra" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "XI")])
>
> @@ -26796,7 +26769,7 @@
> vshuf<shuffletype>32x4\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}
> vbroadcast<shuffletype>32x8\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
> [(set_attr "type" "ssemov")
> - (set_attr "prefix_extra" "1")
> + (set_attr "length_immediate" "1,*")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> @@ -26813,7 +26786,7 @@
> vshuf<shuffletype>64x2\t{$0x0, %<xtg_mode>1, %<xtg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<xtg_mode>1, %<xtg_mode>1, 0x0}
> vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
> [(set_attr "type" "ssemov")
> - (set_attr "prefix_extra" "1")
> + (set_attr "length_immediate" "1")
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 07/10] x86: add (adjust) XOP insn attributes
2023-08-03 8:12 ` [PATCH 07/10] x86: add (adjust) XOP insn attributes Jan Beulich
@ 2023-08-04 1:57 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:57 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:14 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Many were lacking "prefix" and "prefix_extra", some had a bogus value of
> 2 for "prefix_extra" (presumably inherited from their SSE5 counterparts,
> which are long gone) and a meaningless "prefix_data16" one. Where
> missing, "mode" attributes are also added. (Note that "sse4arg" and
> "ssemuladd" ones don't need further adjustment in this regard.)
Ok.
>
> gcc/
>
> * config/i386/sse.md (xop_phadd<u>bw): Add "prefix",
> "prefix_extra", and "mode" attributes.
> (xop_phadd<u>bd): Likewise.
> (xop_phadd<u>bq): Likewise.
> (xop_phadd<u>wd): Likewise.
> (xop_phadd<u>wq): Likewise.
> (xop_phadd<u>dq): Likewise.
> (xop_phsubbw): Likewise.
> (xop_phsubwd): Likewise.
> (xop_phsubdq): Likewise.
> (xop_rotl<mode>3): Add "prefix" and "prefix_extra" attributes.
> (xop_rotr<mode>3): Likewise.
> (xop_frcz<mode>2): Likewise.
> (*xop_vmfrcz<mode>2): Likewise.
> (xop_vrotl<mode>3): Add "prefix" attribute. Change
> "prefix_extra" to 1.
> (xop_sha<mode>3): Likewise.
> (xop_shl<mode>3): Likewise.
>
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -24897,7 +24897,10 @@
> (const_int 13) (const_int 15)])))))]
> "TARGET_XOP"
> "vphadd<u>bw\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> (define_insn "xop_phadd<u>bd"
> [(set (match_operand:V4SI 0 "register_operand" "=x")
> @@ -24926,7 +24929,10 @@
> (const_int 11) (const_int 15)]))))))]
> "TARGET_XOP"
> "vphadd<u>bd\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> (define_insn "xop_phadd<u>bq"
> [(set (match_operand:V2DI 0 "register_operand" "=x")
> @@ -24971,7 +24977,10 @@
> (parallel [(const_int 7) (const_int 15)])))))))]
> "TARGET_XOP"
> "vphadd<u>bq\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> (define_insn "xop_phadd<u>wd"
> [(set (match_operand:V4SI 0 "register_operand" "=x")
> @@ -24988,7 +24997,10 @@
> (const_int 5) (const_int 7)])))))]
> "TARGET_XOP"
> "vphadd<u>wd\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> (define_insn "xop_phadd<u>wq"
> [(set (match_operand:V2DI 0 "register_operand" "=x")
> @@ -25013,7 +25025,10 @@
> (parallel [(const_int 3) (const_int 7)]))))))]
> "TARGET_XOP"
> "vphadd<u>wq\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> (define_insn "xop_phadd<u>dq"
> [(set (match_operand:V2DI 0 "register_operand" "=x")
> @@ -25028,7 +25043,10 @@
> (parallel [(const_int 1) (const_int 3)])))))]
> "TARGET_XOP"
> "vphadd<u>dq\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> (define_insn "xop_phsubbw"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> @@ -25049,7 +25067,10 @@
> (const_int 13) (const_int 15)])))))]
> "TARGET_XOP"
> "vphsubbw\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> (define_insn "xop_phsubwd"
> [(set (match_operand:V4SI 0 "register_operand" "=x")
> @@ -25066,7 +25087,10 @@
> (const_int 5) (const_int 7)])))))]
> "TARGET_XOP"
> "vphsubwd\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> (define_insn "xop_phsubdq"
> [(set (match_operand:V2DI 0 "register_operand" "=x")
> @@ -25081,7 +25105,10 @@
> (parallel [(const_int 1) (const_int 3)])))))]
> "TARGET_XOP"
> "vphsubdq\t{%1, %0|%0, %1}"
> - [(set_attr "type" "sseiadd1")])
> + [(set_attr "type" "sseiadd1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> + (set_attr "mode" "TI")])
>
> ;; XOP permute instructions
> (define_insn "xop_pperm"
> @@ -25209,6 +25236,8 @@
> "TARGET_XOP"
> "vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sseishft")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "mode" "TI")])
>
> @@ -25224,6 +25253,8 @@
> return \"vprot<ssemodesuffix>\t{%3, %1, %0|%0, %1, %3}\";
> }
> [(set_attr "type" "sseishft")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "mode" "TI")])
>
> @@ -25264,8 +25295,8 @@
> "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sseishft")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_extra" "2")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> (set_attr "mode" "TI")])
>
> ;; XOP packed shift instructions.
> @@ -25501,8 +25532,8 @@
> "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpsha<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sseishft")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_extra" "2")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> (set_attr "mode" "TI")])
>
> (define_insn "xop_shl<mode>3"
> @@ -25520,8 +25551,8 @@
> "TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpshl<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sseishft")
> - (set_attr "prefix_data16" "0")
> - (set_attr "prefix_extra" "2")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> (set_attr "mode" "TI")])
>
> (define_expand "<insn><mode>3"
> @@ -25733,6 +25764,8 @@
> "TARGET_XOP"
> "vfrcz<ssemodesuffix>\t{%1, %0|%0, %1}"
> [(set_attr "type" "ssecvt1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "xop_vmfrcz<mode>2"
> @@ -25757,6 +25790,8 @@
> "TARGET_XOP"
> "vfrcz<ssescalarmodesuffix>\t{%1, %0|%0, %<iptr>1}"
> [(set_attr "type" "ssecvt1")
> + (set_attr "prefix" "vex")
> + (set_attr "prefix_extra" "1")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "xop_maskcmp<mode>3"
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 08/10] x86: add missing "prefix" attribute to VF{,C}MULC
2023-08-03 8:13 ` [PATCH 08/10] x86: add missing "prefix" attribute to VF{,C}MULC Jan Beulich
@ 2023-08-04 1:57 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:57 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:16 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> gcc/
>
> * config/i386/sse.md
> (<avx512>_<complexopname>_<mode><maskc_name><round_name>): Add
> "prefix" attribute.
> (avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>):
> Likewise.
Ok.
> ---
> Talking of "prefix": Shouldn't at least V32HF and V32BF have it also
> default to "evex"? (It won't matter right here, but it may matter
> elsewhere.)
>
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -6790,6 +6790,7 @@
> return "v<complexopname><ssemodesuffix>\t{<round_maskc_op3>%2, %1, %0<maskc_operand3>|%0<maskc_operand3>, %1, %2<round_maskc_op3>}";
> }
> [(set_attr "type" "ssemul")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "<MODE>")])
>
> (define_expand "avx512fp16_fmaddcsh_v8hf_maskz<round_expand_name>"
> @@ -6993,6 +6994,7 @@
> return "v<complexopname>sh\t{<round_scalarc_mask_op3>%2, %1, %0<mask_scalarc_operand3>|%0<mask_scalarc_operand3>, %1, %2<round_scalarc_mask_op3>}";
> }
> [(set_attr "type" "ssemul")
> + (set_attr "prefix" "evex")
> (set_attr "mode" "V8HF")])
>
> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 09/10] x86: correct "length_immediate" in a few cases
2023-08-03 8:13 ` [PATCH 09/10] x86: correct "length_immediate" in a few cases Jan Beulich
@ 2023-08-04 1:57 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:57 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:14 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> When first added explicitly in 3ddffba914b2 ("i386.md
> (sse4_1_round<mode>2): Add avx512f alternative"), "*" should not have
> been used for the pre-existing alternative. The attribute was plain
> missing. Subsequent changes adding more alternatives then generously
> extended the bogus pattern.
>
> Apparently something similar happened to the two mmx_pblendvb_* insns.
Ok.
>
> gcc/
>
> * config/i386/i386.md (sse4_1_round<mode>2): Make
> "length_immediate" uniformly 1.
> * config/i386/mmx.md (mmx_pblendvb_v8qi): Likewise.
> (mmx_pblendvb_<mode>): Likewise.
>
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -21594,7 +21594,7 @@
> vrndscale<ssemodesuffix>\t{%2, %1, %d0|%d0, %1, %2}"
> [(set_attr "type" "ssecvt")
> (set_attr "prefix_extra" "1,1,1,*,*")
> - (set_attr "length_immediate" "*,*,*,1,1")
> + (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,evex,evex")
> (set_attr "isa" "noavx512f,noavx512f,noavx512f,avx512f,avx512f")
> (set_attr "avx_partial_xmm_update" "false,false,true,false,true")
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -3094,7 +3094,7 @@
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "ssemov")
> (set_attr "prefix_extra" "1")
> - (set_attr "length_immediate" "*,*,1")
> + (set_attr "length_immediate" "1")
> (set_attr "prefix" "orig,orig,vex")
> (set_attr "btver2_decode" "vector")
> (set_attr "mode" "TI")])
> @@ -3114,7 +3114,7 @@
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "ssemov")
> (set_attr "prefix_extra" "1")
> - (set_attr "length_immediate" "*,*,1")
> + (set_attr "length_immediate" "1")
> (set_attr "prefix" "orig,orig,vex")
> (set_attr "btver2_decode" "vector")
> (set_attr "mode" "TI")])
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 10/10] x86: drop redundant "prefix_data16" attributes
2023-08-03 8:14 ` [PATCH 10/10] x86: drop redundant "prefix_data16" attributes Jan Beulich
@ 2023-08-04 1:58 ` Hongtao Liu
0 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 1:58 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:17 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> The attribute defaults to 1 for TI-mode insns of type sselog, sselog1,
> sseiadd, sseimul, and sseishft.
>
> In *<code>v8hi3 [smaxmin] and *<code>v16qi3 [umaxmin] also drop the
> similarly stray "prefix_extra" at this occasion. These two max/min
> flavors are encoded in 0f space.
Ok.
>
> gcc/
>
> * config/i386/mmx.md (*mmx_pinsrd): Drop "prefix_data16".
> (*mmx_pinsrb): Likewise.
> (*mmx_pextrb): Likewise.
> (*mmx_pextrb_zext): Likewise.
> (mmx_pshufbv8qi3): Likewise.
> (mmx_pshufbv4qi3): Likewise.
> (mmx_pswapdv2si2): Likewise.
> (*pinsrb): Likewise.
> (*pextrb): Likewise.
> (*pextrb_zext): Likewise.
> * config/i386/sse.md (*sse4_1_mulv2siv2di3<mask_name>): Likewise.
> (*sse2_eq<mode>3): Likewise.
> (*sse2_gt<mode>3): Likewise.
> (<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
> (*vec_extract<mode>): Likewise.
> (*vec_extract<PEXTR_MODE12:mode>_zext): Likewise.
> (*vec_extractv16qi_zext): Likewise.
> (ssse3_ph<plusminus_mnemonic>wv8hi3): Likewise.
> (ssse3_pmaddubsw128): Likewise.
> (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Likewise.
> (<ssse3_avx2>_pshufb<mode>3<mask_name>): Likewise.
> (<ssse3_avx2>_psign<mode>3): Likewise.
> (<ssse3_avx2>_palignr<mode>): Likewise.
> (*abs<mode>2): Likewise.
> (sse4_2_pcmpestr): Likewise.
> (sse4_2_pcmpestri): Likewise.
> (sse4_2_pcmpestrm): Likewise.
> (sse4_2_pcmpestr_cconly): Likewise.
> (sse4_2_pcmpistr): Likewise.
> (sse4_2_pcmpistri): Likewise.
> (sse4_2_pcmpistrm): Likewise.
> (sse4_2_pcmpistr_cconly): Likewise.
> (vgf2p8affineinvqb_<mode><mask_name>): Likewise.
> (vgf2p8affineqb_<mode><mask_name>): Likewise.
> (vgf2p8mulb_<mode><mask_name>): Likewise.
> (*<code>v8hi3 [smaxmin]): Drop "prefix_data16" and
> "prefix_extra".
> (*<code>v16qi3 [umaxmin]): Likewise.
>
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -3863,7 +3863,6 @@
> }
> }
> [(set_attr "isa" "noavx,avx")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "type" "sselog")
> (set_attr "length_immediate" "1")
> @@ -3950,7 +3949,6 @@
> }
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "orig,vex")
> @@ -4002,7 +4000,6 @@
> %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
> %vpextrb\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex")
> @@ -4017,7 +4014,6 @@
> "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
> "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex")
> @@ -4035,7 +4031,6 @@
> vpshufb\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,maybe_evex")
> (set_attr "btver2_decode" "vector")
> @@ -4053,7 +4048,6 @@
> vpshufb\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,maybe_evex")
> (set_attr "btver2_decode" "vector")
> @@ -4191,7 +4185,6 @@
> (set_attr "mmx_isa" "native,*")
> (set_attr "type" "mmxcvt,sselog1")
> (set_attr "prefix_extra" "1,*")
> - (set_attr "prefix_data16" "*,1")
> (set_attr "length_immediate" "*,1")
> (set_attr "mode" "DI,TI")])
>
> @@ -4531,7 +4524,6 @@
> }
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "orig,vex")
> @@ -4575,7 +4567,6 @@
> %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
> %vpextrb\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex")
> @@ -4590,7 +4581,6 @@
> "TARGET_SSE4_1"
> "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex")
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -15614,7 +15614,6 @@
> vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "isa" "noavx,noavx,avx")
> (set_attr "type" "sseimul")
> - (set_attr "prefix_data16" "1,1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,orig,vex")
> (set_attr "mode" "TI")])
> @@ -16688,8 +16687,6 @@
> vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseiadd")
> - (set_attr "prefix_data16" "1,*")
> - (set_attr "prefix_extra" "*,1")
> (set_attr "prefix" "orig,vex")
> (set_attr "mode" "TI")])
>
> @@ -16772,8 +16769,6 @@
> vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseiadd")
> - (set_attr "prefix_data16" "1,*")
> - (set_attr "prefix_extra" "*,1")
> (set_attr "prefix" "orig,vex")
> (set_attr "mode" "TI")])
>
> @@ -17001,7 +16996,6 @@
> vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "ssecmp")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix" "orig,vex")
> (set_attr "mode" "TI")])
>
> @@ -17063,7 +17057,6 @@
> vpcmpgt<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "ssecmp")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix" "orig,vex")
> (set_attr "mode" "TI")])
>
> @@ -18819,12 +18812,6 @@
> (match_test "GET_MODE_NUNITS (<MODE>mode) == 2"))
> (const_string "1")
> (const_string "*")))
> - (set (attr "prefix_data16")
> - (if_then_else
> - (and (not (match_test "TARGET_AVX"))
> - (match_test "GET_MODE_NUNITS (<MODE>mode) == 8"))
> - (const_string "1")
> - (const_string "*")))
> (set (attr "prefix_extra")
> (if_then_else
> (ior (eq_attr "prefix" "evex")
> @@ -19985,7 +19972,6 @@
> %vpextr<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "*,sse4")
> (set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1")
> (set (attr "prefix_extra")
> (if_then_else
> (eq (const_string "<MODE>mode") (const_string "V8HImode"))
> @@ -20006,7 +19992,6 @@
> "TARGET_SSE2"
> "%vpextr<PEXTR_MODE12:ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1")
> (set (attr "prefix_extra")
> (if_then_else
> (eq (const_string "<PEXTR_MODE12:MODE>mode") (const_string "V8HImode"))
> @@ -20026,7 +20011,6 @@
> "TARGET_SSE4_1"
> "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex")
> @@ -21240,7 +21224,6 @@
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseiadd")
> (set_attr "atom_unit" "complex")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,vex")
> (set_attr "mode" "TI")])
> @@ -21511,7 +21494,6 @@
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseiadd")
> (set_attr "atom_unit" "simul")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,vex")
> (set_attr "mode" "TI")])
> @@ -21639,7 +21621,6 @@
> vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseimul")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -21763,7 +21744,6 @@
> vpshufb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,maybe_evex")
> (set_attr "btver2_decode" "vector")
> @@ -21830,7 +21810,6 @@
> vpsign<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,vex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -21898,7 +21877,6 @@
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseishft")
> (set_attr "atom_unit" "sishuf")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "orig,vex")
> @@ -21992,7 +21970,6 @@
> "TARGET_SSSE3"
> "%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "maybe_vex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -24244,7 +24221,6 @@
> DONE;
> }
> [(set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,load")
> @@ -24270,7 +24246,6 @@
> "TARGET_SSE4_2"
> "%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
> [(set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "maybe_vex")
> (set_attr "length_immediate" "1")
> @@ -24298,7 +24273,6 @@
> "TARGET_SSE4_2"
> "%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
> [(set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex")
> @@ -24324,7 +24298,6 @@
> %vpcmpestri\t{%6, %4, %2|%2, %4, %6}
> %vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
> [(set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,load,none,load")
> @@ -24379,7 +24352,6 @@
> DONE;
> }
> [(set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,load")
> @@ -24401,7 +24373,6 @@
> "TARGET_SSE4_2"
> "%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
> [(set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex")
> @@ -24425,7 +24396,6 @@
> "TARGET_SSE4_2"
> "%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
> [(set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "prefix" "maybe_vex")
> @@ -24449,7 +24419,6 @@
> %vpcmpistri\t{%4, %3, %2|%2, %3, %4}
> %vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
> [(set_attr "type" "sselog")
> - (set_attr "prefix_data16" "1")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> (set_attr "memory" "none,load,none,load")
> @@ -29268,7 +29237,6 @@
> gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
> vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
> [(set_attr "isa" "noavx,avx")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -29285,7 +29253,6 @@
> gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
> vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
> [(set_attr "isa" "noavx,avx")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "<sseinsnmode>")])
> @@ -29301,7 +29268,6 @@
> gf2p8mulb\t{%2, %0| %0, %2}
> vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> - (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "<sseinsnmode>")])
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
` (9 preceding siblings ...)
2023-08-03 8:14 ` [PATCH 10/10] x86: drop redundant "prefix_data16" attributes Jan Beulich
@ 2023-08-04 2:01 ` Hongtao Liu
10 siblings, 0 replies; 22+ messages in thread
From: Hongtao Liu @ 2023-08-04 2:01 UTC (permalink / raw)
To: Jan Beulich
Cc: gcc-patches, Uros Bizjak, Hongtao Liu, Jan Hubicka, Kirill Yukhin
On Thu, Aug 3, 2023 at 4:09 PM Jan Beulich via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Having noticed various bogus uses, I thought I'd go through and audit
> them all. This is the result, with some other attributes also adjusted
> as noticed in the process. (I think this tidying also is a good thing
> to have ahead of APX further complicating insn length calculations.)
Thanks for doing this.
I'm just checking the way to modify the attribute , doesn't go detail
for those instructions encoding(I think you must know better than me).
>
> 01: "prefix_extra" tidying
> 02: "sse4arg" adjustments
> 03: "ssemuladd" adjustments
> 04: "prefix_extra" can't really be "2"
> 05: replace/correct bogus "prefix_extra"
> 06: drop stray "prefix_extra"
> 07: add (adjust) XOP insn attributes
> 08: add missing "prefix" attribute to VF{,C}MULC
> 09: correct "length_immediate" in a few cases
> 10: drop redundant "prefix_data16" attributes
>
> Jan
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2023-08-04 1:54 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-03 8:08 [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Jan Beulich
2023-08-03 8:09 ` [PATCH 01/10] x86: "prefix_extra" tidying Jan Beulich
2023-08-04 1:50 ` Hongtao Liu
2023-08-03 8:10 ` [PATCH 02/10] x86: "sse4arg" adjustments Jan Beulich
2023-08-04 1:54 ` Hongtao Liu
2023-08-03 8:10 ` [PATCH 03/10] x86: "ssemuladd" adjustments Jan Beulich
2023-08-04 1:55 ` Hongtao Liu
2023-08-03 8:11 ` [PATCH 04/10] x86: "prefix_extra" can't really be "2" Jan Beulich
2023-08-04 1:55 ` Hongtao Liu
2023-08-03 8:12 ` [PATCH 05/10] x86: replace/correct bogus "prefix_extra" Jan Beulich
2023-08-04 1:56 ` Hongtao Liu
2023-08-03 8:12 ` [PATCH 06/10] x86: drop stray "prefix_extra" Jan Beulich
2023-08-04 1:56 ` Hongtao Liu
2023-08-03 8:12 ` [PATCH 07/10] x86: add (adjust) XOP insn attributes Jan Beulich
2023-08-04 1:57 ` Hongtao Liu
2023-08-03 8:13 ` [PATCH 08/10] x86: add missing "prefix" attribute to VF{,C}MULC Jan Beulich
2023-08-04 1:57 ` Hongtao Liu
2023-08-03 8:13 ` [PATCH 09/10] x86: correct "length_immediate" in a few cases Jan Beulich
2023-08-04 1:57 ` Hongtao Liu
2023-08-03 8:14 ` [PATCH 10/10] x86: drop redundant "prefix_data16" attributes Jan Beulich
2023-08-04 1:58 ` Hongtao Liu
2023-08-04 2:01 ` [PATCH 00/10] x86: (mainly) "prefix_extra" adjustments Hongtao Liu
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