* [PATCH] i386: Fix behavior for both using AVX10.1-256 in options and function attribute
@ 2024-04-24 5:45 Haochen Jiang
2024-04-24 7:07 ` Hongtao Liu
0 siblings, 1 reply; 2+ messages in thread
From: Haochen Jiang @ 2024-04-24 5:45 UTC (permalink / raw)
To: gcc-patches; +Cc: hongtao.liu, ubizjak
Hi all,
When we are using -mavx10.1-256 in command line and avx10.1-256 in
target attribute together, zmm should never be generated. But current
GCC will generate zmm since it wrongly enables EVEX512 for non-explicitly
set AVX512. This patch will fix that issue.
Regtested on x86_64-pc-linux-gnu. Ok for trunk?
gcc/ChangeLog:
* config/i386/i386-options.cc (ix86_valid_target_attribute_tree):
Check whether AVX512F is explicitly enabled.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_1-24.c: New test.
---
gcc/config/i386/i386-options.cc | 1 +
gcc/testsuite/gcc.target/i386/avx10_1-24.c | 7 +++++++
2 files changed, 8 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-24.c
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 68a2e1c6910..ac48b5c61c4 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1431,6 +1431,7 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
scenario. */
if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256)
&& (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
+ && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F)
&& !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-24.c b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
new file mode 100644
index 00000000000..2e93f041760
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));
+
+void __attribute__((target("avx10.1-256"))) callee256(__m512 *a, __m512 *b) { *a = *b; }
--
2.31.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] i386: Fix behavior for both using AVX10.1-256 in options and function attribute
2024-04-24 5:45 [PATCH] i386: Fix behavior for both using AVX10.1-256 in options and function attribute Haochen Jiang
@ 2024-04-24 7:07 ` Hongtao Liu
0 siblings, 0 replies; 2+ messages in thread
From: Hongtao Liu @ 2024-04-24 7:07 UTC (permalink / raw)
To: Haochen Jiang; +Cc: gcc-patches, hongtao.liu, ubizjak
On Wed, Apr 24, 2024 at 1:46 PM Haochen Jiang <haochen.jiang@intel.com> wrote:
>
> Hi all,
>
> When we are using -mavx10.1-256 in command line and avx10.1-256 in
> target attribute together, zmm should never be generated. But current
> GCC will generate zmm since it wrongly enables EVEX512 for non-explicitly
> set AVX512. This patch will fix that issue.
>
> Regtested on x86_64-pc-linux-gnu. Ok for trunk?
Ok.
>
> gcc/ChangeLog:
>
> * config/i386/i386-options.cc (ix86_valid_target_attribute_tree):
> Check whether AVX512F is explicitly enabled.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/avx10_1-24.c: New test.
> ---
> gcc/config/i386/i386-options.cc | 1 +
> gcc/testsuite/gcc.target/i386/avx10_1-24.c | 7 +++++++
> 2 files changed, 8 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-24.c
>
> diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
> index 68a2e1c6910..ac48b5c61c4 100644
> --- a/gcc/config/i386/i386-options.cc
> +++ b/gcc/config/i386/i386-options.cc
> @@ -1431,6 +1431,7 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
> scenario. */
> if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256)
> && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
> + && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F)
> && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)
> && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
> opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-24.c b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
> new file mode 100644
> index 00000000000..2e93f041760
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
> +/* { dg-final { scan-assembler-not "%zmm" } } */
> +
> +typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +void __attribute__((target("avx10.1-256"))) callee256(__m512 *a, __m512 *b) { *a = *b; }
> --
> 2.31.1
>
--
BR,
Hongtao
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2024-04-24 7:07 ` Hongtao Liu
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