From: Hongtao Liu <crazylht@gmail.com>
To: Jakub Jelinek <jakub@redhat.com>
Cc: Haochen Jiang <haochen.jiang@intel.com>,
gcc-patches@gcc.gnu.org, hongtao.liu@intel.com,
Richard.Earnshaw@foss.arm.com, segher@kernel.crashing.org
Subject: Re: [PATCH] Support Intel prefetchit0/t1
Date: Wed, 9 Nov 2022 10:30:48 +0800 [thread overview]
Message-ID: <CAMZc-bzc_3CWq=YY7059=jAt6NEaeGjejSdf0w9w6uxcVn8+EQ@mail.gmail.com> (raw)
In-Reply-To: <Y2oqDhtIpzKB/XZE@tucnak>
On Tue, Nov 8, 2022 at 6:07 PM Jakub Jelinek via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> On Fri, Nov 04, 2022 at 03:46:32PM +0800, Haochen Jiang via Gcc-patches wrote:
> > We will take back the patches which add a new parameter on original
> > builtin_prefetch and implement instruction prefetch on that.
> >
> > Also we consider that since we will only do that on specific backend,
> > no need to add a new rtl for that.
> >
> > This patch will only support instructions prefetch for x86 backend.
> >
> > Regtested on x86_64-pc-linux-gnu. Ok for trunk?
>
> The gcc.target/i386/prefetchi-4.c testcase ICEs for me on i686-linux.
> Can be reproduced even on x86_64, with:
> ./cc1 -quiet -m32 -march=pentiumpro prefetchi-4.c -isystem include/
> during RTL pass: expand
> prefetchi-4.c: In function ‘prefetch_test’:
> prefetchi-4.c:11:3: internal compiler error: in gen_prefetch, at config/i386/i386.md:23913
> 11 | __builtin_ia32_prefetch (p, 0, 3, 0);
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 0x1b92416 gen_prefetch(rtx_def*, rtx_def*, rtx_def*)
> ../../gcc/config/i386/i386.md:23913
> 0x141dcf3 ix86_expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
> ../../gcc/config/i386/i386-expand.cc:13077
> 0x60deb4 expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
> ../../gcc/builtins.cc:7321
> 0x80803d expand_expr_real_1(tree_node*, rtx_def*, machine_mode, expand_modifier, rtx_def**, bool)
> ../../gcc/expr.cc:11865
> 0x7fa4d5 expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier, rtx_def**, bool)
> ../../gcc/expr.cc:9000
> 0x648c12 expand_expr
> ../../gcc/expr.h:310
> 0x651c17 expand_call_stmt
> ../../gcc/cfgexpand.cc:2831
> 0x655709 expand_gimple_stmt_1
> ../../gcc/cfgexpand.cc:3880
> 0x655d93 expand_gimple_stmt
> ../../gcc/cfgexpand.cc:4044
> 0x65e061 expand_gimple_basic_block
> ../../gcc/cfgexpand.cc:6096
> 0x660575 execute
> ../../gcc/cfgexpand.cc:6822
> Please submit a full bug report, with preprocessed source (by using -freport-bug).
> Please include the complete backtrace with any bug report.
> See <https://gcc.gnu.org/bugs/> for instructions.
>
> The ICE is on
> gcc_assert (TARGET_3DNOW);
> operands[2] = GEN_INT (3);
> The expander has
> "TARGET_3DNOW || TARGET_PREFETCH_SSE || TARGET_PRFCHW || TARGET_PREFETCHWT1"
> condition and for write handles all those different ISAs, so gcc_assert (TARGET_3DNOW);
> at the end only asserts the obvious that the expander condition had to be
> satisfied. But for !write, it only has:
> if (TARGET_PREFETCH_SSE)
> ;
> else
> {
> gcc_assert (TARGET_3DNOW);
> operands[2] = GEN_INT (3);
> }
> and here I don't understand how it can work, because if
> !TARGET_3DNOW && !TARGET_PREFETCH_SSE, but
> TARGET_PRFCHW || TARGET_PREFETCHWT1
> then it clearly ICEs. Both of the latter ISAs can be enabled/disabled
> individually without dependencies.
>
> It is unclear what exactly changed though, because the prefetch pattern
> has not changed, but it didn't ICE before that commit.
We need to check the expander condition before gen_prefetch.
>
> Jakub
>
--
BR,
Hongtao
next prev parent reply other threads:[~2022-11-09 2:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 7:46 Haochen Jiang
2022-11-07 1:28 ` Hongtao Liu
2022-11-08 10:06 ` Jakub Jelinek
2022-11-09 2:30 ` Hongtao Liu [this message]
2022-11-09 7:13 ` [PATCH] i386: Add ISA check for newly introduced prefetch builtins Haochen Jiang
2022-11-11 1:52 ` Hongtao Liu
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